74LV General description. 2. Features. 8-bit addressable latch

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1 Rev January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed for general purpose storage applications in digital systems. The is multifunctional device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE). The has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (0 to 2) and data (D) input. When operating the as an address latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. Optimized for low voltage applications:.0 V to 3.6 V ccepts TTL input levels between = 2.7 V and = 3.6 V Typical output ground bounce < 0.8 V at = 3.3 V and T amb = 25 C Typical HIGH-level output voltage (V OH ) undershoot: > 2 V at = 3.3 V and T amb =25 C Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder ESD protection: HBM JESD22-4E exceeds 2000 V MM JESD22-5- exceeds 200 V Multiple package options Specified from 40 C to+85 C and from 40 C to +25 C

2 3. Ordering information Table. Type number Ordering information Package Temperature range Name Description Version N 40 C to +25 C DIP6 plastic dual in-line package; 6 leads (300 mil) SOT38-4 D 40 C to +25 C SO6 plastic small outline package; 6 leads; SOT09- body width 3.9 mm DB 40 C to +25 C SSOP6 plastic shrink small outline package; 6 leads; SOT338- body width 5.3 mm PW 40 C to +25 C TSSOP6 plastic thin shrink small outline package; 6 leads; SOT403- body width 4.4 mm BQ 40 C to +25 C DHVQFN6 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 6 terminals; body mm SOT Functional diagram 5 3 G8 Z LE Q0 D Q Q2 Q3 0 Q4 Q5 2 Q6 Q7 MR DX 0 G ,0D C0 8R aah8 7 00aah9 2 Fig. Logic symbol Fig 2. IEC logic symbol _3 Product data sheet Rev January of 9

3 LE MR D OF 8 DECODER 8 LTCHES Q0 Q Q2 Q3 Q4 Q5 Q6 Q aah20 Fig 3. Functional diagram 5. Pinning information 5. Pinning terminal index area 0 VCC MR LE 2 5 MR Q0 4 3 D 2 Q0 Q Q LE D Q7 Q6 Q Q2 Q V () CC Q7 Q6 Q5 Q Q5 Q4 Q4 00aah7 00aah27 Transparent top view () The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP6, SO6 and (T)SSOP6 Fig 5. Pin configuration DHVQFN6 5.2 Pin description Table 2. Pin description Symbol Pin Description 0 address input 2 address input 2 3 address input 8 ground (0 V) Q[0:7] 4, 5, 6, 7, 9, 0,, 2 latch output _3 Product data sheet Rev January of 9

4 Table 2. Pin description continued Symbol Pin Description D 3 data input LE 4 latch enable input (active LOW) MR 5 conditional reset input (active LOW) 6 supply voltage 6. Functional description Table 3. Mode select table H = HIGH voltage level; L = LOW voltage level LE MR Mode L H addressable latch H H memory L L active HIGH 8-channel demultiplexer H L reset Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don t care; d = High or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared Operating modes Input Output MR LE D 0 2 Q0 Q Q2 Q3 Q4 Q5 Q6 Q7 master reset L H X X X X L L L L L L L L demultiplex (active L L d L L L Q = d L L L L L L L HIGH) decoder L L d H L L L Q = d L L L L L L (when D = H) L L d L H L L L Q = d L L L L L L L d H H L L L L Q = d L L L L L L d L L H L L L L Q = d L L L L L d H L H L L L L L Q = d L L L d L H H L L L L L L Q = d L L L d H H H L L L L L L L Q = d store (do nothing) H H X X X X q0 q q2 q3 q4 q5 q6 q7 addressable latch H L d L L L Q = d q q2 q3 q4 q5 q6 q7 H L d H L L q0 Q = d q2 q3 q4 q5 q6 q7 H L d L H L q0 q Q = d q3 q4 q5 q6 q7 H L d H H L q0 q q2 Q = d q4 q5 q6 q7 H L d L L H q0 q q2 q3 Q = d q5 q6 q7 H L d H L H q0 q q2 q3 q4 Q = d q6 q7 H L d L H H q0 q q2 q3 q4 q5 Q = d q7 H L H H H H q0 q q2 q3 q4 q5 q6 Q = d _3 Product data sheet Rev January of 9

5 7. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to (ground = 0 V). Symbol Parameter Conditions Min Max Unit supply voltage V I IK input clamping current V I < 0.5 V or V I > V [] - ±20 m I OK output clamping current V O < 0.5 V or V O > V [] - ±50 m I O output current V O = 0.5 V to ( V) - ±25 m I CC supply current - 50 m I ground current 50 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +25 C DIP6 package [2] mw SO6 package mw (T)SSOP6 package [4] mw DHVQFN6 package [5] mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] P tot derates linearly with 2 mw/k above 70 C. P tot derates linearly with 8 mw/k above 70 C. [4] P tot derates linearly with 5.5 mw/k above 60 C. [5] P tot derates linearly with 4.5 mw/k above 60 C. 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit supply voltage [] V V I input voltage 0 - V V O output voltage 0 - V T amb ambient temperature C t/ V input transition rise and fall rate =.0 V to 2.0 V ns/v = 2.0 V to 2.7 V ns/v = 2.7 V to 3.6 V ns/v [] The static characteristics are guaranteed from =.2 V to = 5.5 V, but LV devices are guaranteed to function down to =.0 V (with input levels or ). _3 Product data sheet Rev January of 9

6 9. Static characteristics Table 7. Static characteristics Voltages are referenced to (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max V IH HIGH-level input voltage =.2 V V = 2.0 V V = 2.7 V to 3.6 V V V IL LOW-level input voltage =.2 V V = 2.0 V V = 2.7 V to 3.6 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 00 µ; =.2 V V I O = 00 µ; = 2.0 V V I O = 00 µ; = 2.7 V V I O = 00 µ; = 3.0 V V I O = 6 m; = 3.0 V V V OL LOW-level output voltage V I = V IH or V IL I O = 00 µ; =.2 V V I O = 00 µ; = 2.0 V V I O = 00 µ; = 2.7 V V I O = 00 µ; = 3.0 V V I O = 6 m; = 3.0 V V I I input leakage current V I = or ; µ = 5.5 V I CC supply current V I = or ; I O = 0 ; µ = 5.5 V I CC additional supply current per input; V I = 0.6 V; µ = 2.7 V to 3.6 V C I input capacitance pf [] Typical values are measured at T amb = 25 C. _3 Product data sheet Rev January of 9

7 0. Dynamic characteristics Table 8. Dynamic characteristics = 0 V; For test circuit see Figure 2. Symbol Parameter Conditions 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max t pd propagation delay D to Qn; see Figure 8 [2] =.2 V ns = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V; C L =5pF ns = 3.0 V to 3.6 V ns t pd propagation delay n to Qn; see Figure 7 [2] =.2 V ns = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V; C L =5pF ns = 3.0 V to 3.6 V ns t pd propagation delay LE to Qn; Figure 6 [2] =.2 V ns = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V; C L =5pF ns = 3.0 V to 3.6 V ns t PHL HIGH to LOW propagation delay MR to Qn; Figure 9 =.2 V ns = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V; C L =5pF ns = 3.0 V to 3.6 V ns t W pulse width LE, HIGH or LOW; see Figure 6 = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V ns t W pulse width MR, LOW; see Figure 9 = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V ns _3 Product data sheet Rev January of 9

8 Table 8. Dynamic characteristics continued = 0 V; For test circuit see Figure 2. Symbol Parameter Conditions 40 C to +85 C 40 C to +25 C Unit t su set-up time D, n to LE; see Figure 0 and Figure =.2 V ns = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V ns t h hold time D to LE; see Figure 0 =.2 V ns = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V ns t h hold time n to LE; see Figure =.2 V ns = 2.0 V ns = 2.7 V ns = 3.0 V to 3.6 V ns C PD power dissipation capacitance C L = 50 pf; f i = MHz; V I = to [] Typical values are measured at T amb =25 C. [2] t pd is the same as t PLH and t PHL. Typical value measured at = 3.3 V. [4] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Min Typ [] Max Min Max [4] 9 pf _3 Product data sheet Rev January of 9

9 . Waveforms D input LE input V OH t W t PHL t PLH Qn output V OL 00aah2 Fig 6. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. The enable input (LE) to output (Qn) propagation delays and the enable input pulse width n input t PHL t PLH V OH Qn output V OL 00aah22 Fig 7. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. The address input (n) to output (Qn) propagation delays D input t PHL t PLH V OH Qn output V OL 00aah23 Fig 8. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. The data input (D) to output (Qn) propagation delays _3 Product data sheet Rev January of 9

10 MR input V OH t PHL t W Qn output V OL 00aah24 Fig 9. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. The conditional reset input (MR) to output (Qn) propagation delays LE input t su t su t h t h D input V OH Qn output Q = D Q = D V OL 00aah25 Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Fig 0. The data set-up and hold times for the D input to the LE input n input DDRESS STBLE t su t h LE input 00aah26 Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Fig. The address input set-up and hold times for the n inputs to the LE input _3 Product data sheet Rev January of 9

11 Table 9. Measurement points Supply voltage Input Output < 2.7 V V to 3.6 V.5 V.5 V PULSE GENERTOR V I R T D.U.T. V O C L 50 pf R L kω 00aaa663 Test data is given in Table 0. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. R L = Load resistance. C L = Load capacitance including jig and probe capacitance. Fig 2. Load circuit for switching times Table 0. Test data Supply voltage Input V I t r, t f < 2.7 V 2.5 ns 2.7 V to 3.6 V 2.7 V 2.5 ns _3 Product data sheet Rev January 2008 of 9

12 2. Package outline DIP6: plastic dual in-line package; 6 leads (300 mil) SOT38-4 D M E seating plane 2 L Z 6 e b b 9 b 2 w M c (e ) M H pin index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT 2 () () () max. b b 2 c D E e L M Z min. max. b e M E H w max mm inches Note. Plastic or metal protrusions of 0.25 mm (0.0 inch) maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT Fig 3. Package outline SOT38-4 (DIP6) _3 Product data sheet Rev January of 9

13 SO6: plastic small outline package; 6 leads; body width 3.9 mm SOT09- D E X c y H E v M Z 6 9 Q 2 ( ) 3 pin index θ L p 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT09-076E07 MS Fig 4. Package outline SOT09- (SO6) _3 Product data sheet Rev January of 9

14 SSOP6: plastic shrink small outline package; 6 leads; body width 5.3 mm SOT338- D E X c y H E v M Z 6 9 Q 2 ( ) 3 pin index 8 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E () e H E L L p Q v w y Z() max. mm θ o 8 o 0 Note. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT338- MO Fig 5. Package outline SOT338- (SSOP6) _3 Product data sheet Rev January of 9

15 TSSOP6: plastic thin shrink small outline package; 6 leads; body width 4.4 mm SOT403- D E X c y H E v M Z 6 9 pin index 2 Q ( ) 3 θ 8 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT403- MO-53 EUROPEN PROJECTION ISSUE DTE Fig 6. Package outline SOT403- (TSSOP6) _3 Product data sheet Rev January of 9

16 DHVQFN6: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 6 terminals; body 2.5 x 3.5 x 0.85 mm SOT763- D B E c terminal index area detail X terminal index area e e b 2 7 v M w M C C B y C C y L 8 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 7. Package outline SOT763- (DHVQFN6) _3 Product data sheet Rev January of 9

17 3. bbreviations Table. cronym CMOS DUT ESD HBM MM TTL bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 4. Revision history Table 2. Revision history Document ID Release date Data sheet status Change notice Supersedes _ Product data sheet - _2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN6 package added. Section 7: derating values added for DHVQFN6 package. Section 2: outline drawing added for DHVQFN6 package. _ Product specification Product specification - - _3 Product data sheet Rev January of 9

18 5. Legal information 5. Data sheet status Document status [][2] Product status Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 5.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For additional information, please visit: For sales office addresses, send an to: salesaddresses@nxp.com _3 Product data sheet Rev January of 9

19 7. Contents General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 2 January 2008 Document identifier: _3