74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

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1 Rev January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (pin ) and master reset (pin MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. ll outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. Ideal buffer for MOS microprocessor or memory Common clock and master reset Eight positive edge-triggered D-type flip-flops Complies with JEDEC standard no. 7 ESD protection: HBM EI/JESD C exceeds 2000 V MM EI/JESD exceeds 200 V Multiple package options Specified from 40 C to+85 C and from 40 C to +125 C Table 1: Quick reference data GND = 0 V; T amb = 25 C; t r = t f = 6 ns. 74HC273 t PHL, propagation delay to Qn V CC = 5 V; C L =15pF ns t PLH t PHL HIGH-to-LOW propagation V CC = 5 V; C L =15pF ns delay MR to Qn f max maximum input clock frequency V CC = 5 V; C L = 15 pf MHz

2 4. Ordering information delay to Qn V CC = 5 V; C L =15pF ns Table 1: Quick reference data continued GND = 0 V; T amb = 25 C; t r = t f = 6 ns. C i input capacitance pf C PD power dissipation capacitance per flip-flop; V I = GND to V CC [1] pf 74HCT273 t PHL, propagation t PLH t PHL HIGH-to-LOW propagation V CC = 5 V; C L =15pF ns delay MR to Qn f max maximum input clock V CC = 5 V; C L = 15 pf MHz frequency C i input capacitance pf C PD power dissipation capacitance per flip-flop; V I = GND to (V CC 1.5 V) [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D = C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. [1] pf Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC273 74HC273N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT HC273D 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT HC273DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width SOT mm 74HC273PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body SOT360-1 width 4.4 mm 74HC273BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body mm SOT HCT273 74HCT273N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT HCT273D 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 Product data sheet Rev January of 26

3 Table 2: Type number Ordering information continued Package Temperature range Name Description Version 74HCT273DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm 74HCT273PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm 74HCT273BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body mm 5. Functional diagram SOT339-1 SOT360-1 SOT D0 D1 D2 D3 D4 D5 D6 D7 FF1 TO FF8 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q MR 001aae055 Fig 1. Functional diagram 11 C1 MR 1 R D0 D1 D2 D3 D4 D5 D6 D7 11 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MR D0 4 D1 7 D2 8 D3 13 D4 14 D5 17 D6 18 D7 1D Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 mna763 mna764 Fig 2. Logic symbol Fig 3. IEC logic symbol Product data sheet Rev January of 26

4 D0 D1 D2 D3 D Q D Q D Q D Q FF1 FF2 FF3 FF4 R D R D R D R D MR Q0 Q1 Q2 Q3 D4 D5 D6 D7 D Q D Q D Q D Q FF5 FF6 FF7 FF8 R D R D R D R D Q4 Q5 Q6 Q7 001aae056 Fig 4. Logic diagram Product data sheet Rev January of 26

5 6. Pinning information 6.1 Pinning 74HC273 74HCT273 74HC273 74HCT273 terminal 1 index area Q0 MR 1 VCC Q7 MR Q0 D0 D V CC Q7 D7 D6 D0 D1 Q1 Q D7 D6 Q6 Q5 Q1 Q2 D2 D3 Q3 GND Q6 Q5 D5 D4 Q4 D2 D3 Q GND (1) GND 11 D5 D4 Q4 001aae aae053 Transparent top view Fig 5. Pin configuration DIP20, SO20, SSOP20 and TSSOP20 Fig 6. (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or output. Pin configuration DHVQFN Pin description Table 3: Pin description Symbol Pin Description MR 1 master reset input (active LOW) Q0 2 flip-flop output 0 D0 3 data input 0 D1 4 data input 1 Q1 5 flip-flop output 1 Q2 6 flip-flop output 2 D2 7 data input 2 D3 8 data input 3 Q3 9 flip-flop output 3 GND 10 ground (0 V) 11 clock input (LOW-to-HIGH, edge-triggered) Q4 12 flip-flop output 4 D4 13 data input 4 D5 14 data input 5 Product data sheet Rev January of 26

6 7. Functional description Table 3: Pin description continued Symbol Pin Description Q5 15 flip-flop output 5 Q6 16 flip-flop output 6 D6 17 data input 6 D7 18 data input 7 Q7 19 flip-flop output 7 V CC 20 supply voltage 8. Limiting values 7.1 Function table Table 4: Function table [1] Operating Control Input Output modes MR Dn Qn Reset (clear) L X X L Load 1 H h H Load 0 H I L [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH transition; = LOW-to-HIGH transition; X = don t care. Table 5: Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I > V CC V - ±20 m I OK output clamping current V O < 0.5 V or V O > - ±20 m V CC V I O output current V O = 0.5 V to (V CC V) - ±25 m I CC quiescent supply - 50 m current I GND ground current - 50 m T stg storage temperature C Product data sheet Rev January of 26

7 Table 5: Limiting values continued In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit P tot [1] For DIP20 package: P tot derates linearly with 12 mw/k above 70 C. [2] For SO20 package: P tot derates linearly with 8 mw/k above 70 C. [3] For SSOP20 and TSSOP20 packages: P tot derates linearly with 5.5 mw/k above 60 C. [4] For DHVQFN20 packages: P tot derates linearly with 4.5 mw/k above 60 C. 9. Recommended operating conditions total power dissipation DIP20 package [1] mw SO20 package [2] mw SSOP20 package [3] mw TSSOP20 package [3] mw DHVQFN20 package [4] mw 10. Static characteristics Table 6: Recommended operating conditions 74HC273 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r, t f input rise and fall time V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns 74HCT273 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r, t f input rise and fall time V CC = 4.5 V ns Table 7: Static characteristics 74HC273 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). T amb = 25 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V Product data sheet Rev January of 26

8 Table 7: Static characteristics 74HC273 continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V OL LOW-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I LI input leakage current V I = V CC or GND; V CC = 6.0 V - - ±0.1 µ I OZ OFF-state output current V I = V IH or V IL ; V O = V CC or GND; - - ±0.5 µ V CC = 6.0 V I CC quiescent supply current V I = V CC or GND; I O = 0 ; µ V CC = 6.0 V C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V OL LOW-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I LI input leakage current V I = V CC or GND; V CC = 6.0 V - - ±1.0 µ Product data sheet Rev January of 26

9 Table 7: Static characteristics 74HC273 continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). I OZ OFF-state output current V I = V IH or V IL ; V O = V CC or GND; - - ±5.0 µ V CC = 6.0 V I CC quiescent supply current V I = V CC or GND; I O = 0 ; V CC = 6.0 V µ T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL - I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V OL LOW-state output voltage V I = V IH or V IL - I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I LI input leakage current V I = V CC or GND; V CC = 6.0 V - - ±1.0 µ I OZ OFF-state output current V I = V IH or V IL ; V O = V CC or GND; - - ±10.0 µ V CC = 6.0 V I CC quiescent supply current V I = V CC or GND; I O = 0 ; V CC = 6.0 V µ Table 8: Static characteristics 74HCT273 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). T amb = 25 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4.0 m V V OL LOW-state output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4.0 m V I LI input leakage current V I = V CC or GND; V CC = 5.5 V - - ±0.1 µ Product data sheet Rev January of 26

10 Table 8: Static characteristics 74HCT273 continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). I OZ OFF-state output current V I = V IH or V IL ; V CC = 5.5 V; V O =V CC or GND per input pin; other inputs at V CC or GND; I O =0 I CC quiescent supply current V I = V CC or GND; I O = 0 ; V CC = 5.5 V I CC additional quiescent supply current V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V; I O =0 - - ±0.5 µ µ pin MR µ pin µ pin Dn µ C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4.0 m V V OL LOW-state output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4.0 m V I LI input leakage current V I = V CC or GND; V CC = 5.5 V - - ±1.0 µ I OZ OFF-state output current V I =V IH or V IL ; V CC = 5.5 V; V O =V CC or GND per input pin; other inputs at V CC or GND; I O =0 - - ±5.0 µ I CC quiescent supply current V I =V CC or GND; I O =0; V CC = 5.5 V I CC additional quiescent supply current V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V; I O = µ pin MR µ pin µ pin Dn µ T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4.0 m V V OL LOW-state output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4.0 m V I LI input leakage current V I = V CC or GND; V CC = 5.5 V - - ±1.0 µ Product data sheet Rev January of 26

11 Table 8: Static characteristics 74HCT273 continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). I OZ OFF-state output current V I =V IH or V IL ; V CC = 5.5 V; V O =V CC or GND per input pin; other inputs at V CC or GND; I O =0 I CC quiescent supply current V I =V CC or GND; I O =0; V CC = 5.5 V I CC additional quiescent supply current 11. Dynamic characteristics V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V; I O =0 - - ±10 µ µ pin MR µ pin µ pin Dn µ Table 9: Dynamic characteristics 74HC273 Voltages are referenced to GND (ground = 0 V); t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 10. delay to Qn see Figure 7 T amb = 25 C t PHL, propagation t PLH V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L =15pF ns V CC = 6.0 V ns t PHL HIGH-to-LOW propagation delay MR to Qn see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L =15pF ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width clock HIGH or LOW see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns master reset LOW see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev January of 26

12 Table 9: Dynamic characteristics 74HC273 continued Voltages are referenced to GND (ground = 0 V); t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 10. to Qn see Figure 7 t rec recovery time MR to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time Dn to see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time Dn to see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum input clock frequency see Figure 7 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 5 V; C L = 15 pf MHz V CC = 6.0 V MHz C PD power dissipation capacitance per flip-flop; V I = GND to V CC [1] pf T amb = 40 C to +85 C t PHL, propagation delay t PLH V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHL HIGH-to-LOW propagation delay MR to Qn see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width clock HIGH or LOW see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns master reset LOW see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev January of 26

13 Table 9: Dynamic characteristics 74HC273 continued Voltages are referenced to GND (ground = 0 V); t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 10. to Qn see Figure 7 t rec recovery time MR to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time Dn to see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time Dn to see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum input clock frequency see Figure 7 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz T amb = 40 C to +125 C t PHL, propagation delay t PLH V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHL HIGH-to-LOW propagation delay MR to Qn see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width clock HIGH or LOW see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns master reset LOW see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev January of 26

14 Table 9: Dynamic characteristics 74HC273 continued Voltages are referenced to GND (ground = 0 V); t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 10. t rec recovery time MR to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time Dn to see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time Dn to see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum input clock frequency see Figure 7 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D = C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Table 10: Dynamic characteristics 74HCT273 Voltages are referenced to GND (ground = 0 V); t r = t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 10. delay to Qn see Figure 7 T amb = 25 C t PHL, propagation t PLH V CC = 4.5 V ns V CC = 5 V; C L =15pF ns t PHL HIGH-to-LOW propagation delay MR to Qn see Figure 8 V CC = 4.5 V ns V CC = 5 V; C L =15pF ns t THL, output transition time V CC = 4.5 V; see Figure ns t TLH t W pulse width clock HIGH or LOW V CC = 4.5 V; see Figure ns master reset LOW V CC = 4.5 V; see Figure ns Product data sheet Rev January of 26

15 to Qn V CC = 4.5 V; see Figure ns to Qn V CC = 4.5 V; see Figure ns Table 10: Dynamic characteristics 74HCT273 continued Voltages are referenced to GND (ground = 0 V); t r = t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 10. t rec recovery time MR to V CC = 4.5 V; see Figure ns t su set-up time Dn to V CC = 4.5 V; see Figure ns t h hold time Dn to V CC = 4.5 V; see Figure ns f max maximum input clock frequency see Figure 7 V CC = 4.5 V MHz V CC = 5.0 V; C L = 15 pf MHz C PD power dissipation capacitance per flip-flop; V I = GND to (V CC 1.5 V) [1] pf T amb = 40 C to +85 C t PHL, propagation delay t PLH t PHL HIGH-to-LOW propagation delay V CC = 4.5 V; see Figure ns MR to Qn t THL, output transition time V CC = 4.5 V; see Figure ns t TLH t W pulse width clock HIGH or LOW V CC = 4.5 V; see Figure ns master reset LOW V CC = 4.5 V; see Figure ns t rec recovery time MR to V CC = 4.5 V; see Figure ns t su set-up time Dn to V CC = 4.5 V; see Figure ns t h hold time Dn to V CC = 4.5 V; see Figure ns f max maximum input clock frequency V CC = 4.5 V; see Figure MHz T amb = 40 C to +125 C t PHL, propagation delay t PLH t PHL HIGH-to-LOW propagation delay V CC = 4.5 V; see Figure ns MR to Qn t THL, output transition time V CC = 4.5 V; see Figure ns t TLH t W pulse width clock HIGH or LOW V CC = 4.5 V; see Figure ns master reset LOW V CC = 4.5 V; see Figure ns t rec recovery time MR to V CC = 4.5 V; see Figure ns t su set-up time Dn to V CC = 4.5 V; see Figure ns t h hold time Dn to V CC = 4.5 V; see Figure ns f max maximum input clock frequency V CC = 4.5 V; see Figure MHz [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D = C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; Product data sheet Rev January of 26

16 (C L V CC 2 f o ) = sum of outputs. 12. Waveforms 1/f max V I input GND t W t W t PHL t PLH Qn output V OH 90% 10% V OL t THL t TLH 001aae062 Fig 7. Measurement points are given in Table 11. V OL and V OH are typical voltage output drop that occur with the output load. Propagation delay clock input () to output (Qn), clock () pulse width, output transition time and the maximum clock pulse frequency V I MR input GND t W t rec V I input GND t PHL Qn output mna464 Fig 8. Measurement points are given in Table 11. V OL and V OH are typical voltage output drop that occur with the output load. Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR) and recovery time master reset (MR) to clock () Product data sheet Rev January of 26

17 V I input GND t su t su V I t h th Dn input GND V OH Qn output V OL mna767 Fig 9. Measurement points are given in Table 11. The shaded areas indicate when the input is permitted to change for predictable output performance. V OL and V OH are typical voltage output drop that occur with the output load. Data set-up and hold times data input (Dn) Table 11: Measurement points Type Input Output 74HC V CC 0.5V CC 74HCT V 1.3 V Product data sheet Rev January of 26

18 V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC PULSE GENERTOR VI DUT VO RL S1 open RT CL 001aad983 Test data is given in Table 12. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator C L = Load capacitance including jig and probe capacitance R L = Load resistor S1 = Test selection switch Fig 10. Load circuitry for measuring switching times Table 12: Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC273 V CC 6 ns 15 pf, 50 pf 1 kω open GND V CC 74HCT273 3 V 6 ns 15 pf, 50 pf 1 kω open GND V CC Product data sheet Rev January of 26

19 13. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 D M E seating plane 2 L 1 Z 20 e b b 1 11 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT146-1 MS-001 SC Fig 11. Package outline SOT146-1 (DIP20) Product data sheet Rev January of 26

20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L L p θ 1 e b p 10 w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E04 MS Fig 12. Package outline SOT163-1 (SO20) Product data sheet Rev January of 26

21 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ L L p 1 10 detail X e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z (1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT339-1 MO-150 EUROPEN PROJECTION ISSUE DTE Fig 13. Package outline SOT339-1 (SSOP20) Product data sheet Rev January of 26

22 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ 1 10 w M e b p L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT360-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 14. Package outline SOT360-1 (TSSOP20) Product data sheet Rev January of 26

23 DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 9 v M w M C C B y 1 C C y L 1 10 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 15. Package outline SOT764-1 (DHVQFN20) Product data sheet Rev January of 26

24 14. bbreviations Table 13: cronym CMOS DUT ESD HBM LSTTL MM MOS bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Metal Oxide Semiconductor 15. Revision history Table 14: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes Product data sheet HC_HCT273_CNV_2 Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 4 Ordering information, Section 6 Pinning information and Section 13 Package outline : dded DHVQFN package information Section 10 Static characteristics : dded from the family specification 74HC_HCT273_CNV_ Product specification Product data sheet Rev January of 26

25 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Disclaimers customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 19. Trademarks Notice ll referenced brands, product names, service names and trademarks are the property of their respective owners. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 20. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev January of 26

26 21. Contents 1 General description Features Quick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Data sheet status Definitions Disclaimers Trademarks Contact information Koninklijke Philips Electronics N.V ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 24 January 2006 Document number: Published in The Netherlands

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