74ALVCH bit universal bus transceiver (3-State)

Transcription

1 INTEGRATED CIRCUITS Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 24

2 FEATURES Complies with JEDEC standard no. 8-1A CMOS low power coumption Direct interface with TTL levels Current drive ± 24 ma at 3.0 V All inputs have bushold circuitry Output drive capability 50Ω tramission 85 C MULTIBYTE TM flow-through standard pin-out architecture Low inductance multiple and ground pi for minimum noise and ground bounce DESCRIPTION The is a high-performance CMOS product. This device is an 18-bit universal traceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directio. Data flow in each direction is controlled by output enable (OE AB and OE BA ), latch enable (LE AB and LE BA ), and clock (CP AB and CP BA ) inputs. For A-to-B data flow, the device operates in the traparent mode when LE AB is High. When LE AB is Low, the A data is latched if CP AB is held at a High or Low logic level. If LE AB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low traition of CP AB. When OE AB is High, the outputs are active. When OE AB is Low, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OE BA, LE BA and CP BA. The output enables are complimentary (OE AB is active High, and OE BA is active Low). To eure the high impedance state during power up or power down, OE BA should be tied to through a pullup resistor and OE AB should be tied to through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA = 0V; T amb = 25 C; t r = t f = 2.5 SYMBOL PARAMETER CONDITIONS TYPICAL UNIT t PHL /t PLH Propagation delay An, Bn to Bn, An = 2.5V, C L = 30pF = 3.3V, C L = 50pF C I/O Input/output capacitance 8.0 pf C I Input capacitance 4.0 pf C dissipation capacitance per PD Power acitance latch V I = to V 1 CC Outputs enabled 21 Outputs disabled 3 NOTES: 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD 2 f i + (C L 2 f o ) where: f i = input frequency in MHz; C L = output load capacitance in pf; f o = output frequency in MHz; = supply voltage in V; (C L 2 f o ) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER 56-Pin Plastic TSSOP Type II 40 C to +85 C DGG SOT364-1 pf 1998 Sep

3 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION OE AB OE AB Output enable A-to-B LE AB 2 55 CP AB 2 LE AB Latch enable A-to-B A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A A0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, A0 to A17 Data inputs/outputs 20, 21, 23, 24, 26 4, 11, 18, 25, 29, 32, 39, 46, Ground (0V) 53, 56 7, 22, 35, 50 Positive supply voltage 27 OE BA Output enable B-to-A 28 LE BA Latch enable B-to-A 30 CP BA Clock input B-to-A 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, B0 to B17 Data inputs/outputs 38, 37, 36, 34, 33, CP AB Clock input A-to-B A B11 BUS HOLD CIRCUIT A B12 A B13 A B A15 A B15 B16 Data Input To internal circuit A B17 OE BA CP BA LE BA SW00080 SW Sep 24 3

4 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) A0 A1 A2 A3 B0 B1 B2 B OE AB CP AB LE AB EN1 2C3 C A4 A5 A6 A7 B4 B5 B6 B OE AB CP BA G2 EN4 5C A8 A9 A10 B8 B9 B LE BA 28 C6 G A11 A12 B11 B A0 3 3D B0 20 A13 B D A14 A15 A16 A17 B14 B15 B16 B A1 A2 A B1 B2 B3 1 2 OE AB LE AB OE BA LE BA A4 A B4 B5 55 CP AB CP BA 30 A B6 SW00081 A B7 A B8 A B9 A B10 A B11 A B12 A B13 A B14 A B15 A B16 A B17 SW Sep 24 4

5 LOGIC DIAGRAM (one section) OE AB CP BA LE BA CP AB LE AB OE BA An C1 1D C1 1D Bn C1 C1 1D 1D 18 IDENTICAL CHANNELS SW00090 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE OEAB LEAB CPAB An Bn L H X X Z Disabled H H X H H Traparent H H X L L H X h H H X I L Latch data & display H L h H H L I L Clock data & display H L H or L X H H L H or L X L Hold data & display NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA. H = High voltage level h = High voltage level one set-up time prior to the Enable or Clock traition L = Low voltage level I = Low voltage level one set-up time prior to the Enable or Clock traition NC= No Change X = Don t care Z = High Impedance off state = High-to-Low Enable or Clock traition 1998 Sep 24 5

6 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS DC supply voltage 2.5V range (for max. speed 30 pf output load) DC supply voltage 3.3V range (for max. speed 50 pf output load) MIN LIMITS MAX V I DC Input voltage range 0 V V O DC output voltage range 0 V T amb Operating free-air temperature range C t r, t f Input rise and fall times = 2.3 to 3.0V = 3.0 to 3.6V UNIT V /V ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to (ground = 0V) SYMBOL PARAMETER CONDITIONS RATING UNIT DC supply voltage 0.5 to +4.6 V I IK DC input diode current V I 0 50 ma V I DC input voltage For control pi to +4.6 For data inputs to +0.5 I OK DC output diode current V O or V O 0 50 ma V O DC output voltage Note to +0.5 V I O DC output source or sink current V O = 0 to 50 ma I, I CC DC or current 100 ma T stg Storage temperature range 65 to +150 C P TOT Power dissipation per package plastic thin-medium-shrink (TSSOP) For temperature range: 40 to +125 C above +55 C derate linearly with 8 mw/k 600 NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. V mw 1998 Sep 24 6

7 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditio. Voltage are referenced to (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40 C to +85 C UNIT V IH V IL V OH HIGH level Input voltage LOW level Input voltage HIGH level output voltage MIN TYP 1 MAX = 2.3 to 2.7V = 2.7 to 3.6V = 2.3 to 2.7V = 2.7 to 3.6V = 2.3 to 3.6V; V I = V IH or V IL ; I O = 100µA = 2.3V; V I = V IH or V IL ; I O = 6mA = 2.3V; V I = V IH or V IL ; I O = 12mA = 2.7V; V I = V IH or V IL ; I O = 12mA = 3.0V; V I = V IH or V IL ; I O = 12mA = 3.0V; V I = V IH or V IL; I O = 24mA = 2.3 to 3.6V; V I = V IH or V IL ; I O = 100µA 0.20 V = 2.3V; V I = V IH or V IL ; I O = 6mA V V OL LOW level output voltage = 2.3V; V I = V IH or V IL ; I O = 12mA = 2.7V; V I = V IH or V IL ; I O = 12mA V = 3.0V; V I = V IH or V IL; I O = 24mA V V V I I Input leakage current =23to36V; V; V I = or µa I OZ 3-State output OFF-state current = 2.7 to 3.6V; V I = V IH or V IL ; V O = or µa I CC Quiescent supply current = 2.3 to 3.6V; V I = or ; I O = µa I CC Additional quiescent supply current = 2.3V to 3.6V; V I = 0.6V; I O = µa I BHL I BHH Bus hold LOW sustaining current Bus hold HIGH sustaining current = 2.3V; V I = 0.7V 2 45 = 3.0V; V I = 0.8V = 2.3V; V I = 1.7V 2 45 = 3.0V; V I = 2.0V I BHLO Bus hold LOW overdrive current = 3.6V µa I BHHO Bus hold HIGH overdrive current = 3.6V µa NOTES: 1. All typical values are at T amb = 25 C. 2. Valid for data inputs of bus hold parts. µa µa 1998 Sep 24 7

8 AC CHARACTERISTICS FOR = 2.3V TO 2.7V RANGE = 0V; t r = t f 2.0; C L = 30pF LIMITS SYMBOL PARAMETER WAVEFORM = 2.5V ± 0.2V UNIT t PHL /t PLH t PZH /t PZL t PHZ /t PLZ Propagation delay An, Bn to Bn, An Propagation delay LE AB, LE BA to Bn, An Propagation delay CP AB, CP BA to Bn, An 3-State output enable time OE BA to An 3-State output enable time OE AB to Bn 3-State output enable time OE BA to An 3-State output enable time OE AB to Bn MIN TYP 1 MAX , Pulse width HIGH LE AB, LE BA t W 2 Pulse width HIGH or LOW CP AB, CP BA Set-up time An, Bn to CP AB, CP BA t SU 4 Set-up time An, Bn to LE AB, LE BA Hold time An, Bn to CP AB, CP BA t h 4 Hold time An, Bn to LE AB, LE BA f MAX Maximum clock frequency MHz NOTE: 1. All typical values are at = 2.5V and T amb = 25 C Sep 24 8

9 AC CHARACTERISTICS FOR = 3.0V TO 3.6V RANGE AND = 2.7V = 0V; t r = t f = 2.5; C L = 50pF LIMITS SYMBOL PARAMETER WAVEFORM = 3.3V ±0.3V = 2.7V UNIT t PHL /t PLH t PZH /t PZL t PHZ /t PLZ Propagation delay An, Bn to Bn, An Propagation delay LE AB, LE BA to Bn, An Propagation delay CP AB, CP BA to Bn, An 3-State output enable time OE BA to An 3-State output enable time OE AB to Bn 3-State output disable time OE BA to An 3-State output disable tiime OE AB to Bn MIN TYP 1 MAX MIN TYP MAX , LE pulse width LE AB, LE BA to CP AB, CP BA t W 2 LE pulse width HIGH or LOW CP AB, CP BA Set-up time An, Bn to CP AB, CP BA t SU 4 Set-up time An, Bn to LE AB, LE BA Hold time An, Bn to CP AB, CP BA t h 4 Hold time An, Bn to LE AB, LE BA f MAX Maximum clock frequency MHz NOTE: 1. All typical values are at = 3.3V and T amb = 25 C Sep 24 9

10 AC WAVEFORMS = 2.3 TO 2.7 V RANGE 1. = 0.5 V 2. V X = V OL V 3. V Y = V OH 0.15V 4. V I = 5. V OL and V OH are the typical output voltage drop that occur with the output load. = 3.0 TO 3.6 V RANGE AND = 2.7 V 1. = 1.5 V 2. V X = V OL + 0.3V 3. V Y = V OH 0.3V 4. V I = 2.7 V 5. V OL and V OH are the typical output voltage drop that occur with the output load. OE AB INPUT OE BA INPUT OUTPUT LOW-to-OFF OFF-to-LOW V OL t PLZ V X t PZL V I t PHZ t PZH An, Bn INPUT V OH OUTPUT HIGH-to-OFF OFF-to-HIGH V Y V OH t PHL t PLH outputs enabled outputs disabled outputs enabled Bn, An OUTPUT V OL SW00083 Waveform 1. Input (An, Bn) to output (Bn, An) propagation times V I CP XX INPUT LE XX INPUT V OH An, Bn OUTPUT t W t PHL t PLH SW00085 Waveform 3. 3-State enable and disable times V I ÉÉÉ ÉÉ An, Bn INPUT V I CP XX, LE XX INPUT t SU t h ÉÉÉÉ ÉÉÉÉÉ ÉÉÉ ÉÉÉ NOTE: The uhaded areas indicate when the input is permitted to change for predictable output performance. SW00093 Waveform 4. Data set-up and hold times for the An and Bn inputs to the LE AB, LE BA, CP AB and CP BA inputs t SU t h V OL SW00084 Waveform 2. Latch enable input (LE AB, LE BA ) and clock pulse input (CP AB, CP BA ) to output (An, Bn) propagation delays and latch enable pulse width 1998 Sep 24 10

11 TEST CIRCUIT S 1 2 * Open PULSE GENERATOR V I D.U.T. V O R L = 500 Ω R T C L R L = 500 Ω Test Circuit for switching times DEFINITIONS R L = Load resistor C L = Load capacitance includes jig and probe capacitance R T = Termination resistance should be equal to Z OUT of pulse generators. SWITCH POSITION TEST S 1 V I t PLH/ t PHL Open < 2.7V t PLZ/ t PZL V 2.7V t PHZ/ t PZH Waveform 5. Load circuitry for switching times SV Sep 24 11

12 18 Bit Universal Bus Traceiver TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT Sep 24 12

13 18 Bit Universal Bus Traceiver NOTES 1998 Sep 24 13

14 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contai the design target or goal specificatio for product development. Specificatio may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai Final Specificatio. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: Document order number: Aug 31 14

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