74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger

Transcription

1 INTEGRATED IRUITS positive-edge trigger Supersedes data of 1996 Nov 07 I24 Data andbook 1998 Apr 20

2 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0 to 3.6V Accepts TT input levels between V = 2.7V and V = 3.6V Typical V OP (output ground bounce) V = 3.3V, T amb = 25 Typical V OV (output V O undershoot) V = 3.3V, T amb = 25 Output capability: standard I category: flip-flops DESRIPTION The is a low-voltage Si-gate MOS device and is pin and function compatible with 74/T74. The is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (S D ) and (R D ) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active OW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the OW-to-IG transition of the clock pulse. The D inputs must be stable one set-up time prior to the OW-to-IG clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUIK REFERENE DATA GND = 0V; T amb = 25 ; t r =t f 2.5 ns SYMBO PARAMETER ONDITIONS TYPIA UNIT t P /t P Propagation delay np to nq, nq ns D to nq, nq nr D to nq, nq = 15pF V = 3.3V f max Maximum clock frequency = 15pF V = 3.3V 76 Mz I Input capacitance 3.5 pf PD Power dissipation capacitance per flip-flop Notes 1 and 2 24 pf NOTES: 1. PD is used to determine the dynamic power dissipation (P D in µw) P D = PD V 2 x f i ( V 2 f o ) where: f i = input frequency in Mz; = output load capacitance in pf; f o = output frequency in Mz; V = supply voltage in V; ( V 2 f o ) = sum of the outputs. 2. The condition is V I = GND to V ORDERING INFORMATION PAKAGES TEMPERATURE RANGE OUTSIDE NORT AMERIA NORT AMERIA PKG. DWG. # 14-Pin Plastic DI 40 to +125 N N SOT Pin Plastic SO 40 to +125 D D SOT Pin Plastic SSOP Type II 40 to +125 DB DB SOT Pin Plastic TSSOP Type I 40 to +125 PW PW D SOT ns PIN DESRIPTION PIN NUMBER SYMBO FUNTION 1, 13 1R D, 2R D Asynchronous reset-direct input (active-ow) 2, 12 1D, 2D Data inputs 3, 11 1P, 2P lock input (OW-to-IG), edge-triggered) 4, 10 1S D, 2S D Asynchronous set-direct input (active-ow) 5, 9 1Q, 2Q True flip-flop outputs 6, 8 1Q, 2Q omplement flip-flop outputs 7 GND Ground (0V) 14 V Positive supply voltage FUNTION TABE INPUTS OUTPUTS S D R D P D Q Q X X X INPUTS OUTPUTS S D R D P D Q n+1 Q n+1 = IG voltage level = OW voltage level X = don t care = OW-to-IG P transition Q n+1 = state after the next OW-to-IG P transition X X X 1998 Apr

3 PIN ONFIGURATION OGI SYMBO 1R D 1 14 V 1D R D S D 2S D 1P 1S D 1Q D 2P 2S D S 2 1D D 1Q 5 D Q 12 2D 2Q 9 3 1P P FF 11 2P Q 1Q 6 2Q 8 1Q 6 9 2Q R D GND 7 8 2Q 1R D 2R D 1 13 SV00330 SV00331 OGI SYMBO (IEEE/IE) FUNTIONA DIAGRAM S 1 1D R S D 1D 1P S D D Q P FF1 Q 1Q 5 1Q S 2 2D R 9 8 SV R D 2S D 2D 2P R D S D D Q P FF2 2Q 9 Q 2Q R D R D SV Apr 20 3

4 OGI DIAGRAM (ONE FIP-FOP) Q D Q R D S D P SV00334 REOMMENDED OPERATING ONDITIONS SYMBO PARAMETER ONDITIONS MIN TYP. MAX UNIT V D supply voltage See Note V V I Input voltage 0 V V V O Output voltage 0 V V T amb t r, t f Operating ambient temperature range in free air Input rise and fall times except for Schmitt-trigger inputs See D and A characteristics V = 1.0V to 2.0V V = 2.0V to 2.7V V = 2.7V to 3.6V V = 3.6V to 5.5V NOTE: 1. The V is guaranteed to function down to V = 1.0V (input levels GND or V ); D characteristics are guaranteed from V = 1.2V to V = 5.5V. ABSOUTE MAXIMUM RATINGS 1, 2 In accordance with the Absolute Maximum Rating System (IE 134) Voltages are referenced to GND (ground = 0V) SYMBO PARAMETER ONDITIONS RATING UNIT V D supply voltage 0.5 to +7.0 V ±I IK D input diode current V I < 0.5 or V I > V + 0.5V 20 ma ±I OK D output diode current V O < 0.5 or V O > V + 0.5V 50 ma ±I O D output source or sink current standard outputs 0.5V < V O < V + 0.5V 25 ns/v ma ±I GND, ±I D V or GND current for types with standard outputs 50 ma T stg Storage temperature range 65 to +150 Power dissipation per package for temperature range: 40 to +125 plastic DI above +70 derate linearly with 12mW/K 750 P tot t plastic mini-pack (SO) above +70 derate linearly with 8 mw/k 500 plastic shrink mini-pack (SSOP and TSSOP) above +60 derate linearly with 5.5 mw/k 400 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. mw 1998 Apr 20 4

5 D ARATERISTIS Over recommended operating conditions voltages are referenced to GND (ground = 0V) IMITS SYMBO PARAMETER TEST ONDITIONS -40 to to +125 UNIT MIN TYP 1 MAX MIN MAX V = 1.2V IG level Input V = 2.0V V I voltage V = 2.7 to 3.6V V V = 4.5 to 5.5V 0.7*V 0.7*V V = 1.2V OW level Input V = 2.0V V I voltage V = 2.7 to 3.6V V V O V O V O V O I I I IG level output voltage; all outputs uts V = 4.5 to *V 0.3*V V = 1.2V; V I = V I or V I; I O = 100µA 1.2 V = 2.0V; V I = V I or V I; I O = 100µA V = 2.7V; V I = V I or V I; I O = 100µA V V = 3.0V; V I = V I or V I; I O = 100µA V = 4.5V;V I = V I or V I; I O = 100µA IG level output voltage; V = 3.0V;V I = V I or V I; I O = 6mA STANDARD outputs V = 4.5V;V I = V I or V I; I O = 12mA OW level output voltage; all outputs uts V = 1.2V; V I = V I or V I; I O = 100µA 0 V = 2.0V; V I = V I or V I; I O = 100µA V = 2.7V; V I = V I or V I; I O = 100µA V V = 3.0V;V I = V I or V I; I O = 100µA V = 4.5V;V I = V I or V I; I O = 100µA OW level output voltage; V = 3.0V;V I = V I or V I; I O = 6mA STANDARD outputs V = 4.5V;V I = V I or V I; I O = 12mA Input leakage current Quiescent supply current; flip-flops V = 5.5V; V I = V or GND µa V = 5.5V; V I = V or GND; I O = µa I Additional quiescent supply V = 2.7V to 3.6V; V I = V 0.6V µa current per input NOTE: 1. All typical values are measured at T amb = 25. V V 1998 Apr 20 5

6 A ARATERISTIS GND = 0V; t r = t f 2.5ns; = 50pF; R = 1KΩ SYMBO PARAMETER WAVEFORM t P/ t P t P/ t P t P/ t P t W t W t rem t su t h f max Propagation delay np to nq, nq Propagation delay ns D to nq, nq Propagation delay nr D to nq, nq lock pulse width IG to OW Set or reset pulse width OW Removal time set or reset Set-up time nd to np old time nd to np Maximum clock pulse frequency ONDITION IMITS 40 to +85 IMITS 40 to +125 UNIT V (V) MIN TYP 1 MAX MIN MAX Figures, 1, ns 3.0 to to Figures 2, ns 3.0 to to Figures 2, ns Figure 1 Figure to to to to to to Figure ns 3.0 to to Figure ns 3.0 to to Figure ns Figure to to to to NOTE: 1. Unless otherwise stated, all typical values are at T amb = Typical value measured at V = 3.3V. 3. Typical value measured at V = 5.0V. ns ns Mz 1998 Apr 20 6

7 A WAVEFORMS = 1.5V at V 2.7V 3.6V = 0.5 * V at V 2.7V and 4.5V V O and V O are the typical output voltage drop that occur with the output load. TEST IRUIT V cc V l V O V I nd INPUT ÏÏ VM ÏÏÏÏ ÏÏ PUSE GENERATOR R T D.U.T. 50pF R = 1k GND t h t h t su t su Test ircuit for Outputs V I np INPUT GND t W 1/f max DEFINITIONS R = oad resistor = oad capacitance includes jig and probe capacitiance R T = Termination resistance should be equal to Z OUT of pulse generators. V O t P t P TEST V V I nq OUTPUT t P/ t P < 2.7V V V O V 2.7V V O nq OUTPUT V O t P t P 4.5 V V SV00902 Figure 3. oad circuitry for switching times SV00335 Figure 1.The clock (np) to output (nq, nq) propagation delays, the clock pulse width, the nd to np setup times, the np to nd hold times, the output transition times and the maximum clock pulse frequency NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. V I np INPUT GND V I t rem ns D INPUT GND V I t W t W nr D INPUT GND V O nq OUTPUT t P t P V O V O nq OUTPUT V O t P t P SV00336 Figure 2.The set (ns D ) and reset (nr D ) input to output (nq, nq) propagation delays, the set and reset pulse widths and the nr D to np removal time 1998 Apr 20 7

8 DIP14: plastic dual in-line package; 14 leads (300 mil) SOT Apr 20 8

9 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT Apr 20 9

10 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT Apr 20 10

11 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT Apr 20 11

12 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America orporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. IFE SUPPORT APPIATIONS Philips Semiconductors and Philips Electronics North America orporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America orporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America orporation customers using or selling Philips Semiconductors and Philips Electronics North America orporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America orporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, alifornia Telephone opyright Philips Electronics North America orporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: Document order number: