3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state

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1 with 30 Ω termination resistors; 3-state Rev January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The is designed with 30 Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitters. This device is a 16-bit edge-triggered -type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the outputs of the flip-flop take on the logic levels set up at the inputs. 16-bit edge-triggered flip-flop 3-state buffers Output capability: +12 ma and 12 ma TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Outputs include series resistance of 30 Ω making external resistors unnecessary Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection exceeds 500 ma per JES78 ES protection: MIL ST 883 method 3015: exceeds 2000 V Machine model: exceeds 200 V

2 3. uick reference data 4. Ordering information Table 1: uick reference data T amb =25 C. Symbol Parameter Conditions Min Typ Max Unit t PLH, t PHL propagation delay C L = 50 pf; V CC = 3.3 V ns ncp to nn C I input capacitance V I = 0 V or 3.0 V pf C O output capacitance outputs disabled; pf V O = 0 V or 3.0 V I CC supply current outputs disabled; V CC = 3.6 V µa Table 2: Type number Ordering information Package Temperature range Name escription Version GG 40 C to +85 C TSSOP48 plastic thin shrink small outline package; SOT leads; body width 6.1 mm L 40 C to +85 C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 Product data sheet Rev January of 17

3 5. Functional diagram CP 1OE CP 2OE OE 1CP 2OE 2CP EN 48 C3 24 2EN 25 C aaa aac369 Fig 1. Logic symbol Fig 2. IEC logic symbol n0 n1 n2 n3 n4 n5 n6 n7 CP CP CP CP CP CP CP CP ncp noe n0 n1 n2 n3 n4 n5 n6 n7 001aac371 Fig 3. Logic diagram Product data sheet Rev January of 17

4 V CC 27 Ω output 27 Ω 001aac372 Fig 4. Output schematic (one output) 6. Pinning information 6.1 Pinning 1OE CP GN 4 45 GN V CC 7 42 V CC GN GN GN GN V CC V CC GN GN OE CP 001aac370 Fig 5. Pin configuration Product data sheet Rev January of 17

5 6.2 Pin description Table 3: Pin description Symbol Pin escription 1OE 1 output enable input (active LOW) 10 2 data output 11 3 data output GN 4 ground (0 V) 12 5 data output 13 6 data output V CC 7 supply voltage 14 8 data output 15 9 data output GN 10 ground (0 V) data output data output data output data output GN 15 ground (0 V) data output data output V CC 18 supply voltage data output data output GN 21 ground (0 V) data output data output 2OE 24 output enable input (active LOW) 2CP 25 clock pulse input (active rising edge) data input data input GN 28 ground (0 V) data input data input V CC 31 supply voltage data input data input GN 34 ground (0 V) data input data input data input data input GN 39 ground (0 V) Product data sheet Rev January of 17

6 7. Functional description Table 3: Pin description Symbol Pin escription data input data input V CC 42 supply voltage data input data input GN 45 ground (0 V) data input data input 1CP 48 clock pulse input (active rising edge) 8. Limiting values 7.1 Function table Table 4: Function table [1] Operating mode Input Internal register Output noe ncp nn n0 to n7 Load and read L l L L register L h H H Hold L NC X NC NC isable outputs H NC X NC Z H nn nn Z [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; NC = no change; X = don t care; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition. Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GN (ground = 0V) Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input diode current V I < 0 V 50 - ma V I input voltage [1] V I OK output diode current V O < 0 V 50 - ma V O output voltage output in OFF-state or HIGH-state [1] V Product data sheet Rev January of 17

7 Table 5: Limiting values continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GN (ground = 0V) Symbol Parameter Conditions Min Max Unit I O output current output in LOW-state ma output in HIGH-state - 64 ma T stg storage temperature C T j junction temperature [2] 150 C [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal 9. Recommended operating conditions Table 6: 10. Static characteristics Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage V V I input diode voltage V V IH HIGH-level input voltage V V IL LOW-level input voltage V I OH HIGH-level output ma current I OL LOW-level output current ma t/ V input transition rise or fall outputs enabled ns/v rate T amb ambient temperature C Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C [1] V IK input clamp voltage V CC = 2.7 V; I IK = 18 ma V V OH HIGH-level output voltage V CC = 3.0 V; I OH = 12 ma V V OL LOW-level output voltage V CC = 3.0 V; I OL = 12 ma V V RST power-up output low voltage V CC = 3.6 V; I O = 1 ma; [2] V V I = GN or V CC I LI input leakage current control pins V CC = 3.6 V; V I =V CC or GN ±1 µa V CC = 0 V or 3.6 V; V I = 5.5 V µa I/O data pins V CC = 3.6 V; V I = V CC µa V CC = 3.6 V; V I = 0 V µa I OFF output off current V CC = 0 V; V I or V O = 0 V to 4.5 V ±100 µa Product data sheet Rev January of 17

8 Table 7: Static characteristics continued At recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit I HOL bus hold current inputs V CC = 3 V; V I = 0.8 V [4] µa V CC = 3 V; V I = 2.0 V µa V CC = 0 V to 3.6 V; V I = 3.6 V ± µa I EX external current into output output in HIGH-state when µa V O >V CC ; measured at V O = 5.5 V and V CC = 3.0 V I PU, I P power-up or power-down 3-state output current V CC 1.2 V; V O = 5.0 V to V CC ; V I = GN or V CC ; noe and noe = don t care [5] - 1 ±100 µa µa µa I OZH 3-state output HIGH current V CC = 3.6 V; V O = 3.0 V; V I =V IH or V IL I OZL 3-state output LOW current V CC = 3.6 V; V O = 0.5 V; V I =V IH or V IL I CC quiescent supply current V CC = 3.6 V; V I = GN or V CC ; I O =0A outputs HIGH ma outputs LOW ma outputs disabled [6] ma I CC additional supply current per input pin V CC = 3 V to 3.6 V; one input at V CC 0.6 V; other inputs at V CC or GN [7] ma C I input capacitance V I = 0 V or 3.0 V pf C O output capacitance outputs disabled; V O = 0 V or 3.0 V pf [1] All typical values are at V CC = 3.3 V and T amb = 25 C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at V CC or GN. [4] This is the bus-hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any V CC between 0 V and 1.2 V with a transition time of up to 10 ms. From V CC = 1.2 V to V CC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for T amb = 25 C only. [6] I CC is measured with outputs pulled to V CC or GN. [7] This is the increase in supply current for each input at the specified voltage level other than V CC or GN. Table 8: ynamic characteristics GN = 0 V; t r = t f = 2.5 ns; C L = 50 pf; R L = 500 Ω; for test circuit see Figure 10. Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C [1] f max maximum clock frequency V CC = 3.3 V ± 0.3 V; see Figure MHz t PLH propagation delay ncp to nn see Figure 6 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns Product data sheet Rev January of 17

9 Table 8: ynamic characteristics continued GN = 0 V; t r = t f = 2.5 ns; C L = 50 pf; R L = 500 Ω; for test circuit see Figure 10. Symbol Parameter Conditions Min Typ Max Unit t PHL t PZH t PZL t PHZ t PLZ propagation delay ncp to nn output enable time to HIGH-level output enable time to LOW-level output disable time from HIGH-level output disable time from LOW-level [1] All typical values are at V CC = 3.3 V and T amb = 25 C. see Figure 6 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns see Figure 7 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns see Figure 8 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns see Figure 7 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns see Figure 8 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns Table 9: ynamic characteristics set-up requirements GN = 0 V; t r = t f = 2.5 ns; C L = 50 pf; R L = 500 Ω. Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C [1] t su(h), t su(l) set-up time nn to ncp see Figure 9 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns t h(h), t h(l) hold time nn to ncp see Figure 9 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns t W(H) ncp pulse width HIGH see Figure 6 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns t W(L) ncp pulse width LOW see Figure 6 V CC = 3.3 V ± 0.3 V ns V CC = 2.7 V ns [1] All typical values are at V CC = 3.3 V and T amb = 25 C. Product data sheet Rev January of 17

10 12. Waveforms 1/f max ncp 2.7 V 0 V t W(H) t PHL t W(L) t PLH V OH nn V OL 001aac373 Fig 6. = 1.5 V; V I = GN to 3.0 V. V OL and V OH are typical voltage output drop that occur with the output load. Propagation delay clock input to output, clock pulse width and maximum clock frequency 2.7 V noe t PZH t PHZ nn V OH V OH 0.3 V 0 V 001aac374 Fig 7. = 1.5 V; V I = GN to 3.0 V. V OH is typical voltage output drop that occur with the output load. 3-state output enable time to HIGH-level and output disable time from HIGH-level 2.7 V noe t PZL t PLZ 3.0 V nn V OL V V OL 001aac375 Fig 8. = 1.5 V; V I = GN to 3.0 V. V OL is typical voltage output drop that occur with the output load. 3-state output enable time to LOW-level and output disable time from LOW-level Product data sheet Rev January of 17

11 2.7 V nn 0 V ncp t su(h) t h(h) t su(l) t h(l) 2.7 V 0 V 001aac376 Fig 9. = 1.5 V; V I = GN to 3.0 V. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. ata set-up and hold times V I negative pulse 0 V V I positive pulse 0 V t W 90 % 90 % 10 % t THL (t f ) t TLH (t r ) t TLH (t r ) t THL (t f ) 90 % 10 % 10 % t W 001aac221 = 1.5 V. a. Input pulse definition V EXT V CC PULSE GENERATOR V I.U.T. V O R L RT C L R L mna616 Test data is given in Table 10. efinitions: R L = Load resistor. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. V EXT = Test voltage for switching times. b. Test circuit Fig 10. Load circuitry for switching times Product data sheet Rev January of 17

12 Table 10: Test data Supply Repetition rate Input Load V EXT voltage t W t r, t f C L R L t PHZ, t PZH t PLZ, t PZL t PLH, t PHL 2.7 V 10 MHz 500 ns 2.5 ns 50 pf 500 Ω GN 6 V open Product data sheet Rev January of 17

13 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E A X y c H E v M A Z A 2 A 1 (A ) 3 A pin 1 index 1 24 L detail X L p θ e bp w M mm scale IMENSIONS (mm are the original dimensions). A UNIT A 1 A 2 A 3 b p c (1) E (2) e H E L L p v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEITA EUROPEAN PROJECTION ISSUE ATE SOT362-1 MO Fig 11. Package outline SOT362-1 (TSSOP48) Product data sheet Rev January of 17

14 SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 E A X c y H E v M A Z A 2 A 1 (A ) 3 A pin 1 index θ L p 1 24 L e b p w M detail X mm scale IMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c (1) E (1) e H E L L p v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEITA EUROPEAN PROJECTION ISSUE ATE SOT370-1 MO Fig 12. Package outline SOT370-1 (SSOP48) Product data sheet Rev January of 17

15 14. Revision history Table 11: Revision history ocument I Release date ata sheet status Change notice oc. number Supersedes _ Product data sheet _2 Modifications: The format of this data sheet is redesigned to comply with the current presentation and information standard of Philips Semiconductors. Section 2 Features : Changed JEEC Std 17 into JES78 Table 1 uick reference data :Changed t PLH and t PHL propagation delays ncp to nn to 3.0 ns Table 9 ynamic characteristics set-up requirements : Changed the minimum values of t h(h) and t h(l) hold time nn to ncp to 0.8 ns _ Product specification _1 _ Product specification Product data sheet Rev January of 17

16 15. ata sheet status Level ata sheet status [1] Product status [2] [3] efinition I Objective data evelopment This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data ualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. efinitions 17. isclaimers Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev January of 17

17 19. Contents 1 General description Features uick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics ynamic characteristics Waveforms Package outline Revision history ata sheet status efinitions isclaimers Contact information Koninklijke Philips Electronics N.V All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. ate of release: 17 January 2005 ocument number: Published in The Netherlands

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