74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

Transcription

1 Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V CC. Input levels: For 74HC574: CMOS level For 74HCT574: TTL level 3-state non-inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common 3-state output enable input Complies with JEDEC standard no. 7 A Multiple package options ESD protection: HBM JESD22-A114F exceeds V MM JESD22-A115-A exceeds 200 V Specified from 40 C to+85c and from 40 C to+125c Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC574D 40 C to +125 C SO20 plastic small outline package; 20 leads; SOT HCT574D 74HC574DB 40 C to +125 C SSOP20 body width 7.5 mm plastic shrink small outline package; 20 leads; SOT HCT574DB 74HC574PW 74HCT574PW 40 C to +125 C TSSOP20 body width 5.3 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

2 4. Functional diagram Fig 1. Functional diagram Fig 2. Logic diagram Product data sheet Rev. 7 4 March of 18

3 Fig 3. Logic symbol Fig 4. IEC logic symbol 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SO20, SSOP20 and TSSOP Pin description Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) CP 11 clock input (LOW-to-HIGH, edge triggered) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output V CC 20 supply voltage Product data sheet Rev. 7 4 March of 18

4 6. Functional description Table 3. Function table [1] Operating mode Input Internal Output OE CP Dn flip-flop Qn Load and read register L l L L L h H H Load register and disable output H l L Z H h H Z [1] H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC +0.5 V - 20 ma I OK output clamping current V O < 0.5 V or V O >V CC +0.5V - 20 ma I O output current V O = 0.5 V to (V CC +0.5V) - 35 ma I CC supply current ma I GND ground current - 70 ma T stg storage temperature C P tot total power dissipation SO20, SSOP20 and TSSOP20 packages [1] mw [1] For SO20: P tot derates linearly with 8 mw/k above 70 C. For SSOP20 and TSSOP20 packages: P tot derates linearly with 5.5 mw/k above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC574 74HCT574 Unit Min Typ Max Min Typ Max V CC supply voltage V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature C Product data sheet Rev. 7 4 March of 18

5 Table 5. Recommended operating conditions continued Voltages are referenced to GND (ground = 0 V) continued Symbol Parameter Conditions 74HC574 74HCT574 Unit Min Typ Max Min Typ Max t/v input transition rise and fall rate V CC = 2.0 V ns/v V CC = 4.5 V ns/v V CC = 6.0 V ns/v 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC574 V IH HIGH-level V CC = 2.0 V V input voltage V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level V CC = 2.0 V V input voltage V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 A; V CC = 2.0 V V I O = 20 A; V CC = 4.5 V V I O = 20 A; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =20A; V CC = 2.0 V V I O =20A; V CC = 4.5 V V I O =20A; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I I input leakage current V I =V CC or GND; V CC =6.0V A I OZ OFF-state output current V I =V IH or V IL ; V CC =6.0V; V O =V CC or GND I CC supply current V I =V CC or GND; I O =0A; V CC =6.0V C I input capacitance A A pf Product data sheet Rev. 7 4 March of 18

6 Table 6. Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HCT574 V IH HIGH-level input voltage V IL LOW-level input voltage V OH HIGH-level output voltage V OL I I I OZ LOW-level output voltage input leakage current OFF-state output current V CC = 4.5 V to 5.5 V V V CC = 4.5 V to 5.5 V V V I =V IH or V IL ; V CC =4.5V I O = 20 A V I O = 6 ma V V I =V IH or V IL ; V CC =4.5V I O =20A V I O = 6.0 ma V V I =V CC or GND; A V CC =5.5V V I =V IH or V IL ; V CC =5.5V; A V O =V CC or GND A I CC supply current V I =V CC or GND; I O =0A; V CC =5.5V I CC C I additional supply current input capacitance V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V; I O =0A per input pin; Dn inputs A per input pin; OE input A per input pin; CP input A pf Product data sheet Rev. 7 4 March of 18

7 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 9. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC574 t pd propagation CP to Qn; see Figure 6 [1] delay V CC = 2.0 V ns V CC = 4.5 V ns V CC =5V; C L =15pF ns V CC = 6.0 V ns t en enable time OE to Qn; see Figure 8 [2] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t dis disable time OE to Qn; see Figure 8 [3] t t transition time V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Qn; see Figure 6 [4] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width CP HIGH or LOW; see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time Dn to CP; see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time Dn to CP; see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum CP; see Figure 6 frequency V CC = 2.0 V MHz V CC = 4.5 V MHz V CC =5V; C L = 15 pf MHz V CC = 6.0 V MHz Product data sheet Rev. 7 4 March of 18

8 Table 7. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 9. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max [5] pf C PD power dissipation capacitance 74HCT574 t pd propagation delay C L =50pF;f=1 MHz; V I =GNDtoV CC CP to Qn; see Figure 6 [1] V CC = 4.5 V ns V CC =5V; C L =15pF ns t en enable time OE to Qn; see Figure 8 [2] V CC = 4.5 V ns t dis disable time OE to Qn; see Figure 8 [3] t t transition time V CC = 4.5 V ns Qn; see Figure 6 [4] V CC = 4.5 V ns t W pulse width CP HIGH or LOW; see Figure 7 V CC = 4.5 V ns t su set-up time Dn to CP; see Figure 7 V CC = 4.5 V ns t h hold time Dn to CP; see Figure 7 V CC = 4.5 V ns f max maximum CP; see Figure 6 frequency V CC = 4.5 V MHz V CC =5V; C L =15pF MHz C PD power dissipation capacitance C L =50pF;f=1 MHz; V I =GNDtoV CC 1.5 V [5] pf [1] t pd is the same as t PLH and t PHL. [2] t en is the same as t PZH and t PZL. [3] t dis is the same as t PLZ and t PHZ. [4] t t is the same as t THL and t TLH. [5] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V 2 CC f i N+(C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Product data sheet Rev. 7 4 March of 18

9 11. Waveforms Fig 6. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the maximum frequency (CP) Fig 7. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times Product data sheet Rev. 7 4 March of 18

10 Fig 8. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Enable and disable times Table 8. Measurement points Type Input Output V M V M V X V Y 74HC V CC 0.5V CC 0.1V CC 0.9V CC 74HCT V 1.3 V 0.1V CC 0.9V CC Product data sheet Rev. 7 4 March of 18

11 Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Fig 9. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC574 V CC 6ns 15pF, 50 pf 1k open GND V CC 74HCT574 3 V 6 ns 15 pf, 50 pf 1 k open GND V CC Product data sheet Rev. 7 4 March of 18

12 12. Package outline Fig 10. Package outline SOT163-1 (SO20) Product data sheet Rev. 7 4 March of 18

13 Fig 11. Package outline SOT339-1 (SSOP20) Product data sheet Rev. 7 4 March of 18

14 Fig 12. Package outline SOT360-1 (TSSOP20) Product data sheet Rev. 7 4 March of 18

15 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT574 v Product data sheet - 74HC_HCT574 v.6 Modifications: Type numbers 74HC574N and 74HCT574N (SOT146-1) removed. 74HC_HCT574 v Product data sheet - 74HC_HCT574 v.5 Modifications: Table 7: Power dissipation capacitance condition for 74HCT574 is corrected. 74HC_HCT574 v Product data sheet - 74HC_HCT574 v.4 Modifications: V X and V Y measurement points added to Table 8. 74HC_HCT574 v Product data sheet - 74HC_HCT574 v.3 Modifications: Legal pages updated. 74HC_HCT574 v Product data sheet - 74HC_HCT574_CNV v.2 74HC_HCT574_CNV v Product specification - - Product data sheet Rev. 7 4 March of 18