74HC244; 74HCT244. Octal buffer/line driver; 3-state
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1 Rev December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. HIGH on noe causes the outputs to assume a high-impedance OFF-state. The 74HC244; 74HCT244 is identical to the 74HC240; 74HCT240 but has non-inverting outputs. Octal bus interface Non-inverting 3-state outputs Complies with JEDEC standard no. 7 ESD protection: HBM EI/JESD C exceeds 2000 V MM EI/JESD exceeds 200 V Multiple package options Specified from 40 C to+85 C and from 40 C to +125 C Table 1: Quick reference data GND = 0 V; T amb =25 C; t r =t f = 6 ns Symbol Parameter Conditions Min Typ Max Unit 74HC244 t PHL, t PLH propagation delay nn to nyn V CC =5V; C L =15pF ns C i input capacitance pf C PD power dissipation capacitance per buffer; V I = GND to V CC [1] pf 74HCT244 t PHL, t PLH propagation delay nn to nyn V CC =5V; C L =15pF ns C i input capacitance pf C PD power dissipation capacitance per buffer; V I = GND to (V CC 1.5 V) [1] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: [1] pf
2 f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC244 74HC244N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT HC244D 40 C to +125 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74HC244DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74HC244PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74HC244BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body mm SOT HCT244 74HCT244N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT HCT244D 40 C to +125 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74HCT244DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74HCT244PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74HCT244BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body mm SOT764-1 Product data sheet Rev December of 22
3 5. Functional diagram Y Y Y Y OE Y Y Y Y OE mna875 Fig 1. Functional diagram 1 EN Y Y Y Y OE Y2 12 1Y OE 7 2Y2 9 2Y3 mna EN mna873 Fig 2. Logic symbol Fig 3. IEC logic symbol Product data sheet Rev December of 22
4 6. Pinning information 6.1 Pinning 74HC244 74HCT244 terminal 1 index area 1OE VCC 74HC244 74HCT OE 1OE 10 2Y V CC 2OE 1Y0 20 2Y0 11 2Y Y0 20 1Y1 21 2Y1 12 2Y Y1 21 1Y2 22 2Y2 13 2Y GND (1) Y2 22 1Y3 2Y3 GND Y3 23 GND aae aae011 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input Fig 4. Pin configuration DIP20, SO20, SSOP20 and TSSOP20 Fig 5. Pin configuration DHVQFN Pin description Table 3: Pin description Symbol Pin Description 1OE 1 1 output enable input (active LOW) data input 0 2Y0 3 2 bus output data input 1 2Y1 5 2 bus output data input 2 2Y2 7 2 bus output data input 3 2Y3 9 2 bus output 3 GND 10 ground (0 V) data input 3 1Y bus output data input 2 1Y bus output 2 Product data sheet Rev December of 22
5 7. Functional description Table 3: Pin description continued Symbol Pin Description data input 1 1Y bus output data input 0 1Y bus output 0 2OE 19 2 output enable input (active LOW) V CC 20 supply voltage 8. Limiting values 7.1 Function table Table 4: Function table [1] Control Input Output noe nn nyn L L L H H H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. Table 5: Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V - ±20 m I OK output clamping current V O < 0.5 V or - ±20 m V O >V CC V I O output current V O = 0.5 V to (V CC V) - ±35 m I CC quiescent supply current - 70 m I GND ground current - 70 m T stg storage temperature C P tot total power dissipation DIP20 package [1] mw SO20 package [2] mw SSOP20 package [3] mw TSSOP20 package [3] mw DHVQFN20 package [4] mw Product data sheet Rev December of 22
6 [1] For DIP20 package: P tot derates linearly with 12 mw/k above 70 C. [2] For SO20 package: P tot derates linearly with 8 mw/k above 70 C. [3] For SSOP20 and TSSOP20 packages: P tot derates linearly with 5.5 mw/k above 60 C [4] For DHVQFN20 packages: P tot derates linearly with 4.5 mw/k above 60 C. 9. Recommended operating conditions 10. Static characteristics Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC244 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r, t f input rise and fall time V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns 74HCT244 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r, t f input rise and fall time V CC = 4.5 V ns Table 7: Static characteristics 74HC244 t recommended operating conditions; voltages are referenced to GND (ground = 0V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6 V V Product data sheet Rev December of 22
7 Table 7: Static characteristics 74HC244 continued t recommended operating conditions; voltages are referenced to GND (ground = 0V). Symbol Parameter Conditions Min Typ Max Unit V OL LOW-state output voltage V I = V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6 V V I LI input leakage current V I =V CC or GND; V CC = 6 V - - ±0.1 µ I OZ OFF-state output current V I = V IH or V IL ; V O =V CC or GND - - ±0.5 µ I CC quiescent supply current V I =V CC or GND; I O = 0 ; µ V CC = 6.0 V C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6 V V V OL LOW-state output voltage V I = V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6 V V I LI input leakage current V I =V CC or GND; V CC = 6 V - - ±1.0 µ I OZ OFF-state output current V I = V IH or V IL ; V O =V CC or GND - - ±5.0 µ I CC quiescent supply current V I =V CC or GND; I O = 0 ; V CC = 6.0 V µ Product data sheet Rev December of 22
8 Table 7: Static characteristics 74HC244 continued t recommended operating conditions; voltages are referenced to GND (ground = 0V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6 V V V OL LOW-state output voltage V I = V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6 V V I LI input leakage current V I =V CC or GND; V CC = 6 V - - ±1.0 µ I OZ OFF-state output current V I = V IH or V IL ; V O =V CC or GND - - ±10.0 µ I CC quiescent supply current V I =V CC or GND; I O = 0 ; V CC = 6.0 V µ Table 8: Static characteristics 74HCT244 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 6.0 m V V OL LOW-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O =20µ V I O = 6.0 m V I LI input leakage current V I =V CC or GND; V CC = 5.5 V - - ±0.1 µ I OZ OFF-state output current per input pin; V I = V IH or V IL ; V O =V CC or GND; other pins at GND or V CC ; I O = 0 ; V CC = 5.5 V - - ±0.5 µ I CC quiescent supply current V I =V CC or GND; I O =0; V CC = 5.5 V µ Product data sheet Rev December of 22
9 Table 8: Static characteristics 74HCT244 continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit I CC additional quiescent supply current per input pin; V I =V CC 2.1 V; other inputs at V CC or GND; I O =0; V CC = 4.5 V to 5.5 V µ C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 6.0 m V V OL LOW-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O =20µ V I O = 6.0 m V I LI input leakage current V I =V CC or GND; V CC = 5.5 V - - ±1.0 µ I OZ OFF-state output current per input pin; V I = V IH or V IL ; V O =V CC or GND; other pins at GND or V CC ; I O = 0 ; V CC = 5.5 V ±5.0 µ I CC quiescent supply current V I =V CC or GND; I O =0; V CC = 5.5 V I CC additional quiescent supply current per input pin; V I =V CC 2.1 V; other inputs at V CC or GND; I O =0; V CC = 4.5 V to 5.5 V µ µ T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 6.0 m V V OL LOW-state output voltage V I =V IH or V IL ; V CC = 4.5 V I O =20µ V I O = 6.0 m V I LI input leakage current V I =V CC or GND; V CC = 5.5 V - - ±1.0 µ I OZ OFF-state output current per input pin; V I = V IH or V IL ; V O =V CC or GND; other pins at GND or V CC ; I O = 0 ; V CC = 5.5 V - - ±10.0 µ I CC quiescent supply current V I =V CC or GND; I O =0; V CC = 5.5 V I CC additional quiescent supply current per input pin; V I =V CC 2.1 V; other inputs at V CC or GND; I O =0; V CC = 4.5 V to 5.5 V µ µ Product data sheet Rev December of 22
10 11. Dynamic characteristics Table 9: Dynamic characteristics 74HC244 GND = 0 V; t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 8. delay nn to nyn see Figure 6 Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C t PHL, propagation t PLH V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L =15pF ns V CC = 6.0 V ns t PZH, t PZL t PHZ, t PLZ 3-state output enable time 3-state output disable time see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns C PD power dissipation capacitance V I = GND to V CC [1] pf T amb = 40 C to +85 C t PHL, propagation delay t PLH V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL t PHZ, t PLZ 3-state output enable time 3-state output disable time see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev December of 22
11 Table 9: Dynamic characteristics 74HC244 continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 8. Symbol Parameter Conditions Min Typ Max Unit nn to nyn see Figure 6 T amb = 40 C to +125 C t PHL, propagation delay t PLH V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL t PHZ, t PLZ 3-state output enable time 3-state output disable time [1] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Table 10: Dynamic characteristics type 74HCT244 GND = 0 V; t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 8. delay nn to nyn see Figure 6 Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C t PHL, propagation t PLH V CC = 4.5 V ns V CC = 5 V; C L =15pF ns t PZH, t PZL t PHZ, t PLZ 3-state output enable time 3-state output disable time V CC = 4.5 V; see Figure ns V CC = 4.5 V; see Figure ns t THL, output transition time V CC = 4.5 V; see Figure ns t TLH C PD power dissipation capacitance V I = GND to (V CC 1.5 V) [1] pf Product data sheet Rev December of 22
12 Table 10: Dynamic characteristics type 74HCT244 continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf unless otherwise specified; for test circuit see Figure 8. Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C t PHL, propagation delay nn to nyn V CC = 4.5 V; see Figure ns t PLH t PZH, t PZL t PHZ, t PLZ 3-state output enable time 3-state output disable time [1] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. 12. Waveforms V CC = 4.5 V; see Figure ns V CC = 4.5 V; see Figure ns t THL, t TLH output transition time V CC = 4.5 V; see Figure ns T amb = 40 C to +125 C t PHL, propagation delay t PLH t PZH, t PZL t PHZ, t PLZ 3-state output enable time 3-state output disable time V CC = 4.5 V; see Figure ns V CC = 4.5 V; see Figure ns t THL, output transition time V CC = 4.5 V; see Figure ns t TLH V I nn input GND t PHL t PLH V OH nyn output V OL 90 % 10 % t THL t TLH 001aae013 Fig 6. Measurement points are given in Table 11. V OL and V OH are typical voltage output drop that occur with the output load. Propagation delay input (1n, 2n) to output (1Yn, 2Yn) and transition time output (nyn) Product data sheet Rev December of 22
13 V I noe input GND t PLZ t PZL nyn output LOW-to-OFF OFF-to-LOW V CC V OL V X t PHZ t PZH V OH nyn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled V Y outputs disabled outputs enabled 001aae014 Measurement points are given in Table 11. V OL and V OH are typical voltage output drop that occur with the output load. Fig 7. 3-state enable and disable times Table 11: Measurement points Type Input Output 74HC V CC 0.5V CC 74HCT V 1.3 V Product data sheet Rev December of 22
14 V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC PULSE GENERTOR VI DUT VO RL S1 open RT CL 001aad983 Fig 8. Test data is given in Table 12. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator C L = Load capacitance including jig and probe capacitance R L = Load resistor S1 = Test selection switch Load circuitry for switching times Table 12: Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC244 V CC 6 ns 15 pf, 50 pf 1 kω open GND V CC 74HCT244 3 V 6 ns 15 pf, 50 pf 1 kω open GND V CC Product data sheet Rev December of 22
15 13. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 D M E seating plane 2 L 1 Z 20 e b b 1 11 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT146-1 MS-001 SC Fig 9. Package outline SOT146-1 (DIP20) Product data sheet Rev December of 22
16 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L L p θ 1 e b p 10 w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E04 MS Fig 10. Package outline SOT163-1 (SO20) Product data sheet Rev December of 22
17 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ L L p 1 10 detail X e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z (1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT339-1 MO-150 EUROPEN PROJECTION ISSUE DTE Fig 11. Package outline SOT339-1 (SSOP20) Product data sheet Rev December of 22
18 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ 1 10 w M e b p L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT360-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 12. Package outline SOT360-1 (TSSOP20) Product data sheet Rev December of 22
19 DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 9 v M w M C C B y 1 C C y L 1 10 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 13. Package outline SOT764-1 (DHVQFN20) Product data sheet Rev December of 22
20 14. bbreviations Table 13: cronym CMOS DUT ESD HBM LSTTL MM bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model 15. Revision history Table 14: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes Product data sheet HC_HCT244_CNV _2 Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 4 Ordering information, Section 6 Pinning information and Section 13 Package outline : dded DHVQFN package information Section 10 Static characteristics : dded from the family specification 74HC_HCT244_CNV_ Product specification Product data sheet Rev December of 22
21 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Disclaimers customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 19. Trademarks Notice ll referenced brands, product names, service names and trademarks are the property of their respective owners. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 20. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev December of 22
22 21. Contents 1 General description Features Quick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Data sheet status Definitions Disclaimers Trademarks Contact information Koninklijke Philips Electronics N.V ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 22 December 2005 Document number: Published in The Netherlands
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Rev. 03 20 January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with
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Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
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INTEGRTED CIRCUITS DT SHEET Supersedes data of 993 Sep 0 2003 Jul 23 FETURES Complies with JEDEC standard no. 8- ESD protection: HBM EI/JESD22-4- exceeds 2000 V MM EI/JESD22-5- exceeds 200 V. Specified
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Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
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Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
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Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
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Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
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Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance
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Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state
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Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
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Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
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Rev. 03 16 July 2007 Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238
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Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1990 Dec 01 2003 Jul 25 FETURES
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Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
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Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
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Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
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Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.
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Rev. 06 6 March 2006 Product data sheet. General description 2. Features 3. Quick reference data The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device combines low
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Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.
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Rev. 03 4 pril 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They
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Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
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Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
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Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
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Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has four identical 2-input multiplexers with
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Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
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Rev. 03 8 January 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The is a 5-stage Johnson decade counter with
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1997 ug 26 2003 Oct 30 FETURES
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Rev. 04 16 June 2006 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
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Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
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