14-stage binary ripple counter

Transcription

1 Rev November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020. he is a with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 fully buffered parallel outputs (0, and 3 to 13). he counter advances on the HIGH-to-LOW transition of CP. HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Optimized for low-voltage applications: 1.0 V to 5.5 V ccepts L input levels between V CC = 2.7 V and V CC = 3.6 V ypical LOW-level output voltage (peak) or output ground bounce: V OL(p) < 0.8 V at V CC = 3.3 V and amb =25 C ypical HIGH-level output voltage (valley) or output V OH undershoot: V OH(v) >2V at V CC = 3.3 V and amb =25 C ESD protection: HBM EI/JESD C exceeds 2000 V MM EI/JESD exceeds 200 V. Multiple package options Specified from 40 C to +80 C and from 40 C to +125 C. Frequency dividing circuits ime delay circuits Control counters

2 4. uick reference data 5. Ordering information able 1: uick reference data GND = 0 V; amb =25 C; t r =t f = 2.5 ns. Symbol Parameter Conditions Min yp Max Unit t PHL, propagation delay C L = 15 pf; V CC = 3.3 V t PLH CP to ns n to (n+1) ns t PHL propagation delay C L = 15 pf; V CC = 3.3 V MR to n ns f max maximum input clock C L = 15 pf; V CC = 3.3 V MHz frequency C i input capacitance pf C PD power dissipation capacitance per gate; V I = GND to V CC [1] pf [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. able 2: Ordering information ype number Package emperature range Name Description Version N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SO38-4 D 40 C to +125 C SO16 plastic small outline package; 16 leads; SO109-1 body width 3.9 mm DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SO338-1 body width 5.3 mm PW 40 C to +125 C SSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SO403-1 _1 Product data sheet Rev November of 20

3 6. Functional diagram CP MR C D 14-SGE COUNER aad722 Fig 1. Functional diagram 10 CP 11 MR aad C CR C aad724 Fig 2. Logic symbol Fig 3. IEC logic symbol CP MR aad725 Fig 4. Logic diagram _1 Product data sheet Rev November of 20

4 7. Pinning information 7.1 Pinning V CC MR CP GND aad721 Fig 5. Pin configuration DIP16, SO16, SSOP16 and SSOP Pin description able 3: Pin description Symbol Pin Description 11 1 parallel output parallel output parallel output parallel output parallel output parallel output parallel output 3 GND 8 ground (0 V) 0 9 parallel output 0 CP 10 clock input (HIGH-to-LOW, edge-triggered) MR 11 master reset input (active HIGH) 8 12 parallel output parallel output parallel output parallel output 10 V CC 16 supply voltage _1 Product data sheet Rev November of 20

5 8. Functional description 8.1 Function table able 4: Function table [1] Input Output CP MR 0, 3 to 13 L no change L count X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition iming diagram CP input MR input aad726 Fig 6. iming diagram _1 Product data sheet Rev November of 20

6 9. Limiting values able 5: Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I > V CC V - ±20 m I OK output clamping current V O < 0.5 V or - ±50 m V O >V CC V I O output current V O = 0.5 V to V CC V - ±25 m I CC quiescent supply current - 50 m I GND ground current - 50 m stg storage temperature C P tot total power dissipation amb = 40 C to +125 C DIP16 package [1] mw SO16 package [2] mw SSOP16 and SSOP16 packages [3] mw [1] bove amb = 70 C: P tot derates linearly with 12 mw/k. [2] bove amb = 70 C: P tot derates linearly with 8 mw/k. [3] bove amb = 60 C: P tot derates linearly with 5.5 mw/k. 10. Recommended operating conditions able 6: Recommended operating conditions Symbol Parameter Conditions Min yp Max Unit V CC supply voltage [1] V V I input voltage 0 - V CC V V O output voltage 0 - V CC V amb ambient temperature C t/ V input transition rise and V CC = 1.0 V to 2.0 V ns/v fall rate V CC = 2.0 V to 2.7 V ns/v V CC = 2.7 V to 3.6 V ns/v V CC = 3.6 V to 5.5 V ns/v [1] he static characteristics are guaranteed from V CC = 1.2 V to V CC = 5.5 V, but LV devices are guaranteed to function down to V CC = 1.0 V (with input levels GND or V CC ). _1 Product data sheet Rev November of 20

7 11. Static characteristics able 7: Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min yp Max Unit amb = 40 C to +85 C [1] V IH HIGH-state input voltage V CC = 1.2 V V V CC = 2.0 V V V CC = 2.7 V to 3.6 V V V CC = 4.5 V to 5.5 V 0.7 V CC - - V V IL LOW-state input voltage V CC = 1.2 V V V CC = 2.0 V V V CC = 2.7 V to 3.6 V V V CC = 4.5 V to 5.5 V V CC V V OH HIGH-state output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.2 V V I O = 100 µ; V CC = 2.0 V V I O = 100 µ; V CC = 2.7 V V I O = 100 µ; V CC = 3.0 V V I O = 100 µ; V CC = 4.5 V V I O = 6 m; V CC = 3.0 V V I O = 12 m; V CC = 4.5 V V V OL LOW-state output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.2 V V I O = 100 µ; V CC = 2.0 V V I O = 100 µ; V CC = 2.7 V V I O = 100 µ; V CC = 3.0 V V I O = 100 µ; V CC = 4.5 V V I O = 6 m; V CC = 3.0 V V I O = 12 m; V CC = 4.5 V V I LI input leakage current V I = V CC or GND; V CC = 5.5 V µ I CC quiescent supply current V I = V CC or GND; I O = 0 ; V CC = 5.5 V µ I CC additional quiescent supply current per input; V I = V CC 0.6 V; V CC = 2.7 V to 3.6 V µ C i input capacitance pf amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 1.2 V V V CC = 2.0 V V V CC = 2.7 V to 3.6 V V V CC = 4.5 V to 5.5 V 0.7 V CC - - V _1 Product data sheet Rev November of 20

8 able 7: Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min yp Max Unit V IL LOW-state input voltage V CC = 1.2 V V V CC = 2.0 V V V CC = 2.7 V to 3.6 V V V CC = 4.5 V to 5.5 V V CC V V OH HIGH-state output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.2 V V I O = 100 µ; V CC = 2.0 V V I O = 100 µ; V CC = 2.7 V V I O = 100 µ; V CC = 3.0 V V I O = 100 µ; V CC = 4.5 V V I O = 6 m; V CC = 3.0 V V I O = 12 m; V CC = 4.5 V V V OL LOW-state output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.2 V V I O = 100 µ; V CC = 2.0 V V I O = 100 µ; V CC = 2.7 V V I O = 100 µ; V CC = 3.0 V V I O = 100 µ; V CC = 4.5 V V I O = 6 m; V CC = 3.0 V V I O = 12 m; V CC = 4.5 V V I LI input leakage current V I = V CC or GND; V CC = 5.5 V µ I CC quiescent supply current V I = V CC or GND; I O = 0 ; V CC = 5.5 V µ I CC additional quiescent supply current [1] ll typical values are measured at amb = 25 C. per input; V I = V CC 0.6 V; V CC = 2.7 V to 3.6 V µ _1 Product data sheet Rev November of 20

9 12. Dynamic characteristics able 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C L = 50 pf; for test circuit see Figure 9. Symbol Parameter Conditions Min yp Max Unit amb = 40 C to +85 C [1] t PHL, t PLH propagation delay CP to 0 see Figure 7 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns V CC = 3.3 V; C L = 15 pf ns n to (n+1) see Figure 7 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns V CC = 3.3 V; C L = 15 pf ns t PHL propagation delay MR to n see Figure 8 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns V CC = 3.3 V; C L = 15 pf ns t W pulse width CP (HIGH and LOW) see Figure 7 V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns MR (HIGH) see Figure 8 V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns _1 Product data sheet Rev November of 20

10 able 8: Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); C L = 50 pf; for test circuit see Figure 9. Symbol Parameter Conditions Min yp Max Unit t rec recovery time MR to CP see Figure 8 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns f max maximum input clock frequency see Figure 7 V CC = 2.0 V MHz V CC = 2.7 V MHz V CC = 3.0 V to 3.6 V MHz V CC = 4.5 V to 5.5 V MHz V CC = 3.3 V; C L = 15 pf MHz C PD power dissipation capacitance per gate; V I = GND to V CC [2] pf amb = 40 C to +125 C t PHL, t PLH propagation delay CP to 0 see Figure 7 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns n to (n+1) see Figure 7 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns t PHL propagation delay MR to n see Figure 8 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns _1 Product data sheet Rev November of 20

11 able 8: Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); C L = 50 pf; for test circuit see Figure 9. Symbol Parameter Conditions Min yp Max Unit t W t rec pulse width CP (HIGH and LOW) see Figure 7 V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns MR (HIGH) see Figure 8 V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns recovery time MR to CP see Figure 8 V CC = 1.2 V ns V CC = 2.0 V ns V CC = 2.7 V ns V CC = 3.0 V to 3.6 V ns V CC = 4.5 V to 5.5 V ns f max maximum input clock frequency see Figure 7 V CC = 2.0 V MHz V CC = 2.7 V MHz V CC = 3.0 V to 3.6 V MHz V CC = 4.5 V to 5.5 V MHz [1] ypical values are measured at nominal V CC and amb = 25 C. [2] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ(C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; Σ(C L V 2 CC f o ) = sum of the outputs. _1 Product data sheet Rev November of 20

12 13. Waveforms 1/f max V I input CP, n V M GND t W t PHL t PLH V OH output 0, (n+1) V M V OL 001aad727 Fig 7. Measurement points: V M = 0.5 V CC. V OL and V OH are typical output voltage drop that occur with the output load. Propagation delay clock (CP) to output (n), clock pulse width and maximum clock frequency V I MR input V M GND t W t rec V I CP input V M GND t PHL V OH n output V M V OL 001aad728 Fig 8. Measurement points: V M = 0.5 V CC. V OL and V OH are typical output voltage drop that occur with the output load. Propagation delay master reset (MR) to output (n), pulse width master reset (MR) and removal time master reset (MR) to clock (CP) _1 Product data sheet Rev November of 20

13 V CC PULSE GENEROR V I R D.U.. V O C L 50 pf R L 1 kω 001aaa663 Fig 9. est data is given in able 9. Definitions for test circuit: R L = Load resistor. C L = Load capacitance including jig and probe capacitance. R = ermination resistance should be equal to output impedance Z o of the pulse generator. Load circuitry for switching times able 9: est data Supply voltage Input Load est V CC V I t r, t f C L R L 1.2 V V CC 2.5 ns 50 pf 1 kω t PHL, t PLH 2.0 V V CC 2.5 ns 50 pf 1 kω t PHL, t PLH 2.7 V 2.7 V 2.5 ns 50 pf 1 kω t PHL, t PLH 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pf, 15 pf 1 kω t PHL, t PLH 4.5 V to 5.5 V V CC 2.5 ns 50 pf 1 kω t PHL, t PLH _1 Product data sheet Rev November of 20

14 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SO38-4 D M E seating plane 2 L 1 Z 16 e b b 1 9 b 2 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNI 1 2 (1) (1) (1) max. b 1 b 2 c D E e L M Z min. max. b e 1 M E H w max mm inches Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included OULINE VERSION REFERENCES IEC JEDEC JEI EUROPEN PROJECION ISSUE DE SO Fig 10. Package outline SO38-1 (DIP16) _1 Product data sheet Rev November of 20

15 SO16: plastic small outline package; 16 leads; body width 3.9 mm SO109-1 D E X c y H E v M Z ( ) 3 pin 1 index θ L p 1 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNI mm inches max b p c D (1) E (1) e H (1) E L L p v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OULINE VERSION REFERENCES IEC JEDEC JEI EUROPEN PROJECION ISSUE DE SO E07 MS Fig 11. Package outline SO109-1 (SO16) _1 Product data sheet Rev November of 20

16 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SO338-1 D E X c y H E v M Z ( ) 3 pin 1 index 1 8 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNI b p c D (1) E (1) e H E L L p v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OULINE VERSION REFERENCES IEC JEDEC JEI EUROPEN PROJECION ISSUE DE SO338-1 MO Fig 12. Package outline SO338-1 (SSOP16) _1 Product data sheet Rev November of 20

17 SSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SO403-1 D E X c y H E v M Z 16 9 pin 1 index 2 1 ( ) 3 θ 1 8 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNI b p c D (1) E (2) e H (1) E L L p v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OULINE VERSION REFERENCES IEC JEDEC JEI SO403-1 MO-153 EUROPEN PROJECION ISSUE DE Fig 13. Package outline SO403-1 (SSOP16) _1 Product data sheet Rev November of 20

18 15. bbreviations able 10: cronym CMOS L HBM ESD MM bbreviations Description Complementary Metal Oxide Semiconductor ransistor ransistor Logic Human Body Model ElectroStatic Discharge Machine Model 16. Revision history able 11: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes _ Product data sheet _1 Product data sheet Rev November of 20

19 17. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development his data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data ualification his data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production his data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] he product status of the device(s) described in this data sheet may have changed since this data sheet was published. he latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions Short-form specification he data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. hese are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19. Disclaimers customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. rademarks Notice ll referenced brands, product names, service names and trademarks are the property of their respective owners. Life support hese products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ _1 Product data sheet Rev November of 20

20 22. Contents 1 General description Features pplications uick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table iming diagram Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Data sheet status Definitions Disclaimers rademarks Contact information Koninklijke Philips Electronics N.V ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. he information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 29 November 2005 Document number: _1 Published in he Netherlands