DLA LAND AND MARITIME COLUMBUS, OHIO

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1 REVISIONS LTR DESCRIPTION DTE PPROVED Make correction to the vendor part number by deleting TPS51200-EP and replacing with TPS51200MDRCTEP as specified under paragraph ro C. SFFLE Prepared in accordance with SME Y14.24 REV PGE REV PGE Vendor item drawing REV STTUS OF PGES REV PGE PMIC N/ PREPRED BY RICK OFFICER DL LND ND MRITIME Original date of drawing YY-MM-DD CHECKED BY RJESH PITHDI PPROVED BY CHRLES F. SFFLE TITLE MICROCIRCUIT, LINER, SINK ND SOURCE DDR TERMINTION REGULTOR, MONOLITHIC SILICON CODE IDENT. NO. REV PGE 1 OF 13 MSC N/ 5962-V018-17

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance sink and source double data rate (DDR) termination regulator microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 TPS51200-EP Sink and source DDR termination regulator Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 10 See figure 1 Plastic quad leadless small outline Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other DL LND ND MRITIME REV PGE 2

3 1.3 bsolute maximum ratings. 1/ Input voltage (VIN): 2/ REFIN, VIN, VLDOIN, VOSNS V minimum, 3.6 V maximum EN V minimum, 6.5 V maximum PGND to GND V minimum, 0.3 V maximum Output voltage VOUT): 2/ REFOUT, VO V minimum, 3.6 V maximum PGOOD V minimum, 6.5 V maximum Operating junction temperature range (TJ) C to +150 C Storage temperature range (TSTG) C to +150 C Electrostatic discharge (ESD): Human body model (HBM) V 3/ Charged device model (CDM) V 4/ 1.4 Recommended operating conditions. 5/ Supply voltages (VIN) V minimum, V maximum Voltage: EN, VLDOIN, VOSNS V minimum, 3.5 V maximum REFIN V minimum, 1.8 V maximum PGOOD, VO V minimum, 3.5 V maximum REFOUT V minimum, 1.8 V maximum PGND V minimum, 0.1 V maximum Operating junction temperature range (TJ) C to +125 C 1/ Stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Unless otherwise specified, all voltages are with respect to the network ground terminal. 3/ JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. 4/ JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DL LND ND MRITIME REV PGE 3

4 1.5 Thermal characteristics. Thermal metric 6/ Symbol Case X Unit Thermal resistance, junction-to-ambient J 55.6 C/W Thermal resistance, junction-to-case (top) JC(TOP) 84.6 C/W Thermal resistance, junction-to-board JB 30.0 C/W Characterization parameter, junction-to-top JT 5.5 C/W Characterization parameter, junction-to-board JB 30.1 C/W Thermal resistance, junction-to-case (bottom) JC(BOTTOM) 10.9 C/W 2. PPLICBLE DOCUMENTS JEDEC Solid State Technology ssociation JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC JEP Recommended ESD Target Levels for HBM/MM Qualification JEDEC JEP Recommended ESD-CDM Target Levels (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure 2. 6/ Contact manufacturer for more information about traditional and new thermal metrics. DL LND ND MRITIME REV PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TJ Device type Min Limits Max Unit Supply current Supply current IIN VEN = 3.3 V, no load 25 C 01 1 m 0.7 typical Shutdown current IIN(SDN) VEN = 0 V, VREFIN = 0 V, 25 C no load 65 typical VEN = 0 V, VREFIN 0.4 V, 400 no load 200 typical Supply current of VLDOIN Shutdown current of VLDOIN ILDOIN VEN = 3.3 V, no load 25 C typical ILDOIN(SDN) VEN = 0 V, no load 25 C typical Input current Input current, REFIN IREFIN VEN = 3.3 V -55 C to +125 C 01 1 VO output Output dc voltage, VO VVOSNS VREFOUT = 1.25 V (DDR1), -55 C to +125 C V IO = 0 25 C 1.25 typical mv VREFOUT = 0.9 V (DDR2), -55 C to +125 C V IO = 0 25 C 0.9 typical mv VREFOUT = 0.75 V (DDR3), -55 C to +125 C V VLDOIN = 1.5 V, IO = 0 25 C 0.75 typical mv See footnotes at end of table. DL LND ND MRITIME REV PGE 5

6 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, TJ Device type Min Limits Max Unit VO output continued. Output voltage tolerance to REFOUT VVOTOL -2 IVO 2-55 C to +125 C mv VO source current limit IVOSRCL With reference to REFOUT, VOSNS = 90% x VREFOUT -55 C to +125 C VO sink current limit IVOSNCL With reference to REFOUT, VOSNS = 110% x VREFOUT -55 C to +125 C Discharge current, VO IDSCHRG VREFIN = V, VVO = 0.3 V, 25 C VEN = 0 V 18 typical Powergood comparator VO PGOOD threshold VTH(PG) PGOOD window lower threshold -55 C to +125 C % with respect to REFOUT 25 C -20 typical PGOOD window upper threshold -55 C to +125 C with respect to REFOUT 25 C 20 typical PGOOD hysteresis 25 C 5 typical PGOOD start up delay tpgstupdly Start up rising edge, VOSNS within 15% of REFOUT 25 C 01 2 typical ms Output low voltage VPGOODLOW ISINK = 4 m -55 C to +125 C V PGOOD bad delay tpbddly VOSNS is outside of the 20% PGOOD window Leakage current 3/ IPGOODLK VOSNS = VREFIN (PGOOD high impedance), VPGOOD = VVIN V 25 C typical s -55 C to +125 C 01 1 See footnotes at end of table. DL LND ND MRITIME REV PGE 6

7 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, TJ Device type Limits Unit Min Max REFIN and REFOUT REFIN voltage range VREFIN -55 C to +125 C V REFIN undervoltage lockout REFIN undervoltage lockout hysteresis VREFINUVLO REFIN rising -55 C to +125 C mv 25 C 390 typical VREFINUVHYS 25 C typical mv REFOUT voltage VREFOUT 25 C 01 REFIN typical V REFOUT voltage tolerance to VREFIN VREFOUTTOL -10 m IREFOUT 10 m, VREFIN = 1.25 V -55 C to +125 C mv -10 m IREFOUT 10 m, VREFIN = 0.9 V -10 m IREFOUT 10 m, VREFIN = 0.75 V -10 m IREFOUT 10 m, VREFIN = 0.6 V REFOUT source current limit REFOUT sink current limit IREFOUTSRCL VREFOUT = 0 V -55 C to +125 C m 25 C 40 typical IREFOUTSNCL VREFOUT = 0 V -55 C to +125 C m 25 C 40 typical See footnotes at end of table. DL LND ND MRITIME REV PGE 7

8 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, TJ Device type Min Limits Max Unit UVLO and EN logic threshold. UVLO threshold VVINUVVIN Wake up 25 C V 2.3 typical Hysteresis 50 typical mv High level input voltage Low level input voltage VENIH Enable -55 C to +125 C V VENIL Enable -55 C to +125 C V Hysteresis voltage VENYST Enable 25 C typical V Logic input leakage current IENLEK EN 25 C Thermal shutdown Thermal shutdown threshold TSON Shutdown temperature 25 C typical C Hysteresis 25 typical 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 x 10 F and figure 3. 3/ Ensured by design. Not production tested. DL LND ND MRITIME REV PGE 8

9 Case X FIGURE 1. Case outline. DL LND ND MRITIME REV PGE 9

10 Case X continued. Symbol Inches Dimensions Millimeters Min Max Min Max REF 0.20 REF b D E e.019 BSC 0.50 BSC s NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. The package thermal pad must be soldered to the board for thermal and mechanical performance, if present 3. See the additional figure in the manufacturer s datasheet for details regarding the exposed thermal pad features and dimensions, if present. FIGURE 1. Case outline - Continued. DL LND ND MRITIME REV PGE 10

11 Device type 01 Case outline X Terminal number Terminal symbol I/O SEE NOTE 1 Description 1 REFIN I Reference input. 2 VLDOIN I Supply voltage for the LDO. 3 VO O Power output for the LDO. 4 PGND SEE NOTE 2 G Power ground output for the LDO. 5 VOSNS I Voltage sense input for the LDO. Connect to positive terminal of the output capacitor or the load. 6 REFOUT O Reference output. Connect to GND through 0.1 F ceramic capacitor. 7 EN I For DDT VTT application, connect EN to SLP_S3. For any other application, use the EN pin as the ON/OFF function. 8 GND G Signal ground. Connect to negative terminal of the output capacitor. 9 PGOOD O PGOOD output. Indicates regulation. 10 VIN I 2.5 V or 3.3 V power supply. ceramic decoupling capacitor with a value between 1 F and 4.7 F is required. NOTES: 1. I = Input, O = Output, and G = Ground. 2. Thermal pad connection. FIGURE 2. Terminal connections. DL LND ND MRITIME REV PGE 11

12 FIGURE V VIN, DDR3 configuration. DL LND ND MRITIME REV PGE 12

13 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number 2/ -01XE TPS51200MDRCTEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For all available packages, see the orderable addendum at the end of the manufacturer s data sheet. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX DL LND ND MRITIME REV PGE 13

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