IX Ampere, Dual Low-Side MOSFET Driver INTEGRATED CIRCUITS DIVISION. Features. Description. Applications. Ordering Information

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mpere, Dual LowSide MOSFET Driver Features Two Independent Drivers, Each Capable of Sourcing and Sinking CMOS and TTL Compatible Inputs Independent Enable for Each Driver V to 20V Supply Voltage

1 mpere, Dual LowSide MOSFET Driver Features Two Independent Drivers, Each Capable of Sourcing and Sinking CMOS and TTL Compatible Inputs Independent Enable for Each Driver V to 20V Supply Voltage Range 0 C to +12 C Extended Operating Temperature Range ±kv ESD Rating (Human Body Model) Thermally enhanced 8pin SOIC and 8pin MSOP packages and standard 8pin SOIC package Under Voltage Lockout Circuitry Fast Propagation Delays (16ns typical) Fast Rise and Fall Times (7ns typical) pplications SwitchMode Power Supplies DCDC Converters Motor Controllers Power Inverters Description The is a dual, high current, low side gate driver. Each of the two outputs is capable of sourcing and sinking of peak current, and has a maximum voltage rating of 20V. The two outputs can be paralleled for higher current applications. Fast propagation delay times (16ns typical) and fast rise and fall times (7ns) make the well suited for high frequency applications. The inputs are TTL and CMOS logic compatible, and there is an independent Enable function for each output. Under voltage lockout circuitry (UVLO) prevents the high side source driver from conducting until there is sufficient supply voltage. The outputs are held low if the logic inputs are floating. The is available in standard 8pin SOIC and thermally enhanced 8pin SOIC and MSOP packages. Ordering Information Part Number N NTR NE NETR UE UETR Description 8Pin SOIC (100/Tube) 8Pin SOIC (000/Reel) 8Pin SOIC w/ Exposed Thermal Pad (100/Tube) 8Pin SOIC w/ Exposed Thermal Pad (000/Reel) 8Pin MSOP w/ Exposed Thermal Pad (100/Tube) 8Pin MSOP w/ Exposed Thermal Pad (000/Reel) Functional Block Diagram EN 1 8 ENB IN 2 7 OUT GND 3 UVLO 6 INB OUTB DSR0 1

2 1. Specifications Pin Configuration Logic Table Pin Definitions bsolute Maximum Ratings Electrical Characteristics Thermal Characteristics Performance Data Manufacturing Information Moisture Sensitivity ESD Sensitivity Soldering Profile Board Wash Mechanical Dimensions R0

3 1 Specifications 1.1 Pin Configuration 1.2 Logic Table IXx ENx OUTx EN 1 8 ENB 1 1 >UVLO ON 1 IN 2 7 OUT 0 1 >UVLO ON 0 x 0 >UVLO ON 0 GND 3 6 x x <UVLO ON 0 INB B OUTB 1.3 Pin Definitions Pin # Name Description 1 EN Enable input for Channel. logic high (or floating) enables Channel (the state of OUT is determined by IN). logic low disables OUT (OUT held low regardless of IN). 2 IN Channel logic input. Internally pulled to GND. 3 GND Ground. Common ground reference for the device. INB Channel B logic input. Internally pulled to GND. OUTB Channel B output, capable of sourcing and sinking 6 Supply Voltage. 7 OUT Channel output, capable of sourcing and sinking 8 ENB Enable input for Channel B. logic high (or floating) enables Channel B (the state of OUTB is determined by INB). logic low disables OUTB (OUTB held low regardless of INB). The thermal pad on the bottom of the thermally enhanced devices, NE and UE, may be connected to GND or left floating; it must not be connected to any other net. The thermal pad is not intended to carry current. 1. bsolute Maximum Ratings Parameter Symbol Minimum Maximum Units Supply Voltage V Input Voltage V IN V Output Current I OUT ± ESD Rating (Human Body Model) V ESD V Junction Temperature T J +10 C Storage Temperature T STG C bsolute maximum electrical ratings are at T =2 C bsolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. R0 3

4 1. Electrical Characteristics = 12V, T J = 0 C to +12 C, unless otherwise noted. Parameter Conditions Symbol Minimum Typical Maximum Units Supply Supply Current OUT and OUTB Open I CC m Under Voltage Lockout (UVLO) UVLO Rising Threshold Rising UVLO ON UVLO Falling Threshold Falling UVLO OFF UVLO Threshold Hysteresis UVLO HYS Logic Inputs (IN, INB, EN, ENB) Input Low Voltage V IL 0.8 Input High Voltage V IH 2. Output Drivers (OUT, OUTB) Output PullUp Resistance I OUT = 100m, T J = 2 C 1 1. R I OH OUT = 100m Output PullDown Resistance I OUT = 100m, T J = 2 C R I OL OUT = 100m Rise Time C LOD = 1.8nF t R 7 1 Fall Time C LOD = 1.8nF t F 7 1 Propagation Delay, Low to High C LOD = 1.8nF t DLH Propagation Delay, High to Low C LOD = 1.8nF t DHL Propagation Delay Matching t M V V ns V IH INx V IL 90% t DLH t DHL OUTx 10% t R t F 1.6 Thermal Characteristics Parameter Symbol Rating Units N Thermal Impedance, Junction to mbient J 120 NE Thermal Impedance, Junctiontombient J 8 NE Thermal Impedance, JunctiontoCase JC 10 C/W UE Thermal Impedance, Junctiontombient J 0 UE Thermal Impedance, JunctiontoCase JC 10 R0

5 2 Performance Data Unless otherwise noted, data presented in these graphs is typical of device operation at T =2ºC. Supply Current (m) Supply Current vs. Temperature Outputs in DC ON/OFF Condition (EN=ENB= =12V) Input= Input=0V Supply Current (m) Operating Supply Current vs. Temperature (Outputs Switching) ( =12V, f=00khz, C L =00pF) Supply Current (m) Operating Supply Current vs. Frequency (C L =1.8nF, Both Channels Switching) =18V =12V =10V =V Frequency (khz) 2.0 Input Threshold vs. Temperature ( = 12V) 2.0 Enable Threshold vs. Temperature ( =12V).0 UVLO Threshold vs. Temperature Input Threshold (V) V IH V IL Enable Threshold (V) V IH V IL UVLO Threshold (V) UVLO ON UVLO OFF Propagation Delay (ns) Input To Output Propagation Delay vs. Temperature ( =12V, C L =1.8 nf) t DHL t DLH Propagation Delay (ns) Enable to Output Propagation Delay vs. Temperature ( =12V, C L =1.8nF) EN to Output Low EN to Output High Propagation Delay (ns) Propagation Delay vs. Supply Voltage (C L =1.8nF) Input to Output High EN to Output High Input to Output Low EN to Output Low Supply Voltage (V) R0

6 Rise Time (ns) Rise Time vs. Temperature ( =12V, C L =1.8nF) Rise Time (ns) Rise Time vs. Supply Voltage (C L =1.8nF ) Supply Voltage (V) Output Resistance (Ω) Output PullUp Resistance vs. Temperature ( =12V, I OUT = 100m) Fall Time (ns) Fall Time vs. Temperature ( =12V, C L =1.8 nf) Fall Time (ns) Fall Time vs. Supply Voltage (C L =1.8nF ) Supply Voltage (V) Output Resistance (Ω) Output PullDown Resistance vs. Temperature ( = 12V, I OUT = 100m) R0

7 3 Manufacturing Information 3.1 Moisture Sensitivity ll plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC JSTD020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC JSTD033. Device Moisture Sensitivity Level (MSL) Classification N & NE MSL 1 UE MSL ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD Soldering Profile Provided in the table below is the Classification Temperature (T C ) of this product and the maximum dwell time the body temperature of this device may be (T C )ºC or greater. The classification temperature sets the Maximum Body Temperature allowed for this device during leadfree reflow processes. For throughhole devices, and any other processes, the guidelines of JSTD020 must be observed. Device Classification Temperature (T C ) Dwell Time (t p ) Max Reflow Cycles N, NE, & UE 260 C 30 seconds 3 3. Board Wash IXYS Integrated Circuits Division recommends the use of noclean flux formulations. Board washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be used. dditionally, the device must not be exposed to flux or solvents that are Chlorine or Fluorinebased. R0 7

8 3. Mechanical Dimensions 3..1 NE Package Dimensions 0.31 / 0.1 (0.012 / 0.020) 8x TOP VIEW BOTTOM VIEW PCB Land Pattern 0.60 (0.02) 1. (0.061).80 / 6.20 (0.228 / 0.2) 3.80 /.00 (0.10 / 0.17) 1.9 / 2.29 (0.076 / 0.090) 3.8 (0.12) 2.11 (0.083) PIN #1 1.2 MIN (0.09 MIN) 1.70 MX (0.067 MX) 0 / 0.1 (0 / 0.006) x.80 /.00 (0.189 / 0.197) 0.10 (0.00) GUGE PLNE SETING PLNE 1.9 / 2.29 (0.076 / 0.090) 0.2 (0.010) / 0.2 (0.00 / 0.010) 0.0 / 1.27 (0.016 / 0.00) 2.11 (0.083) Dimensions MIN / MX Notes: 1. Controlling dimension: millimeters. 2. ll dimensions are in mm (inches). 3. This package conforms to JEDEC Standard MS012, variation B, Rev. F.. Dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.1mm per end.. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.2mm per side. 6. The thermal pad on the bottom of the device may be connected to GND or left floating; it must not be connected to any other signal. The thermal pad is not intended to carry current. 7. Lead thickness includes plating N Package Dimensions 0.31 / 0.1 (0.012 / 0.020) 8x TOP VIEW PCB Land Pattern 1. (0.061).80 / 6.20 (0.228 / 0.2) 3.80 /.00 (0.10 / 0.17) 3.7 (0.18) 1.7 MX (0.069 MX) PIN #1 1.2 MIN (0.09 MIN) x.80 /.00 (0.189 / 0.197) GUGE PLNE SETING PLNE 0.2 (0.010) / 0.2 (0.00 / 0.010) 0.0 / 1.27 (0.016 / 0.00) 0.60 (0.02) 0.10 / 0.2 (0.00 / 0.010) 0.10 (0.00) Dimensions MIN / MX Notes: 1. Controlling dimension: millimeters. 2. ll dimensions are in mm (inches). 3. This package conforms to JEDEC Standard MS012, variation, Rev. F.. Dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.1mm per end.. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.2mm per side. 6. Lead thickness includes plating. 8 R0

9 3..3 NTR & NETR Tape & Reel Dimensions 330 DI. (13.00 inch DI) B 0 =.20 W=12.0±0.3 Embossed Carrier Embossment K 0 =2.10 K 1 = =6.0 P1=8.00 Notes: sprocket hole pitch cumulative tolerance ± Camber in compliance with EI Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.. ll dimensions in millimeters. 3.. UE Package Dimensions b 0.10 D e E1 2 1 E c Gauge plane Seating plane Detail 0.2 D1 E2 H L L1 1 2 b c D D1 E E1 E2 e L L1 V W X Y Z Recommended PCB Land Pattern X MIN º MILLIMETERS NOM BSC.90 BSC 3.00 BSC 0.6 BSC REF MX REF 8º 0º 8º LND PTTERN V MIN INCHES NOM BSC BSC BSC BSC 0.02 MX Y Notes: Z W 1. JEDEC outline: Thermally enhanced: MO187 T. 2. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.1mm per end. 3. Dimension b does not include dambar protrusion. llowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and an adjacent lead shalll not be less than 0.07mm.. D and E1 dimensions are determined at datum H.. The thermal pad on the bottom of the device may be connected to GND or left floating; it must not be connected to any other signal. The thermal pad is not intended to carry current. R0 9

10 3.. UETR Tape & Reel Dimensions 330 DI. (13.00 inch DI) 2.00±0.0 See Note 3 (0.079±0.002).00 See Note 1 0.3±0.0 (0.17) (0.012±0.002) 8.00 (0.31) 1.7±0.10 (0.069±0.00) 3.30 (0.130).0±0.0 (0.217±0.002) W=12.0±0.3 (0.72±0.012) Embossed Carrier DIMENSIONS: mm (inches) 1.20 (0.07) Embossment (0.07) (0.063).20 (0.20) 3.0 (0.13).20 (0.16) NOTES: sprocket hole pitch cumulative tolerance: ±0.2 (0.008). 2. Camber in compliance with EI Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. For additional information please visit our website at: IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DSR0 Copyright 2018, IXYS Integrated Circuits Division ll rights reserved. Printed in US. 1/18/ R0

IX4340NE. Automotive Grade 5-Ampere, Dual Low-Side MOSFET Driver INTEGRATED CIRCUITS DIVISION. Features. Description. Applications

IX4340NE. Automotive Grade 5-Ampere, Dual Low-Side MOSFET Driver INTEGRATED CIRCUITS DIVISION. Features. Description. Applications Automotive Grade -Ampere, Dual Low-Side MOSFET Driver Features AEC-Q100 qualified Two independent drivers, each capable of sourcing and sinking A V to 20V supply voltage range AEC-Q100 Grade 1-0 C to +12