S6B CH SEGMENT / COMMON DRIVER FOR DOT MATRIX LCD

Transcription

1 6B006 0 H EGENT / OON RIVER FOR OT ATRIX L June Ver. 0.0 ontents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of L river I Team.

2 6B006 0H OON / EGENT RIVER FOR OT ATRIX L INTROUTION The 6B006 is an L driver LI which is fabricated by low power O high voltage process technology. In segment driver mode, it can be interfaced in -bit serial or -bit parallel method by the controller. In common driver mode, dual type mode is applicable. And in segment mode application, the power down function reduces power consumption. FEATURE Power supply voltage: + 5V ± 0 %, + V ± 0% upply voltage for display: 6 to V (V -V EE ) -bit parallel / -bit serial data processing (in segment mode) ingle mode operation / dual mode operation (in common mode) Power down function (in segment mode) Applicable L duty: /6 /56 Interface RIVER O (cascade) 6B006 High voltage O process Bare die or TP available EG (cascade) 6B006

3 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 TP N N N N N N 6B006 E R B V E E V 5 V V V 0 I P 0 F F B V H L V - R - - L - I L A L E L B # #0 * Package Type = 00-TP-5mm * Input Lead Pitch = 0.0mm * Output Lead Pitch = 0.mm

4 6B006 0H OON / EGENT RIVER FOR OT ATRIX L PA IAGRA (6B006 / 6B006 TP) B006 Y (0, 0) X hip size: Pad size: 9 9 Unit: µ m VEE V5 V V V0 IPOFFB V HL V _R L _I L A L

5 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 PA ENTER OORINATE (6B006 / 6B006TP) Pad Pad oordinates Pad Pad oordinates Pad Pad oordinates No. Name X Y No. Name X Y No. Name X Y V V V IP0FFB V HL V _R _ _L _I L L VEE V V

6 6B006 0H OON / EGENT RIVER FOR OT ATRIX L BLOK IAGRA 90 V0 V V 0-bit -level river V5 VEE IP0FFB Output Level elector 0-bit river _I _L LK 0-bit ata Latch/ ommon ata bi-directional shift register R K 0 x -bit egment ata bi-directional hift Register L L lock ontrol ata Latch ontrol Power own Function V A V 6

7 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 BLOK ERIPTION Name Function O / EG lock control ata latch control Power down function Output level selector 0x-bit segment data I-directional shift register 0-bit data latch / common data I-directional shift register 0-bit level shifter 0-bit -level driver Generates latch clock (LK), shift clock (K) and control clock timing according to the input of L, L and control inputs (, A). In common driver application mode, this block generates the shift clock (LK) for the common data Bi-directional shift register. etermines the direction of segment data shift, and input data of each Bi-directional shift register. In -bit segment data parallel transfer mode, data is shifted by a -bit unit. In common driver application mode, data is transferred to the common data shift register directly, which disables this block. ontrols the clock enable state of the current driver according to the input value of enable pin ( or ). If enable input value is Low, every clock of the current driver is enabled and the clock control block works. But if enable input is High, current driver is disabled and the input data value has no effect on the output level. o power consumption can be lowered. ontrols the output voltage level according to the input control pin ( and IPOFFB) (refer to PIN ERIPTION). tores output data value by shifting the input values. In -bit serial interface mode application, all 0 shift clocks (K) are needed to store all the display data. But in -bit parallel transfer mode application, only 0 clocks are needed. In common driver application mode, this block does not work. In segment driver application mode, the data from the 0x-bit segment data shift register are latched for segment driver output. In single-type common driver application,-bit input data (from L or R pin) is shifted and latched by the direction according to the HL signal input. In dual-type common application mode, 0-bit registers are divided by two blocks and controlled independently (refer to NOTE ). Voltage level shifter block for high voltage part. The inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. These values are input in to the driver. elects the output voltage level according to and latched data value. If the data value is "High" the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the non-selected level (V or V). In segment driver application mode, non-selected output value is V or V. and when in common driver application, this value becomes V or V. O / EG EG EG O / EG EG O / EG EG EG

8 6B006 0H OON / EGENT RIVER FOR OT ATRIX L PIN ERIPTION Pin I / O Name Function Interface V Logical "High" input port (+5V ± 0%, +V ± 0%) V VEE V0, V, V, V5-0 L L IPOFFB I O I I I I I Power supply L driver output voltage level L driver output ata shift clock A signal for L driver output ata latch clock isplay OFF control O / EG mode control 0V (GN) Logical "Low" for high voltage part Bias supply voltage input to drive the L. Bias voltage divided by the resistance is usually used as a supply voltage source (refer to NOTE ). isplay data output pin which corresponds to the respective latch contents. One of V0, V, V and V5 is selected as a display driving voltage source according to the combination of the latched data level and signal (refer to NOTE ). lock pulse input for the bi-directional shift register. In segment driver application mode, the data is shifted to 0 x -bit segment data shift The clock pulse, which was input when the enable bit (/) is in not active condition, is invalid. In common driver application mode, the data is shifted to 0-bit common data bi-directional shift register by the L clock. Hence, this clock pin is not used (Open or connect this pin to V). Alternate signal input pin for L driving. Normal frame inversion signal is input in to this pin. In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. L pulse "High" level initializes power-down function block. In common driver application mode, L is used as a shifting clock of common output data. ontrol input pin to fix the driver output (0) to V0 level, during "Low" value input. L becomes non-selected by V0 level output from every output of segment drivers and every output of common drivers. When = "Low", 6B006 is used as an 0-bit segment driver. When = "High", 6B006 is set to an 0-bit common driver Power Power L ontroller ontroller ontroller ontroller V / V

9 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 According to the input value of the A and the pin, application mode of 6B006 is differs as shown below. A I Application mode select A Application mode O/EG 0 0 -bit parallel interface mode 0 -bit serial interface mode 0 ingle type application mode ual type application mode O V / V PIN ERIPTION (ONTINUE) Pin I / O Name Function Interface _I, _L, _, _R HL, I / O Input I / O isplay data input / serial input data / left, right data input output hift direction control Enable data input/output In segment driver application mode, these pins are used as -bit data input pin (when -bit parallel interface mode : A = "Low"), or _I is used as serial data input pin and other pins are not used (connect these to V) (when -bit serial interface mode : A = "High"). In common driver application mode, the data is shifted from _L(_R) to _R(_L), when in single type interface mode (A = "Low"). In dualtype application case, the data are shifted from _L and _ (_R and _) to _R(_L). In each case the direction of the data shift and the connection of data pins are determined by HL input (refer to NOTE, NOTE ). When HL = "Low", data is shifted from left to right. When HL = "High", the direction is reversed. (refer to NOTE) In segment driver application mode, the internal operation is enabled only when enable input ( or ) is Low (power down function). When several drivers are serially connected, the enable state of each driver is shifted according to the HL input. onnect these pins as below. egment river L Output (open) Input (V) H Input (V) Output (open) - In common driver application mode, power down function is not used. Open these pins. ontroller V/V 9

10 6B006 0H OON / EGENT RIVER FOR OT ATRIX L NOTE. Output Level ontrol Latched data IPOFFB Output level ( 0) EG ode O ode L L H V (V) V (V) L H H V0 V5 H L H V (V) V (V) H H H V5 V0 X X L V0 V0 0

11 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 () egment driver application ( = Low ) NOTE. L riving Voltage Application ircuit V V V0 R V R V (n-)r V R V R V5 VEE to O river to O river V0 V V V5 6B006 V EG- EG0 V0, V5 V, V to L Panel election Level Non-selection Level * n = 9 (when /6 duty) to (when /56 duty) () ommon driver application ( = High ) V V R R (n-)r V0 V V V to EG river V0 V V 6B006 O- O0 to L Panel R R V V5 VEE V V5 V V0, V5 V, V election Level Non-selection Level * n = 9 (when /6 duty) to (when /56 duty)

12 6B006 0H OON / EGENT RIVER FOR OT ATRIX L NOTE. ata hift irection according to ontrol ignals () When = Low (segment driver application) A HL Application mode ata irection Input Pin first data last data hift irection _I, _L, R -Bit Parallel ata Transfer ode (EG) L L first data hift irection last data H Last data (_I) first data hift irection first data Last data hift irection -Bit erial ata Transfer ode (EG) L H H _I

13 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 () When = High (common driver application) A HL Application mode ata irection Input Pin hift irection L _L L ingle-type Application ode (O) Input ata (_L) hift irection Output ata (_R) H _R Output ata (_L) Input ata (_R) hift irection L _L, _ H ual-type Application ode (O) Input ata (_L) Input ata (_) hift irection Output ata (_R) H _R, _ Output ata (_L) Input ata (_) Input ata (_R)

14 6B006 0H OON / EGENT RIVER FOR OT ATRIX L NOTE. Usage of ata Pins O / EG ( pin) EG ( = Low ) O ( = High ) Application mode (A pin) -bit parallel interface mode (A = Low ) -bit serial interface mode (A = High ) single-type application mode (A = Low ) dual-type application mode (A = High ) HL ata interface pin _I _L R X (input) (input) (input) (input) X I (input) onnect to V L L (input) R (output) open Open H L (output) R (input) L H open L (input) L (output) (input) (input) R (output) R (input) AXIU ABOLUTE LIIT haracteristic ymbol Value Unit Power supply voltage V river supply voltage VL 0 +0 V Input voltage VIN -0. V + 0. Operating temperature Topr torage temperature Tstg * NOTE: Voltage greater than above may do damage to the circuit.

15 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 ELETRIAL HARATERITI HARATERITI () egment river Application (V = 0V, Ta = ) haracteristic ymbol Test ondition in. Typ. ax. Unit Operating V Voltage V L V IN = V - V EE 6 - Input voltage () Output voltage () Input leakage current () Input leakage current () V IH - 0.V - V V IL V V OH I OH = -0.mA V V OL I OL = 0.mA I IL V IN = V to V -0-0 I IL V IN = V to V EE -5-5 On resistance () R ON I ON = 00µA - kω V V µa upply current (5) I TBY f L = khz = V V pin µa V = 5V I f L = khz ma V = V - - f = 0Hz I EE V = 5V µa NOTE:. Applied to L, L,,, _I - _R, HL, IPOFFB,,, A pin., pin. V0, V, V, V5 pin. V L = V - V EE, V0 = V = 5V, V5= V EE = - V V = V -/n(v L), V = V EE+/n(V L), n = (/56 duty, / bias) 5. V0 = V, V =.V(V = 5V) or -0.06V (V = V), V = -9. V(V = 5V) or -9.9V (V = V), V5 = V EE = -V, no-load condition (/56 duty, / bias) -bit parallel interface mode I TBY : V = 5V, f L = 5.Hz, HL = V, IPOFFB = V, = V, display data pattern = 0000 I : V = V, f L = Hz, display data pattern = 00 V = 5 V, f L = 5.Hz, display data pattern = 00 I EE : V = 5V, f L = 5.Hz, display data pattern = 00, V EE pin 5

16 6B006 0H OON / EGENT RIVER FOR OT ATRIX L HARATERITI (ONTINUE) () ommon river Application (V = 0V, Ta = ) haracteristic ymbol Test ondition in. Typ. ax. Unit Operating V voltage V L V IN = V - V EE 6 - Input voltage () V IH - 0.V - V V IL V Output voltage V OH I OH = -0.mA V () V OL I OL = 0.mA Input leakage current () Input leakage current () Input leakage current () I IL V IN = V to V -0-0 I IL V IN = 0V, V = 5V (PULL UP) I IL V IN = V to V EE -5-5 On resistance(5) R ON I ON = 00µA - kω upply current (6) I TBY f L = khz V pin V = 5V I f L = khz V = V f = 0Hz V = 5V I EE NOTE:. Applied to L, _L (HL = LOW), _R (HL = HIGH), HL, IPOFFB,,, A pin. Pull-up input pins : L, _I, _ (A = HIGH), (HL = LOW), (HL = HIGH). _L (HL = HIGH), _R (HL = LOW) pin. V0, V, V, V5 pin 5. V L = V -V EE, V0 = V = 5V, V5 = V EE = -V V = V -/n(v L), V = V EE+/n(V L), n = (/56 duty, / bias) 6. V0 = V, V =.5V (V = 5V) or.v (V = V), V = -.5V (V = 5 V) or -.V (V = V), V5 = V EE = - V, no-load condition (/56 duty, / bias) single-type mode operation : A = V, HL = V, IPOFFB = V _I = _ = V, _R = OPEN, = = OPEN, I TBY : V = 5V, = V, _L = V I : f = 0Hz, _L = V V = V, display data pattern = , , , ,.. V = 5 V, display data pattern = , , , ,.. I EE : f = 0Hz, _L = V V = 5V, current through V EE Pin, display data pattern = , , , V V µa µa 6

17 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 A HARATERITI () egment river Application haracteristic ymbol Test (V = 0V, Ta = ) () V = 5V ±0% () V = V ±0% ondition in. Typ. ax. in. Typ. ax. lock cycle time t Y uty = 50% lock pulse width t WK lock rise / fall time t R /t F ata set-up time t ata hold time t H lock set-up time t lock hold time t H Output 60 5 Propagation delay time t PHL Output 60 5 Input 0 65, set-up time t PU - - Input 0 65 IPOFFB low pulse width - - t WL µs IPOFFB clear time t ns - OUT propagation delay time L - OUT propagation delay time IPOFFB - OUT propagation delay time t P t P L = 5pF t P Unit ns µs

18 6B006 0H OON / EGENT RIVER FOR OT ATRIX L A HARATERITI (ONTINUE) () ommon river Application haracteristic ymbol Test (V = 0V, Ta = ) () V = 5 V ± 0% () V = V ±0% ondition in. Typ. ax. in. Typ. ax. lock cycle time t Y uty = 50% lock pulse width t WK lock rise / fall time t R /t F ata set-up time t ata hold time t H IPOFFB low pulse width t WL µs IPOFFB clear time t Output delay time t L OUT propagation delay time L - OUT propagation delay time IPOFFB - OUT propagation delay time t P L = 5pF t P t P Unit ns ns µs

19 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 A HARATERITI (ONTINUE) () egment river Application Timing L 0.V 0.V t WK 0.V 0.V t t H L 0.V 0.V 0.V t WK tf t WK 0.V 0.V 0.V _I - _R t R t Y t t H 0.V 0.V t WL t IP0FFB L L, (Output ) V t PHL 0.V 0.V, (Input ) 0.V t PU 0.V 0.V t P L 0.V t P IPOFFB 0.V 0.V t P - 0 (Latched ata) 9

20 6B006 0H OON / EGENT RIVER FOR OT ATRIX L A HARATERITI (ONTINUE) () ommon river Application Timing t Y L 0.V 0.V t R t WKH t F 0.V 0.V t F t t H (*) I 0.V 0.V 0.V 0.V t L (*) O 0.V twl t 0.V IP0FFB (*) When in single-type interface mode I => _L (HL = L), _R (HL = H) O => _R (HL = L ), _L (HL = H) When in dual-type interface mode I => _L and _ (HL = L), _R and _ (HL = H) O => _R (HL = L), _L (HL = H) 0.V 0.V t P L 0.V t P IPOFFB 0.V 0.V t P - 0 (Latched ata 0

21 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 POWER OWN FUNTION In the case of cascade connection of segment mode drivers, 6B006 has a "power down function" In order to reduce the power consumption. HL Enable input Enable output urrent driver status The other drivers status L H While ="Low", current driver is enabled. While ="Low", current driver is enabled. isabled isabled * In the case of common driver application, power down function does not work. L L n- n n- n n- n n- n n- (input) / (Output/Input) / (Output/Input) / (Output/Input) (Output) NOTE:. HL = High (EBL = Input, = Output) urrent 6A006's must be connected to the next 6A006's.. When in -bit parallel interface mode: n = 0 When in -bit serial interface mode: n = 0

22 6B006 0H OON / EGENT RIVER FOR OT ATRIX L OPERATION TIING IAGRA () -bit Parallel ode Interface egment river When HL = "Low" L _I _L R (Input) (Output) L - 0 When HL = High L _I _L R (Input) (Output) L - 0

23 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 () -bit erial ode Interface egment river When HL = Low L _I (Input) (Output) L - 0 When HL = High L _I (Input) (Output) L - 0

24 6B006 0H OON / EGENT RIVER FOR OT ATRIX L () ingle-type Interface ode ommon river When HL = Low L _L _R O_ATA O_ATA O_ATA O_ATA9 O_ATA0 urrent river's OON area When HL = High L _R _L O_ATA O_ATA O_ATA O_ATA9 O_ATA0 urrent river's OON area

25 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 () UAL-type Interface ode ommon river When HL = Low L _L R O_ATA O_ATA O_ATA O_ATA9 O_ATA0 O_ATA O_ATA O_ATA O_ATA9 O_ATA0 When HL = High L _L R O_ATA O_ATA O_ATA O_ATA9 O_ATA0 O_ATA O_ATA O_ATA O_ATA9 O_ATA0 5

26 6B006 0H OON / EGENT RIVER FOR OT ATRIX L (5) ommon / egment river Timing (/00 UTY) L Latched ata (EG) O_ATA O_ATA99 O_ATA00 O V0 V V V5 O99 O00 V0 V V V5 V0 V V V5 EG_ATA EG V0 V V V V V5 L 9 0 L - Latched_ata Enable Out 6

27 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 APPLIATION INFORATION -bit erial Interface ode (0-h. egment river) a) Lower View (HL = L, A = H ) L PANEL 0 60 n n A HL _I _L- _R A HL _I _L- _R A HL _I _L- _R -bit serial data input b) Upper View (HL = H, A = H) -bit serial data input _I _L- _R HL A 0 _L- _R _I HL A 0 _L- _R _I HL A n n+0 L PANEL

28 6B006 0H OON / EGENT RIVER FOR OT ATRIX L -Bit Parallel Interface ode (0 h. egment river) a) Lower View (HL = L, A = L ) L PANEL 0 60 n n A A A HL _I-_R HL _I-_R HL _I-_R -bit serial data input b) Upper View (HL = H, A = L) -bit serial data input _I-_R HL A 0 _I-_R HL A 0 _I-_R HL A n n+0 L PANEL

29 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 ingle-type Interface ode (0 h. ommon river) input data _R 0 A HL _L 0 _R 0 L PANEL A HL _L 60 _R 6 A HL _L 0 9

30 6B006 0H OON / EGENT RIVER FOR OT ATRIX L ual-type Interface ode (0 h. + 0 h. ommon river) input data _R 0 A HL _L 0 _R 0 L PANEL (/) A HL _L 60 input data R 0 6 A HL _L 0 _R 0 A HL _L 0 L PANEL (/) _R 0 A HL _L 00 NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half. In case, /00 duty can be used to drive the 00 common L panel. 0

31 0H OON / EGENT RIVER FOR OT ATRIX L 6B006 APPLIATION IRUIT EXAPLE V R R (n-)r R R O /EG V O V EG V EG V O V5 O /EG V0-V5 IPOFFB A HL _I - _R 6B006 EG - EG0 L L 0 V0-V5 _I - _R IPOFFB L L 6B006 A HL EG - EG0 0 V0-V5 _I - _R IPOFFB L L 6B006 A HL EG - EG0 0 V VEE IPOFFB _R A HL V0-V5 O - O0 6B006 L _L 0 IPOFFB _R 0 0 x 0 L OULE A HL V0-V5 O - O0 6B006 L _L 6 ontroller IPOFFB FRAE() O_ATA - L L IPOFFB A HL V0-V5 L _R 0 O - O0 6B006 _L 6 0