High Speed MOSFET Drivers
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1 High Speed MOSFET Drivers AS / AS9 FEATURES Latch Up Protected >.A Logic Input Swing Negative ESD k Matched Rise and Fall Times ns APPLICATIONS Motor Controls Switch-Mode Power Supplies Pulse Transformer Driver Class D Switching Amplifiers DESCRIPTION The AS and AS9 family operate over. to 8, can withstand high current peaking of 6A and have matched rise and fall times under ns. The product has been designed utilizing Calogic s rugged CMOS process with protection for latch up and ESD. The product is available in inverting (AS9) and noninverting (AS) configurations. ORDERING INFORMATION Part# Logic Package Temperature Range ASP Noninverting 8-Pin PDIP - C to +8 C o o ASS Noninverting AS9P Inverting AS9S Inverting 8-Pin SOIC - o C to +8 o C 8-Pin PDIP - o C to +8 o C 8-Pin SOIC - o C to +8 o C FUNCTIONAL DIAGRAM AND PIN CONFIGURATIONS DIP SOIC DD 8 DD D D 8 D D NC 7 6 NC 7 6 A-7 A-8 DD ì m.7 AS / AS9 EFFECTIE C = 8pF L- CALOGIC, 7 Whitney Place, Fremont, California 99, Telephone: -66-9, FAX: -6-76
2 AS / AS9 ABSOLUTE MAXIMUM RATINGS Supply oltage Static-sensitive device. Unused devices must be stored in Input oltage to >DD conductive material. Protect devices from static discharge Input Current (IN > DD) ma Power Dissipation, TA < o and static fields. Stresses above those listed under "Absolute C Maximum Ratings" may cause permanent damage to the PDIP W device. These are stress ratings only and functional operation SOIC mw of the device at these or any other conditions above those Derating Factors (To Ambient) PDIP mW/ o C indicated in the operation sections of the specifications is not SOIC mw/ o C implied. Exposure to absolute maximum rating conditions for Storage Temperature Range o C to + o C extended-periods may affect device reliability. Operating Temperature (Chip) o C Operating Temperature Range (Ambient) C ersion o C to +7 o C E ersion o C to +8 o C Lead Temperature (Soldering, sec) o C ELECTRICAL CHARACTERISTICS: TA = + o C with. < DD < 8, unless otherwise specified. SYMBOL PARAMETER MIN TYP MAX UNIT TEST CONDITIONS IH IL IN (Max) Logic High Input oltage Logic Low Input oltage Input oltage Range DD+. IIN Input Current - A < IN < DD OH High Output oltage DD-. OL Low Output oltage RO Output Resistance, High RO Output Resistance, Low IPK Peak Output Current A See Figure See Figure IOUT = ma, DD = 8 IOUT = ma, DD = 8 DD = 8 (See Figure ) IRE Latch-Up Protection Withstand Reverse Current >. t A Duty Cycle < % < ìa SWITCHING TIME (Note ) tr Rise Time ns Figure, CL = pf tf Fall Time ns Figure, CL = pf td Delay Time ns Figure td Delay Time ns Figure POWER SUPPLY IS Power Supply Current DD Operating Input oltage. ma A. 8 IN = IN = CALOGIC, 7 Whitney Place, Fremont, California 99, Telephone: -66-9, FAX: -6-76
3 AS / AS9 ELECTRICAL CHARACTERISTICS: Measured over operating temperature range with. ~ DD ~ 8, unless otherwise specified. SYMBOL PARAMETER MIN TYP MAX UNIT TEST CONDITIONS IH Logic High Input oltage. IL Logic Low Input oltage.8 IN (Max) Input oltage Range - DD+. IIN Input Current - LA ~ IN ~ S OH High Output oltage DD-. See Figure OL Low Output oltage. See Figure RO Output Resistance, High IOUT = ma, DD = 8 RO Output Resistance, Low. SWITCHING TIME (Note ) Ω I O U T = ma, DD = 8 tr Rise Time 6 ns Figure, CL = pf tf Fall Time 6 ns Figure, CL = pf td Delay Time ns Figure td Delay Time ns Figure POWER SUPPLY IS Power Supply Current 6 ma L IN = IN = DD Operating Input oltage. 8 Note:. Switching times guaranteed by design. FIGURE. SWITCHING TIME TEST CIRCUIT DD = 8.LF + 9%.LF 8.LF. % t D t F t D t R % 9% 7 C L = pf % % : khz, SQUARE WAE, trise = t FALL~ ns A- A-9 CALOGIC, 7 Whitney Place, Fremont, California 99, Telephone: -66-9, FAX: -6-76
4 AS / AS9 TYPICAL CHARACTERISTICS CURES RISE TIME vs SUPPLY OLTAGE FALL TIME vs SUPPLY OLTAGE 8 C L =, pf 8 6 C L =, pf 6 C L = 7 pf C L = pf C L = 7 pf C L = pf 7 9 DD () L- 7 9 DD () L- RISE AND FALL TIMES vs TEMPERATURE CL = pf DD = 8 8 RISE TIME vs CAPACITIE LOAD 6 DD = t FAL t RISE DD = DD= T A ( C) L-6, CAPACITE LOAD (pf) L-7 FALL TIME vs CAPACITIE LOAD 6 PROPAGATION DELAY TIME vs SUPPLY OLTAGE DD = t D DD = DD = 8 t D, CAPACITE LOAD (pf) L-8 SUPPLY OLTAGE () A-6 CALOGIC, 7 Whitney Place, Fremont, California 99, Telephone: -66-9, FAX: -6-76
5 AS / AS9 TYPICAL CHARACTERISTICS CURES (Cont.) PROPAGATION DELAY TIME vs TEMPERATURE CL = pf 8 SUPPLY CURRENT vs CAPACITY LOAD DD = DD = 8 7 t D 6 t D 8 khz -6-6 T A ( C) A-7 khz khz, CAPACITIE LOAD (pf) A-8 SUPPLY CURRENT vs FREQUENCY CL = pf 8 6 THERMAL DERATING CURE 8 DIP 8 SOIC 8 CerDIP 8 6, FREQUENCY (khz) A AMBIENT TEMPERATURE ( C) L-9. LOW-STATE RESISTANCE HIGH-STATE RESISTANCE ma ma ma ma ma. ma DD () A- DD () A- CALOGIC, 7 Whitney Place, Fremont, California 99, Telephone: -66-9, FAX: -6-76
6 AS / AS9 TYPICAL CHARACTERISTICS CURES (Cont.) EFFECT OF AMPLITUDE ON PROPAGATION DELAY LOAD = pf TOTAL na S CROSSOER* AND DD () A SUPPLY OLTAGE () * The values on this graph represent the loss seen by the driver during one complete cycle. For a single transition, divide the value by. A- IN DD DD OUT OUT DIE SIZE 76x77 (mm) CALOGIC, 7 Whitney Place, Fremont, California 99, Telephone: -66-9, FAX: -6-76
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MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high
MM74HCT138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Data sheet acquired from Harris Semiconductor SCHS171D November 1997 - Revised October 2003 High-Speed CMOS Logic Quad 2-Input Multiplexer with Three-State
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
September 1983 Revised February 1999 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate
MM82C19 16-Line to 1-Line Multiplexer
16-Line to 1-Line Multiplexer General Description The multiplex 16 digital lines to 1 output. A 4-bit address code determines the particular 1-of-16 inputs which is routed to the output. The data is inverted
MM74HC251 8-Channel 3-STATE Multiplexer
8-Channel 3-STATE Multiplexer General Description The MM74HC251 8-channel digital multiplexer with 3- STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and
74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device
PO3B14A. Description. Truth Table. High Bandwidth Potato Chip V CC N.C. EN EN S 1 A 3 B 3 B 2 A 2 A 1 B 1 Y A Y B GND
www.potatosemi.com FEATURES: Patented technology High signal -3db passing bandwidth at 1.2GHz Near-Zero propagation delay VCC = 1.65V to 3.6V Ultra-Low Quiescent Power: 0.1 A typical Ideally suited for
MM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.
CD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each
UNISONIC TECHNOLOGIES CO., LTD U74HC14
UNISONIC TECHNOLOGIES CO., LTD U74HC14 HIGH-SPEED CMOS LOGIC HEX INVERTING SCHMITT TRIGGER DESCRIPTION The UTC U74HC14 each contain six inverting Schmitt triggers in one package. Each of them perform the
LNTA4001NT1G S-LNTA4001NT1G. Small Signal MOSFET 20 V, 238 ma, Single, N-Channel, Gate ESD Protection LESHAN RADIO COMPANY, LTD.
Small Signal MOSFET V, 38 ma, Single, N-Channel, Gate ESD Protection Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate Pb-Free Package is Available ESD Protected:V
IL33290 TECHNICAL DATA. ISO K Line Serial Link Interface
TECHNICAL DATA ISO K Line Serial Link Interface The IL33290 is a serial link bus interface device designed to provide bidirectional half-duplex communication interfacing in automotive diagnostic applications.