ML ML Digital to Analog Converters with Serial Interface
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- Oswin Barrett
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1 OS LSI L L Digital to Analog onverters with Serial Interface Legacy Device: otorola/reescale, The L and L are low cost 6 bit D/A converters with serial interface ports to provide communication with OS microprocessors and microcomputers. The L contains six static D/A converters; the L contains four converters. Due to a unique feature of these DAs, the user is permitted easy scaling of the analog outputs of a system. Over a to V supply range, these DAs maybe directly interfaced to OS PUs operating at V. P DIP = VP PLASTI DIP ASE 707 Direct R R Network Outputs uffered Emitter ollower Outputs Serial Data Input Digital Data Output acilitates ascading Direct Interface to OS µp Wide Operating Voltage Range:. to V Wide Operating Temperature Range: TA = 0 to Software Information is ontained in Document 6HR/AD 0 SO 0W = -6P SOG PAAGE ASE 7D LO DIAGRA Q OUT R OUT Qn Rn OUT OUT 6 P DIP = P PLASTI DIP ASE 66 SO 6W = -P SOG PAAGE ASE 7G R R R R R R R R R R R R HEX UER (INVERTING) ROSS REERENE/ORDERING INORATION PAAGE OTOROLA LANSDALE P DIP P LVP SO 0W DW L-6P P DIP P LP SO 6W DW L-P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from L to LE. HEX LATH L * D Q D 6 IT SHIT REGISTER * Transparent Latch Page of
2 L, L PIN ASSIGNENTS LVP L-6P 0 Q Out 7 Q Out 9 R Out 3 6 R6 Out R Out 3 R6 Out Q Out Q6 Out Q Out 7 Q6 Out R Out R Out R Out 6 R Out Q3 Out 6 3 Q Out Q3 Out 6 Q Out R3 Out 7 R Out R3 Out 7 R Out Q Out 3 Q Out 9 L 9 L N N LP L-P 6 Q Out 3 Q Out R Out 3 R Out R Out 3 R Out Q Out Q Out Q Out 3 Q Out R Out R3 Out R Out R3 Out 6 9 Q3 Out 6 Q3 Out 7 L 7 L N 9 N N = NO ONNETION Page of
3 L, L AXIU RATINGS* (Voltages referenced to ) Parameter Symbol Value Unit D Supply Voltage 0. to + V Input Voltage, All Inputs Vin 0. to + 0. V D Input urrent, per Pin I ± ma Power Dissipation (Per Output) TA = 70, TA =, Power Dissipation (Per Package) TA = 70, TA =, POH PD mw mw This device contains protection circuitry to guard against damage due to high static voltages or electric fields; however, it is advised that precautions be taken to avoid application of voltage higher than maximum rated voltages to this high impedance circuit. or proper operation it is recommended that Vin and Vout be constrained to the range (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Storage Temperature Range Tstg 6 to + 0 * aximum Ratings are those values beyond which damage to the device may occur. ELETRIAL HARATERISTIS (Voltages referenced to, TA = 0 to unless otherwise indicated) Symbol Parameter Test onditions in ax Unit VIH High Level Input Voltage (,, L) VIL Low Level Input Voltage (,, L) IOH High Level Output urrent () Vout = 0. V 00 µa IOL Low Level Output urrent () Vout = 0. V 00 µa IDD Quiescent Supply urrent L L Iout = 0 µa Iin Input Leakage urrent (,, L) Vin = or 0 V ± µa Vnonl Nonlinearity Voltage (Rn Out) See igure Vstep Step Size (Rn Out) See igure Voffset Offset Voltage from = $00, See igure LS IE Emitter Leakage urrent VRn Out = 0 V µa he D urrent Gain IE = 0. to.0 ma TA = V V ma mv mv 0 VE ase to Emitter Voltage Drop IE =.0 ma V Page 3 of
4 L, L SWITHING HARATERISTIS (Voltages referenced to, TA = 0 to, L = 0 p, Input tr = tf = 0 ns unless otherwise indicated) Symbol Parameter in ax Unit twh Positive Pule Width, L (igures 3 and ) twl Negative Pulse Width, L (igure 3 and ) tsu Setup Time, to L (igures 3 and ) tsu Setup Time, to L (igures 3 and ) th Hold Time, L to (igures 3 and ) th Hold Time, L to (igures 3 and ) tr, tf Input Rise and all Times in Input apacitance 7. p ns O UTPUT Rn Out, % (V D D V S S ) $00 Voffset IDEAL $0 3 $ Vnonl PROGRA STEP 7 $ LINEARITY ERROR (integral linearity). A measure of how straight a device s transfer function is, it indicates the worst case deviation of linearity of the actual transfer function from the best fit straight line. It is normally specified in parts of an LS. igure. D/A Transfer unction ATUAL 63 $3 Page of
5 L, L VRn OUT STEP SIZE Step Size = ± (or any adjacent pair of digital numbers) DIGITAL NUER igure. Definition of Step Size 0% tsu th L 0% N twh twl D D DN tsu th igure 3. Serial Input, Positive lock tsu th L N twl twh D D DN tsu th igure. Serial Input, Negative lock Page of
6 L, L INPUTS Data Input PIN DESRIPTIONS Six bit words are entered serially, S first, into digital data input,. Six words are loaded into the L during each D/A cycle; four words are loaded into the L. The last 6 bit word shifted in determines the output level of pins Q Out and R Out. The next to last 6 bit word affects pins Q Out and R Out, etc. Negative Logic Enable The pin must be low (active) during the serial load. On the low to high transition of, data contained in the shift register is loaded into the latch. L Shift Register lock Data is shifted into the register on the high to low transition of L. L is fed into the D input of a transparent latch, which is used for inhibiting the clocking of the shift register when is high. The number of clock cycles required for the L is usually 36. The L usually uses cycles. SeeTable for additional information. OUTPUTS Data Output The digital data output is primarily used for cascading the DAs and may be fed into of the next stage. R Out through Rn Out Resistor Network Outputs These are the R R resistor network outputs. These outputs may be fed to high impedance input ET op amps to bypass the on chip bipolar transistors. The R value of the resistor network ranges from 7 to kω. Q Out through Qn Out NPN Transistor Outputs uffered DA outputs utilize an emitter follower configuration for current gain, thereby allowing interface to low impedance circuits. SUPPLY PINS Negative Supply Voltage This pin is usually ground. Positive Supply Voltage The voltage applied to this pin is used to scale the analog output swing from. to V p p. Table. Number of hannels vs locks Required Number of hannels Required Number of lock ycles Outputs Used on L Outputs Used on L 6 Q/R Q/R Q/R, Q/R Q/R, Q/R 3 Q/R, Q/R, Q3/R3 Q/R, Q/R, Q3/R3 Q/R, Q/R, Q3/R3, Q/R Q/R, Q/R, Q3/R3, Q/R 30 Q/R, Q/R, Q3/R3, Q/R, Q/R Not Applicable 6 36 Q/R, Q/R, Q3/R3, Q/R, Q/R, Q6/R6 Not Applicable Page 6 of
7 L, L OUTLINE DIENSIONS P DIP = VP (LVP) PLASTI DIP ASE NOTES:. POSITIONAL TOLERANE O LEADS (D), SHALL E WITHIN 0. (0.0) AT AXIU ATERIAL ONDITION, IN RELATION TO SEATING PLANE AND EAH OTHER.. DIENSION L TO ENTER O LEADS WHEN ORED PARALLEL. 3. DIENSION DOES NOT INLUDE OLD LASH. H G A D N SEATING PLANE L DI A D G H L N ILLIETERS IN AX S S INHES IN AX S S A X P 0.0 (0.) SO 0W = -6P (L-6P) SOG PAAGE ASE 7D 0 NOTES:. DIENSIONING AND TOLERANING PER ANSI Y., 9.. ONTROLLING DIENSION: ILLIETER. 3. DIENSIONS A AND DO NOT INLUDE OLD PROTRUSION.. AXIU OLD PROTRUSION 0.0 (0.006) PER SIDE.. DIENSION D DOES NOT INLUDE DAAR PROTRUSION. ALLOWALE DAAR PROTRUSION SHALL E 0.3 (0.00) TOTAL IN EXESS O D DIENSION AT AXIU ATERIAL ONDITION. 0X D 0.0 (0.) T A S S X G T SEATING PLANE R X ILLIETERS INHES DI IN AX IN AX A D G.7 S 0.00 S P R Page 7 of
8 L, L 7 A H G D N SEATING PLANE OUTLINE DIENSIONS P DIP = P (LP) PLASTI DIP ASE L NOTES:. LEADS WITHIN 0.3 (0.00) RADIUS O TRUE POSITION AT SEATING PLANE AT AXIU ATERIAL ONDITION.. DIENSION L TO ENTER O LEADS WHEN ORED PARALLEL. 3. DIENSION DOES NOT INLUDE OLD LASH.. ROUNDED ORNERS OPTIONAL. INHES ILLIETERS DI IN AX IN AX A D G 0.0 S. S H L S 7.6 S 0 0 N A 6 9 6X D X G 0.0 (0.) T A S S X P T SEATING PLANE 0.0 (0.) SO 6W = -P (L-P) SOG PAAGE ASE 7G 0 R X NOTES:. DIENSIONING AND TOLERANING PER ANSI Y., 9.. ONTROLLING DIENSION: ILLIETER. 3. DIENSIONS A AND DO NOT INLUDE OLD PROTRUSION.. AXIU OLD PROTRUSION 0. (0.006) PER SIDE.. DIENSION D DOES NOT INLUDE DAAR PROTRUSION. ALLOWALE DAAR PROTRUSION SHALL E 0.3 (0.00) TOTAL IN EXESS O D DIENSION AT AXIU ATERIAL ONDITION. ILLIETERS INHES DI IN AX IN AX A D G.7 S 0.00 S P R Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Typical parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by the customer s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page of
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Rev. 03 4 February 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.
PART TOP VIEW. Maxim Integrated Products 1
9-96; Rev ; 2/ 45, SPDT Analog Switch in SOT23-8 General Description The is a dual-supply, single-pole/doublethrow (SPDT) analog switch. On-resistance is 45 max and flat (7 max) over the specified signal
Precision, Quad, SPDT, CMOS Analog Switch
19-0189; Rev 1; 6/99 Precision, Quad, SPDT, MOS Analog Switch General Description The is a precision, quad, single-pole doublethrow (SPDT) analog switch. The four independent switches operate with bipolar
MM74HC373 3-STATE Octal D-Type Latch
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Dual D Flip-Flop with Set and Reset
TECNICAL DATA IN74C74A Dual D Flip-Flop with Set and Reset The IN74C74A is identical in pinout to the LS/ALS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they
12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS
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Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. September 2001 S7C256 5V/3.3V 32K X 8 CMOS SRM (Common I/O) Features S7C256
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM MAY 1999 FEATURES High-speed access time: 10, 12, 15, 20, 25 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
SN54HC153, SN74HC153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
Permit Multiplexing from n Lines to One Line Perform Parallel-to-Serial Conversion Strobe (Enable) Line Provided for Cascading (N Lines to n Lines) Package Options Include Plastic Small-Outline (D), Thin
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
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MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
SEMICONDUCTOR TECHNICAL DATA
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UT54ACS164/UT54ACTS164 8-Bit Shift Registers January, 2018 Datasheet
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74LS195 SN74LS195AD LOW POWER SCHOTTKY
The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped
MM74HC573 3-STATE Octal D-Type Latch
MM74HC573 3-STATE Octal D-Type Latch General Description The MM74HC573 high speed octal D-type latches utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low
AVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) CERAMIC DIP (JG) TL7702ACD TL7715ACD TL7702ACP TL7715ACP TL7702ACY TL7715ACY
Power-On Reset Generator Automatic Reset Generation After Voltage Drop Wide Supply Voltage Range Precision Voltage Sensor Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally
INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook
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Dual J-K Flip-Flop with Set and Reset
TECNICAL DATA IN74C109A Dual J-K Flip-Flop with Set and Reset igh-performance Silicon-ate CMOS The IN74C109A is identical in pinout to the LS/ALS109. The device inputs are compatible with standard CMOS
74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger
INTEGRATED IRUITS positive-edge trigger Supersedes data of 1996 Nov 07 I24 Data andbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0 to 3.6V Accepts
Low Drift, Low Power Instrumentation Amplifier AD621
a FEATURES EASY TO USE Pin-Strappable Gains of 0 and 00 All Errors Specified for Total System Performance Higher Performance than Discrete In Amp Designs Available in -Lead DIP and SOIC Low Power,.3 ma
DATASHEET CD4093BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad 2-Input NAND Schmitt Triggers
DATASHEET CD9BMS CMOS Quad -Input NAND Schmitt Triggers FN Rev. December 199 Features High Voltage Types (V Rating) Schmitt Trigger Action on Each Input With No External Components Hysteresis Voltage Typically.9V
SN54/74LS145 1-OF-10 DECODER/DRIVER OPEN-COLLECTOR 1-OF-10 DECODER/ DRIVER OPEN-COLLECTOR FAST AND LS TTL DATA 5-240
-OF-0 DECODER/DRIVER OPEN-COLLECTOR The SN54 / 74LS45, -of-0 Decoder/Driver, is designed to accept BCD inputs and provide appropriate outputs to drive 0-digit incandescent displays. All outputs remain
74LVC573 Octal D-type transparent latch (3-State)
INTEGRATED CIRCUITS 74VC573 Supersedes data of February 1996 IC24 Data andbook 1997 Mar 12 74VC573 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance with JEDEC standard no. 8-1A Inputs accept
Figure 1. Pinout: 16 Lead Packages Conductors (Top View) ORDERING INFORMATION Figure 2. Logic Symbol PIN ASSIGNMENT
The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC354 M74HC354 8 CHANNEL MULTIPLEXER/REGISTER (3 STATE) tpd = 24 ns (TYP.
M54HC354 M74HC354 8 CHANNEL MULTIPLEXER/REGISTER (3 STATE). HIGH SPEED tpd = 24 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT
HCF4532B 8-BIT PRIORITY ENCODER
8-BIT PRIORITY ENCODER CONVERTS FROM 1 TO 8 TO INPUTS BINARY PROVIDES CASCADING FEATURE TO HANDLE ANY NUMBER OF INPUTS GROUP SELECT INDICATES ONE OR MORE PRIORITY INPUTS QUIESCENT CURRENT SPECIFIED UP
SN74LS138MEL LOW POWER SCHOTTKY
The LSTTL/MSI SN74LS18 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
74HC594; 74HCT bit shift register with output register
Rev. 03 20 December 2006 Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The is
Miniature Electronically Trimmable Capacitor V DD. Maxim Integrated Products 1
19-1948; Rev 1; 3/01 Miniature Electronically Trimmable Capacitor General Description The is a fine-line (geometry) electronically trimmable capacitor (FLECAP) programmable through a simple digital interface.