SEMICONDUCTOR TECHNICAL DATA

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1 SEMIONDUTOR TEHNIAL DATA The M14560B adds two 4 bit numbers in NBD (natural binary coded decimal) format, resulting in sum and carry outputs in NBD code. This device can also subtract when one set of inputs is complemented with a 9 s omplementer (M14561B). All inputs and outputs are active high. The carry input for the least significant digit is connected to VSS for no carry in. Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc apable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit D Supply Voltage 0.5 to V Vin, Vout Input or Output Voltage (D or Transient) 0.5 to V Iin, Iout Input or Output urrent (D or Transient), per Pin ± ma PD Power Dissipation, per Package 500 mw Tstg Storage Temperature 65 to + 0 TL Lead Temperature (8 Second Soldering) 260 * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ From 65 To 125 eramic L Packages: 12 mw/ From 0 To 125 Input TRUTH TABLE* Output A3 B4 B3 B2 B1 in out S4 S3 S2 S * Partial truth table to show logic operation for representative input values. BLOK DIAGRAM L SUFFIX ERAMI ASE 620 ORDERING INFORMATION M14XXXBP M14XXXBL M14XXXBD P SUFFIX PLASTI ASE 648 D SUFFIX SOI ASE 751B Plastic eramic SOI TA = 55 to 125 for all packages. 7 in S B1 S B2 A3 B3 B4 S3 S4 out = PIN 16 VSS = PIN 8 9 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or ). Unused outputs must be left open. REV 30 1/94 MOTOROLA Motorola, Inc MOS LOGI DATA M14560B 1

2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELETRIAL HARATERISTIS (Voltages Referenced to VSS) haracteristic Output Voltage Vin = or 0 Vin = 0 or 0 Level 1 Level Input Voltage 0 Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive urrent (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) 1 Level Source Sink Symbol VOL VOH VIL VIH IOH Vdc Min Max Min Typ # Max Min Max Unit IOL Input urrent Iin ±0.1 ± ±0.1 ±1.0 µadc Input apacitance (Vin = 0) in 7.5 pf Vdc Vdc Vdc Vdc madc madc Quiescent urrent (Per Package) Total Supply urrent** (Dynamic plus Quiescent, Per Package) (L = 50 pf on all outputs, all buffers switching) IDD IT IT = (1.68 µa/khz) f + IDD IT = (3.35 µa/khz) f + IDD IT = (3 µa/khz) f + IDD #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. ** The formulas given are for the typical characteristics only at 25. To calculate total supply current at loads other than 50 pf: IT(L) = IT(50 pf) + (L 50) Vfk where: IT is in µa (per package), L in pf, V = ( VSS) in volts, f in khz is input frequency, and k = µadc µadc PIN ASSIGNMENT 1 16 B2 2 A B1 B S S2 B4 6 S3 in 7 S4 VSS 8 9 out M14560B 2 MOTOROLA MOS LOGI DATA

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITHING HARATERISTIS* (L = 50 pf, TA = 25 ) Output Rise and Fall Time ttlh, tthl = (1.5 ns/pf) L + 25 ns ttlh, tthl = (0.75 ns/pf) L ns ttlh, tthl = (0.55 ns/pf) L ns haracteristic Symbol Min Typ # Max Unit Propagation Delay Time A or B to S tplh, tphl = (1.7 ns/pf) L ns tplh, tphl = (0.66 ns/pf) L ns tplh, tphl = (0.5 ns/pf) L ns A or B to out tplh, tphl = (1.7 ns/pf) L ns tplh, tphl = (0.66 ns/pf) L ns tplh, tphl = (0.5 ns/pf) L ns in to out tplh, tphl = (1.7 ns/pf) L ns tplh, tphl = (0.66 ns/pf) L ns tplh, tphl = (0.5 ns/pf) L ns Turn Off Delay Time in to S tplh = (1.7 ns/pf) L + 7 ns tplh = (0.66 ns/pf) L ns tplh = (0.5 ns/pf) L + 2 ns Turn On Delay Time in to S tphl = (1.7 ns/pf) L ns tphl = (0.66 ns/pf) L ns tphl = (0.5 ns/pf) L ns ttlh, tthl tplh, tphl * The formulas given are for the typical characteristics only at 25. #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. tplh tphl ns ns ns ns ns ns 20 ns 20 ns ALL INPUTS 90% 50% % 1 2f VSS ANY INPUT 90% 50% % 20 ns 20 ns VSS ANY OUTPUT VOH tplh tphl VOL Duty ycle = 50% All outputs connected to respective L loads f = System clock frequency ANY OUTPUT ttlh 50% % 90% tthl VOH VOL Figure 1. Power Dissipation Waveforms Figure 2. Switching Time Waveforms MOTOROLA MOS LOGI DATA M14560B 3

4 FUNTIONAL EQUIVALENT LOGI DIAGRAM 7 in 14 B1 1 2 B2 3 A3 4 B3 5 6 B4 13 S1 12 S2 S3 S4 9 out = PIN 16 VSS = PIN 8 ADD/SUBTRAT M14561B One M14560B and M14561B permit a BD digit to be added to or subtracted from a second digit, such as in this typical configuration. A second M14561B permits either digit to be added to or subtracted from the other, or either word to appear unmodified at the output. ero Add/Subtract Result B plus A B minus A 1 X B X = Don t are TRUTH TABLE ERO B1 A B F1 A3 F2 OMP F3 OMP F4 M14561B A3 OMP OMP F1 F2 F3 F4 M14560B in A3 B1 B2 B3 B4 M14560B in A3 B1 B2 B3 B4 S1 S2 S3 S4 out S1 S2 S3 S4 out UNITS TENS Figure 3. Parallel Add/Subtract ircuit M14560B 4 MOTOROLA MOS LOGI DATA

5 APPLIATIONS INFORMATION INTRODUTION Frequently in small digital systems, simple decimal arithmetic is performed. Decimal data enters and leaves the system arithmetic unit in a binary coded decimal (BD) format. The adder/subtracter in the arithmetic unit may be required to accept sign as well as magnitude, and generate sign, magnitude, and overflow. In the past, it has been cumbersome to build sign and magnitude adder/subtracters. Now, using Motorola s MSI MOS functions, the M14560 NBD Adders and M s omplementers, NBD adder/ subtracters may be built economically, with surprisingly low package count and moderate speed. Some background information on BD arithmetic is presented here, followed by simple circuits for unsigned adder/ subtracters. The final circuit discussed is an adder/subtracter for signed numbers with complete overflow and sign correction logic. DEIMAL NUMBER REPRESENTATION Because logic elements are binary or two state devices, decimal digits are generally represented as a group of bits in a weighted format. There are many possible binary codes which can be used to represent a decimal number. One of the most popular codes using 4 binary digits to represent 0 thru 9 is Natural Binary oded Decimal (NBD or code). NBD is a weighted code. If a value of 0 or 1 is assigned to each of the bit positions, where the rightmost position is 20 and the leftmost is 23, and the values are summed for a given code, the result is equal to the decimal digit represented by the code. Thus, 01 equals = = 6. The,, 10,,, and binary codes are not used. Because of these illegal states, the addition and subtraction of NBD numbers is more complex than similar calculations on straight binary numbers. ADDITION OF UNSIGNED NBD NUMBERS When 2 NBD digits, A and B, and a possible carry,, are added, a total of 20 digit sums (A + B + ) are possible as shown in Table 1. The binary representations for the digit sums thru 19 are offset by 6, the number of unused binary states, and are not correct. An algorithm for obtaining the correct sum is shown in Figure 1. A conventional method of implementing the BD addition algorithm is shown in Figure 2(a). The NBD digits, A and B, are summed by a 4 bit binary full adder. The resultant (sum and carry) is input to a binary/bd code converter which generates the correct BD code and carry. An NBD adder block which performs the above function is available in a single MOS package (M14560). Figure 2(b) shows n decades cascaded for addition of n digit unsigned NBD numbers. Add time is typically n µs for n decades. When the carry out of the most significant decade is a logical 1, an overflow is indicated. OMPLEMENT ARITHMETI omplement arithmetic is used in NBD subtraction. That is, the complement of the subtrahend is added to the minuend. The complementing process amounts to biasing the subtrahend such that all possible sums are positive. onsider the subtraction of the NBD numbers, A and B: R = A B where R is the result. Now bias both sides of the equation by N 1 where N is the number of digits in A and B. Rearranging, R + N 1 A B + N 1 R + N 1 A + (N 1 B) The term (N 1 B), B biased by N 1, is known as the 9 s complement of B. When A > B, R + N 1 > N 1; thus R is a positive number. To obtain R, 1 is added to R + N 1, and the carry term, N, is dropped. The addition of 1 is called End Around arry (EA). When A < B, R + N 1 < N 1, no EA results and R is a negative number biased by N 1; thus R + N 1 is the 9 s complement of R. SUBTRATION OF UNSIGNED NBD NUMBERS Nine s complement arithmetic requires an element to perform the complementing function. An NBD 9 s complementer may be implemented using a 4 bit binary adder and 4 inverters, or with combinatorial logic. The Motorola M s complementer is available in a single package. It has true and inverted complement disable, which allow straight through or complement modes of operation. A zero line forces the output to 0. Figure 3 shows an NBD subtracter block using the M14560 and M Also shown are n cascaded blocks for subtraction of n digit unsigned numbers. Subtract time is n µs for n stages. Underflow (borrow) is indicated by a logical 0 on the carry output of the most significant digit. A 0 carry also indicates that the difference is a negative number in 9 s complement form. If the result is input to a 9 s complementer, as shown, and its mode controlled by the carry out of the most significant digit, the output of the complementer will be the correct negative magnitude. Note that the carry out of the most significant digit (MSD) is the input to carry in of the least significant digit (LSD). This End Around arry is required because subtraction is done in 9 s complement arithmetic. By controlling the complement and overflow logic with an add/subtract line, both addition and subtraction are performed using the basic subtracter blocks (Figure 4). MOTOROLA MOS LOGI DATA M14560B 5

6 Table 1. Sum = A + B + Binary Sums Non valid BD representation arry arry 00 + arry 00 + arry Decimal Numbers orrected Binary Sums arry arry 00 + arry 00 + arry 00 + arry 01 + arry 01 + arry 01 + arry 00 + arry 01 + arry ADDITION AND SUBTRATION OF SIGNED NBD NUMBERS Using M14560 NBD Adders and M s omplementers, a sign and magnitude adder/subtracter can be configured (Figure 5). Inputs A and B are signed positive (AS, BS = 0 ) or negative (AS, BS = 1 ). B is added to or subtracted from A under control of an Add/Sub line (subtraction = 1 ). The result, R, of the operation is positive signed, positive signed with overflow, negative signed, or negative signed with overflow. Add/subtract time is typically n µs for n decades. An exclusive OR of Add/Sub line and BS produces B, which controls the B complementers. If BS, the sign of B, is a logical 1 (B is negative) and the Add/Sub line is a 0 (add B to A), then the output of the exclusive OR (BS ) is a logical 1 and B is complemented. If BS = 1 and Add/Sub = 1, B is not complemented since subtracting a negative number is the same as adding a positive number. When Add/Sub is a 1 and BS = 0, BS is a 1 and B is complemented. The A complementer is controlled by the A sign bit, AS. When AS = 1, A is complemented. 6, ,870 THOUSANDS HUNDREDS TENS UNITS BIT BINARY ADDERS ADDER in ADDER ADDER in in ADDER DIGIT BINARY SUMS BINARY SUMS WITH ARRY FROM ONVERTERS ODE ONVERTERS ORRETED SUM 12,8 out out out out Figure 4. Unsigned NBD Addition Algorithm A B B1 B2 An Bn in 4 BIT BINARY FULL ADDER BINARY TO NBD ODE ONVERTER RESULT, R (a) M14560 Block Diagram out in out in out in out M14560 M14560 M14560 R1 R2 Rn Typical Add Time = n µs where n = Number of Decades (b) n Decade Adder OVERFLOW Figure 5. Addition of Unsigned NBD Numbers M14560B 6 MOTOROLA MOS LOGI DATA

7 The truth table and Karnaugh maps for sign, overflow, and End Around arry are shown in Figures 6 and 7. Note the use of BS from the exclusive OR of Add/Sub and BS. BS eliminates Add/Sub as a variable in the truth table. As an example of truth table generation, consider an n decade adder/ subtracter where AS = 0, BS = 1, and Add/Sub = 0. B is in 9 s complement form, N 1 B. Thus A + (N 1 B) = N 1 + (A B). There is no carry when A B, and the sign is negative (sign = 1 ). When AS and BS are opposite states and Add/Sub is a 0 (add mode), no overflow can occur (overflow = 0 ). The other output states are determined in a similar manner (see Figure 6). From the Karnaugh maps it is apparent that End Around arry is composed of the two symmetrical functions S2 and S3 of three variables with AS BS out as the center of symmetry. This is the definition of the majority logic function M3(AB). Similarly the Sign is composed of the symmetrical functions S2(3) and S3(3) but with the center of symmetry translated to ASBS out. This is equivalent to the majority function M3(ASBS out). Further evaluation of the maps and truth table reveal that Overflow can be generated by the exclusive OR function of End Around arry and arry Out. This analysis results in a minimum device count consisting of one exclusive OR package and one dual Majority Logic package to implement BS, EA, Sign and Overflow. The logic connections of these devices are shown in Figure 5. The output sign, RS, complements the result of the add/ subtract operation when RS = 1. This is required because the adder performs 9 s complement arithmetic. omplementing, when RS indicates the result is negative, restores sign and magnitude convention. Several variations of the adder/subtracter are possible. For example, 9 s complement is available at the output of the NBD adders, and output complementers are eliminated if sign and magnitude output is not required. A B A3 M14561 F1 F2 F3 F4 n A3 B1 B2 B3 AB in M14560 out n + 1 S1 S2 S3 S4 FROM out OF MOST SIGNIFIANT DEADE A3 M14561 F1 F2 F3 F4 RESULT, R (a) Basic Subtracter Block LEAST SIGNIFIANT DEADE in B1 B2 MOST An Bn SIGNIFIANT DEADE BASI SUBTRAT out in out in out BLOK R1 R1 R2 Rn 0 INDIATES UNDERFLOW Typical Subtract Time = n µs where n = Number of Decades (NEGATIVE RESULT) (b) n Decade Subtracter Figure 6. Subtraction of Unsigned NBD Numbers MOTOROLA MOS LOGI DATA M14560B 7

8 SUMMARY The concepts of binary code representations for decimal numbers, addition, and complement subtraction were discussed in detail. Using the basic Adder and omplementer MSI blocks, adder/subtracters for both signed and unsigned numbers were illustrated with examples. REFERENES 1. hu, Y.: Digital omputer Design Fundamentals, New York, McGraw Hill, McMOS Handbook, Motorola Inc., 1st Edition. 3. Beuscher, H.: Electronic Switching Theory and ircuits, New York, Van Nostrand Reinhold, Garrett, L.: MOS May Help Majority Logic Win Designer s Vote, Electronics, July 19, Richards, R.: Digital Design, New York, Wiley Interscience, B1 B2 An Bn LSD in BASI SUBTRAT BLOK out in out MSD in out R1 R2 Rn ADD/SUBTRAT ( 1 / 0 ) 1/6 M14572 OVERFLOW = 1 1/6 M14572 UNDERFLOW = 1 (NEGATIVE RESULT) Typical Add/Subtract Time = n µs where n = Number of Decades Figure 7. Adder/Subtracter for Unsigned NBD Numbers M14560B 8 MOTOROLA MOS LOGI DATA

9 A S BS ADD/SUB B1 A3 M14561 F1 F2 F3 F4 A3 M14561 F1 F2 F3 F4 A3 B1 B2 B3 B4 in M14560 out S1 S2 S3 S4 A3 M14561 F1 F2 F3 F4 R1 A 1/4 M14070 B M5 B S D E M /4 M14070 A B M 5 D E W W B2 M14561 M14561 M14560 M14561 EA R2 out 1/4 M14070 SIGN Typical Add/Subtract Time = n µ s where n = Number of Decades A n M14561 M14560 M14561 R n OVERFLOW SIGN OF R S Bn M14561 out Figure 8. Sign and Magnitude Adder/Subtracter with Overflow MOTOROLA MOS LOGI DATA M14560B 9

10 Inputs AS BS out 1 = Neg 1 = Neg 1 = arry 0 R = A Arithmatic Expression for R* (Result) (N = Number of Digits, N = Modulus A, B, R are Positive Magnitudes) 0 R = A B = A + (N 1 B) = A B + N 1 Outputs End Around arry (EA) Sign of R Overflow 1 = EA 1 = Negative 1 = Overflow No EA ( 0 ) because R is correct result. No EA ( 0 ) because 9 s complement expression for R is correct result. Since A and B are positive signed, R is positive signed ( 0 ). A B when out = 0 ; thus sign of R must be negative ( 1 ). When out = 0, there is no carry (R < N) and thus no overflow ( 0 ). When out = 1, there is a carry (R N) and thus overflow ( 1 ). 1 1 R = B A = B + (N 1 A) = B A + N 1 EA = 1 because expression for R is in error by 1. No EA ( 0 ) because 9 s complement expression for R is correct result. A > B when out = 1 ; thus sign of R must be positive ( 0 ). B A when out = 0 ; thus sign of R must be negative ( 1 ). There is never an overflow when numbers of opposite sign are added. 1 EA = 1 because expression for R is in error by 1. B > A when out = 1 ; thus sign of R must be positive ( 0 ) R = A B = (N 1 A) + (N 1 B) = (A + B) + 2 x N EA = 1 because 9 s complement expression for R is in error by 1. Since A and B are negative signed. R is negative signed ( 1 ). When out = 0, there is no arry (R < 0N) and (A + B) > N 1 indicating overflow ( 1 ). When out = 1, there is a carry (R N) and (A + B) N 1 indicating no overflow ( 0 ). * Output of Adders Figure 9. Truth Table Generation for EA, Sign, and Overflow Logic M14560B MOTOROLA MOS LOGI DATA

11 Inputs TRUTH TABLE Outputs AS BS out EA SGN OVF BS = (Add/Sub) BS AS = Sign of A ( 1 = Negative) BS = Sign of B ( 1 = Negative) out = Adder arry Out out End Around arry AS 1 1 0* 0 BS * = enter of Symmetry EA SGN EA 1 1 KARNAUGH MAPS out Sign (SGN) AS 1 1 0* 0 BS out = S2 (ASBS out) + S3 (ASBS out) = M3 (ASBS out) = S2 (ASBS out) + S3 (ASBS out) = M3 (ASBS out) out = 1 1 = 1 1 Overflow (OVF) AS 1 0 OVF 1 0 BS Figure. Mapping of EA, Sign and Overflow Logic MOTOROLA MOS LOGI DATA M14560B

12 OUTLINE DIMENSIONS L SUFFIX ERAMI DIP PAKAGE ASE 620 ISSUE V T SEATING PLANE F A E G D 16 PL 0.25 (0.0) M T N B A S K L M J 16 PL 0.25 (0.0) M T B S NOTES: 1. DIMENSIONING AND TOLERANING PER ANSI Y14.5M, ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE ERAMI BODY. INHES MILLIMETERS DIM MIN MAX MIN MAX A B D E 0 BS 1.27 BS F G 0.0 BS 2.54 BS H K L BS 7.62 BS M 0 0 N P SUFFIX PLASTI DIP PAKAGE ASE ISSUE R 16 H A 1 8 G F 9 D 16 PL B S K 0.25 (0.0) M T SEATING T PLANE A M J L M NOTES: 1. DIMENSIONING AND TOLERANING PER ANSI Y14.5M, ONTROLLING DIMENSION: INH. 3. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INLUDE MOLD FLASH. 5. ROUNDED ORNERS OPTIONAL. INHES MILLIMETERS DIM MIN MAX MIN MAX A B D F G 0.0 BS 2.54 BS H 0 BS 1.27 BS J K L M 0 0 S M14560B 12 MOTOROLA MOS LOGI DATA

13 OUTLINE DIMENSIONS D SUFFIX PLASTI SOI PAKAGE ASE 751B 05 ISSUE J T SEATING PLANE G A D 16 PL K B P 8 PL 0.25 (0.0) M B S 0.25 (0.0) M T B S A S M R X 45 J F NOTES: 1. DIMENSIONING AND TOLERANING PER ANSI Y14.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. MILLIMETERS INHES DIM MIN MAX MIN MAX A B D F G 1.27 BS 0 BS J K M P R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi SPD JLD, 6F Seibu Butsuryu enter, P.O. Box 20912; Phoenix, Arizona or Tatsumi Koto Ku, Tokyo 135, Japan MFAX: RMFAX0@ .sps.mot.com TOUHTONE ASIA/PAIFI: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong MOTOROLA MOS LOGI DATA M14560B/D 13