SEMICONDUCTOR TECHNICAL DATA
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1 SEIONDUTOR TEHNIL DT The decoder is constructed so that an 8421 D code on the four inputs provides a decimal (one of ten) decoded output, while a 3 bit binary input provides a decoded octal (one of eight) code output with D forced to a logic 0. Expanded decoding such as binary to hexadecimal (one of 16), etc., can be achieved by using other devices. The part is useful for code conversion, address decoding, memory selection control, demultiplexing, or readout decoding. Diode Protection on ll Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc apable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range Positive Logic Design Low Outputs on ll Illegal Input ombinations Similar to D4028. XIU RTINGS* (Voltages Referenced to VSS) Î ÎÎ ÎÎ Symbol Parameter Value Unit Î D Supply Voltage 0.5 to V Î Vin, VoutÎÎ ÎÎ Input or Output Voltage (D or Transient) 0.5 to V Î lin, Î lout Input or Output urrent (D or Transient), ± 10 per Pin ÎÎ ÎÎ m PD Power Dissipation, per Package 500 ÎÎ mw Tstg Storage Temperature 65 to ÎÎ Lead Temperature (8 Second Soldering) 260 TL * aximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ From 65 To 125 eramic L Packages: 12 mw/ From 100 To D INPUTS 3 IT INRY INPUTS LOK DIGR D Q1 Q5 Q6 Q7 Q8 = PIN 16 VSS = PIN OTL DEODED OUTPUTS DEIL DEODED OUTPUTS TRUTH TLE L SUFFIX ERI SE 620 ORDERING INFORTION 14XXXP 14XXXL 14XXXD P SUFFIX PLSTI SE 648 D SUFFIX SOI SE 751 Plastic eramic SOI T = 55 to 125 for all packages. D Q8 Q7 Q6 Q5 Q REV 3 1/94 OTOROL otorola, Inc OS LOGI DT 113
2 Î ELETRIL HRTERISTIS (Voltages Referenced to VSS) 55 Î Î haracteristic Î Symbol Vdc in ax in Î Typ # axî in ax Unit Î Output Voltage 0 Level ÎÎ Î Vin = or 0 Î VOL Î 0.05 Vdc Î Î Level Vin = 0 or VOH Î 9.95Î 10 Î ÎÎ 4.95 Vdc Î Î Input Voltage 0 Level Î Vdc (VO = 4.5 or 0.5 Vdc) Î (VO = 9.0 or 1.0 Vdc) Î VIL Î 3.0 (VO = 13.5 or 1.5 Vdc) Î Î 3.0 Î Î Level Î Vdc (VO = 0.5 or 4.5 Vdc) Î Î (VO = 1.0 or 9.0 Vdc) VIH Î Î (VO = 1.5 or 13.5 Vdc) Î Î Î Output Drive urrent Î mdc Î Î (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) IOH Î 0.51Î 0.88 Î (VOH = 9.5 Vdc) ÎÎ 1.7 Î (VOH = 13.5 Vdc) Î (VOL = 0.4 Vdc) Sink Î (VOL = 0.5 Vdc) Î IOL Î 1.6 ÎÎ Î (VOL = 1.5 Vdc) Î mdc Î Î Input urrent Î Iin 15 ± 0.1 ± ± 0.1Î ± 1.0 µdc Î Input apacitance Î in 7.5 Î pf Î (Vin = 0) Quiescent urrent IDD (Per Package) 10 Î Î µdc 10 Î 300 Î Î 600 Total Supply urrent** Î IT IT = (0.3 µ/khz) f + IDD µdc Î Î (Dynamic plus Quiescent, Per Package) IT = (0.6 µ/khz) f + IDD IT = (0.9 µ/khz) f + IDD (L = 50 pf on all outputs, all buffers switching) #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. ** The formulas given are for the typical characteristics only at 25. To calculate total supply current at loads other than 50 pf: IT(L) = IT(50 pf) + (L 50) Vfk where: IT is in µ (per package), L in pf, V = ( VSS) in volts, f in khz is input frequency, and k = This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or ). Unused outputs must be left open. PIN SSIGNENT Q1 Q Q D Q VSS 8 9 Q8 114 OTOROL OS LOGI DT
3 Î SWITHING HRTERISTIS* (L = 50 pf, T = 25 ) Î haracteristic Î Symbol ÎÎ in Î Typ # Î ax Unit Î Output Rise and Fall Time Î ttlh, Î ns ÎÎ Î ttlh, tthl = (1.5 ns/pf) L + 25 ns ttlh, tthl = (0.75 ns/pf) L ns ttlh, tthl = (0.55 ns/pf) L ns Î tthl Î Î 100 Î 200 ÎÎ Î Î Î Î Propagation Delay Time Î tplh, Î ns ÎÎ Î tplh, tphl = (1.7 ns/pf) L ns Î tphl Î Î 300 Î 600 ÎÎ tplh, tphl = (0.66 ns/pf) L + 97 ns 10 tplh, tphl = (0.5 ns/pf) L + 65 ns 15 Î * The formulas given are for the typical characteristics only at 25. #Data labelled Typ is not to be used for design purposes but is intended as an indication of the I s potential performance. Inputs,, and D switching in respect to a D code. 20 ns 20 ns 90% INPUT 50% 10% 1/f VSS ll outputs connected to respective L loads. f in respect to a system clock. Inputs,, and D low. INPUT 10% tplh 20 ns 20 ns 90% 50% tphl VSS 10% 90% ttlh 50% tthl VOH VOL Figure 1. Dynamic Signal Waveforms OTOROL OS LOGI DT 115
4 LOGI DIGR D Q1 Q5 Q6 Q7 Q8 PPLITIONS INFORTION Expanded decoding can be performed by using the and other OS Integrated ircuits. The circuit in Figure 2 converts any 4 bit code to a decimal or hexadecimal code. The accompanying table shows the input binary combinations, the associated output numbers that go high when selected, and the redefined output numbers needed for the proper code. For example: For the combination D = 0111 the output number 7 is redefined for the 4 bit binary, 4 bit gray, excess 3, or excess 3 gray codes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6 bit binary 1 of 64 decoder using nine circuits and two 14069U inverters. The can be used in decimal digit displays, such as, neon readouts or incandescent projection indicators as shown in Figure 4. INPUTS D D D OUTPUT NUERS Figure 2. ode onversion ircuit and Truth Table ode and Redefined Output Numbers Hexadecimal Decimal Inputs Output Numbers D it inary 4 it Gray Excess 3 Excess 3 Gray iken OTOROL OS LOGI DT
5 INPUTS E F INHIIT (NO SELETION) D *1/ U 64 OUTPUTS (SELETED OUTPUT IS HIGH) Figure 3. Six it inary 1 of 64 Decoder D Q1 Q5 Q6 Q7 Q8 9 PPROPRITE VOLTGE NEON DISPLY 0 OR PPROPRITE VOLTGE INNDESENT DISPLY Figure 4. Decimal Digit Display pplication OTOROL OS LOGI DT 117
6 OUTLINE DIENSIONS L SUFFIX ERI DIP PKGE SE ISSUE V T SETING PLNE F E G D 16 PL 0.25 (0.010) T N S K L J 16 PL 0.25 (0.010) T S NOTES: 1. DIENSIONING ND TOLERNING PER NSI Y14.5, ONTROLLING DIENSION: INH. 3. DIENSION L TO ENTER OF LED WHEN FORED PRLLEL. 4. DIENSION F Y NRROW TO 0.76 (0.030) WHERE THE LED ENTERS THE ERI ODY. INHES ILLIETERS DI IN X IN X D E S 1.27 S F G S 2.54 S H K L S 7.62 S N P SUFFIX PLSTI DIP PKGE SE ISSUE R 16 H 1 8 G F 9 D 16 PL S K 0.25 (0.010) T SETING T PLNE J L NOTES: 1. DIENSIONING ND TOLERNING PER NSI Y14.5, ONTROLLING DIENSION: INH. 3. DIENSION L TO ENTER OF LEDS WHEN FORED PRLLEL. 4. DIENSION DOES NOT INLUDE OLD FLSH. 5. ROUNDED ORNERS OPTIONL. INHES ILLIETERS DI IN X IN X D F G S 2.54 S H S 1.27 S J K L S OTOROL OS LOGI DT
7 OUTLINE DIENSIONS D SUFFIX PLSTI SOI PKGE SE ISSUE J T SETING PLNE G D 16 PL K P 8 PL 0.25 (0.010) S 0.25 (0.010) T S S R X 45 J F NOTES: 1. DIENSIONING ND TOLERNING PER NSI Y14.5, ONTROLLING DIENSION: ILLIETER. 3. DIENSIONS ND DO NOT INLUDE OLD PROTRUSION. 4. XIU OLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIENSION D DOES NOT INLUDE DR PROTRUSION. LLOWLE DR PROTRUSION SHLL E (0.005) TOTL IN EXESS OF THE D DIENSION T XIU TERIL ONDITION. ILLIETERS INHES DI IN X IN X D F G 1.27 S S J K P R otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: US/EUROPE/Locations Not Listed: otorola Literature Distribution; JPN: Nippon otorola Ltd.; Tatsumi SPD JLD, 6F Seibu utsuryu enter, P.O. ox 20912; Phoenix, rizona or Tatsumi Koto Ku, Tokyo 135, Japan FX: RFX0@ .sps.mot.com TOUHTONE SI/PIFI: otorola Semiconductors H.K. Ltd.; 8 Tai Ping Industrial Park, INTERNET: NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong OTOROL OS LOGI DT /D 119
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MC404B, MC4050B Hex Buffer The MC404B Hex Inverter/Buffer and MC4050B Noninverting Hex Buffer are constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. These
MC14584B. Hex Schmitt Trigger
MC4584B Hex Schmitt Trigger The MC4584B Hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
The LSTTL/MSI SN74LS18 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
LOW POWER SCHOTTKY. MODE SELECT TRUTH TABLE ORDERING INFORMATION GUARANTEED OPERATING RANGES OPERATING MODE
The SN74S74A dual edge-triggered flip-flop utilizes Schottky TT circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary and outputs.
SN74LS166MEL. 8 Bit Shift Registers LOW POWER SCHOTTKY
8 Bit Shift Registers The SN74S166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74S standard load. By utilizing input clamping diodes, switching
MC74VHC132. Quad 2 Input NAND Schmitt Trigger
MC74HC32 Quad 2 Input NAND Schmitt Trigger The MC74HC32 is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
NLSV2T Bit Dual-Supply Inverting Level Translator
2-Bit Dual-Supply Inverting Level Translator The NLSV2T240 is a 2 bit configurable dual supply voltage level translator. The input A n and output B n ports are designed to track two different power supply
74VHC08 Quad 2-Input AND Gate
74VHC08 Quad 2-Input AND Gate Features High Speed: t PD = 4.3ns (Typ.) at T A = 25 C High noise immunity: V NIH = V NIL = 28% V CC (Min.) Power down protection is provided on all inputs Low power dissipation:
SN74LS175MEL. Quad D Flip Flop LOW POWER SCHOTTKY
uad Flip Flop The LSTTL/MSI SN74LS75 is a high speed uad Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the inputs is stored
MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS
Quad 2 Input NAND Gate with Schmitt Trigger Inputs High Performance Silicon Gate CMOS The is identical in pinout to the LS32. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
MARKING DIAGRAMS MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.) ORDERING INFORMATION PDIP 24 P SUFFIX CASE 709
The M14067 multiplexer/demultiplexer is a digitally controlled analog switch featuring low ON resistance and very low leakage current. This device can be used in either digital or analog applications.
NL17SHT08. 2-Input AND Gate / CMOS Logic Level Shifter
N7ST08 -Input AND Gate / CMOS ogic evel Shifter The N7ST08 is an advanced high speed CMOS input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
NB3N2304NZ. 3.3V 1:4 Clock Fanout Buffer
3.3V 1:4 lock Fanout Buffer Description The NB3N2304NZ is a low skew 1 to 4 clock fanout buffer, designed for high speed clock distribution such as in PI X applications. The NB3N2304NZ guarantees low output
MMBZ5221BLT1 Series. Zener Voltage Regulators. 225 mw SOT 23 Surface Mount
MMBZ5BLT Series Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed to provide voltage
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION
These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS22 has an internal
74HCT32. Quad 2 Input OR Gate with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
Quad 2 Input OR Gate with STT Compatible Inputs igh Performance Silicon Gate CMOS The 74CT32 is identical in pinout to the S32. The device has TT compatible inputs. Features Output Drive Capability: 0
74AC00, 74ACT00 Quad 2-Input NAND Gate
74AC00, 74ACT00 Quad 2-Input NAND Gate Features I CC reduced by 50% Outputs source/sink 24mA ACT00 has TTL-compatible inputs Ordering Information Order Number Package Number General Description The AC00/ACT00
MC14518B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) ORDERING INFORMATION
The MC14518B dual BCD counter and the MC14520B dual binary counter are cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each coists of two identical,
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1. JFET Switching Transistors. N Channel. Pb Free Packages are Available.
LT1, LT1, LT1 JFET Switching Transistors NChannel Features PbFree Packages are Available MAXIMUM RATINGS Rating Symbol Value Unit DrainSource Voltage V DS Vdc DrainGate Voltage V DG Vdc GateSource Voltage
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MARKING DIAGRAMS ORDERING INFORMATION VHC139 AWLYYWW SOIC 16 D SUFFIX CASE 751B VHC 139 AWLYWW TSSOP 16 DT SUFFIX CASE 948F
The MC74HC139 is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while
NL17SZ08. Single 2-Input AND Gate
N7SZ08 Single 2-Input AND Gate The N7SZ08 is a single 2 input AND Gate in two tiny footprint packages. The device performs much as CX multi gate products in speed and drive. They should be used wherever
MUR3020PTG SUR83020PTG MUR3040PTG MUR3060PTG SUR83060PTG. SWITCHMODE Power Rectifiers ULTRAFAST RECTIFIERS 30 AMPERES, VOLTS
MUR00PTG, SUR00PTG, MUR00PTG, MUR00PTG, SUR00PTG SWITCHMODE Power Rectifiers These state of the art devices are designed for use in switching power supplies, inverters and as free wheeling diodes. Features
MMBZ5221BLT1 Series. Zener Voltage Regulators. 225 mw SOT 23 Surface Mount
MMBZ5BLT Series Preferred Device Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed
NGTG50N60FLWG IGBT. 50 A, 600 V V CEsat = 1.65 V
NGTGN6FLWG IGBT This Insulated Gate Bipolar Transistor (IGBT) features a robust and cost effective Trench construction, and provides superior performance in demanding switching applications, offering both
FFSP0665A/D. Silicon Carbide Schottky Diode 650 V, 6 A Features. FFSP0665A Silicon Carbide Schottky Diode. Description.
FFSP66A Silicon Carbide Schottky Diode 6 V, 6 A Features Max Junction Temperature 7 o C Avalanche Rated 36 mj High Surge Current Capacity Positive Temperature Coefficient Ease of Paralleling No Reverse
NL17SH02. Single 2-Input NOR Gate
N7S0 Single -Input NOR Gate The N7S0 MiniGate is an advanced high speed CMOS input NOR gate in ultra small footprint. The N7S0 input structures provide protection when voltages up to 7.0 are applied, regardless
MC14099B. 8-Bit Addressable Latches
-Bit Addressable Latches The MC99B is an bit addressable latch. Data is entered in serial form when the appropriate latch is addressed (via address pi A, A, A) and write disable is in the low state. For
MC14511B. MARKING DIAGRAMS 16. MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2) ORDERING INFORMATION
The MC14511B BCD to seven segment latch/decoder/driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides
High Performance Silicon Gate CMOS
SEONDUTOR TEHNAL HighPerformance Siliconate OS The H is identical in pinout to the LS. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs.
NTJD4105C. Small Signal MOSFET. 20 V / 8.0 V, Complementary, A / A, SC 88
NTJD5C Small Signal MOSFET V / 8. V, Complementary, +.63 A /.775 A, SC 88 Features Complementary N and P Channel Device Leading 8. V Trench for Low R DS(on) Performance ESD Protected Gate ESD Rating: Class
NL17SV16. Ultra-Low Voltage Buffer
N7S6 Ultra-ow oltage Buffer The N7S6X5T is an ultra high performance single Buffer fabricated in sub micron silicon gate 0.35 m technology with excellent performance down to 0.9. This device is ideal for