SEMICONDUCTOR TECHNICAL DATA

Transcription

1 SEICONDUCTOR TECHNICL DT The C7 is a static clocked serial shift register whose length may be programmed to be any number of bits between and. The number of bits selected is equal to the sum of the subscripts of the enabled Length Control inputs (L, L, L, L8, L, and L) plus one. Serial data may be selected from the or data inputs with the / select input. This feature is useful for recirculation purposes. Clock Enable (CE) input is provided to allow gating of the clock or negative edge clocking capability. The device can be effectively used for variable digital delay lines or simply to implement odd length shift registers. it Programmable Length and Serial uffered Outputs synchronous aster Reset ll Inputs uffered No Limit On Clock Rise and Fall Times Supply Voltage Range =. to 8 Capable of Driving Two Low power TTL Loads or one Low power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ XIU RTINGS* (Voltages Referenced to ) Symbol Parameter Value Unit DC Supply Voltage. to + 8. V Vin, Vout Input or Output Voltage (DC or Traient). to +. V Iin, Iout Input or Output Current (DC or Traient), per Pin ± m PD Power Dissipation, per Package mw Tstg Storage Temperature to + C TL Lead Temperature (8 Second Soldering) C * aximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7. mw/ C From C To C Ceramic L Packages: mw/ C From C To C LENGTH SELECT TRUTH TLE L L L8 L L L Register Length it its its its its its its its its its its its NOTE: Length equals the sum of the binary length control subscripts plus one. LOCK DIGR L SUFFIX CERIC CSE ORDERING INFORTION CXXXCP CXXXCL CXXXDW P SUFFIX PLSTIC CSE 8 DW SUFFIX SOIC CSE 7G Plastic Ceramic SOIC T = to C for all packages. 7 TRUTH TLE Inputs Output Rst / Clock CE X X X is the output of the first selected shift register stage. X = Don t Care CE / SELECT L L L L8 L L = PIN = PIN 8 REV / OTOROL otorola, Inc. COS LOGIC DT C7

2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICL CHRCTERISTICS (Voltages Referenced to ) Characteristic Output Voltage Vin = or Vin = or Level Level Input Voltage Level (VO =. or. ) (VO =. or. ) (VO =. or. ) (VO =. or. ) (VO =. or. ) (VO =. or. ) Output Drive Current (VOH =. ) (VOH =. ) (VOH =. ) (VOH =. ) (VOL =. ) (VOL =. ) (VOL =. ) Level Source Sink Symbol VOL. VOH. VIL VIH IOH C C C in ax in Typ # ax in ax Unit.... IOL Input Current Iin ±. ±. ±. ±. µdc Input Capacitance (Vin = ) Cin. 7. pf mdc uiescent Current (Per Package) Total Supply Current** (Dynamic plus uiescent, Per Package) (CL = pf on all outputs, all buffers switching) IDD. IT IT = (.7 µ/khz) f + IDD IT = (. µ/khz) f + IDD IT = (. µ/khz) f + IDD #Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. ** The formulas given are for the typical characteristics only at C. To calculate total supply current at loads other than pf: IT(CL) = IT( pf) + (CL ) Vfk where: IT is in µ (per package), CL in pf, V = ( ) in volts, f in khz is input frequency, and k =.. µdc µdc This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be cotrained to the range (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. C7 OTOROL COS LOGIC DT

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHRCTERISTICS* (CL = pf, T = C) Rise and Fall Time, or Output ttlh, tthl = (. /pf) CL + ttlh, tthl = (.7 /pf) CL +. ttlh, tthl = (. /pf) CL +. Propagation Delay, Clock or CE to or tplh, tphl = (.7 /pf) CL + tplh, tphl = (. /pf) CL + 7 tplh, tphl = (. /pf) CL + Propagation Delay, Reset to or tplh, tphl = (.7 /pf) CL + tplh, tphl = (. /pf) CL + 7 tplh, tphl = (. /pf) CL + 7 Characteristic Symbol in Typ # ax Unit ttlh, tthl tplh, tphl tplh, tphl Pulse Width, Clock twh(cl) Pulse Width, Reset twh(rst) Clock Frequency (% Duty Cycle) fcl Setup Time, or to Clock or CE Worst case condition: L = L = L = L8 = L = L = (Register Length = ) est case condition: L =, L through L = Don t Care (ny register length from to ) Hold Time, Clock or CE to or est case condition: L = L = L = L8 = L = L = (Register Length = ) Worst case condition: L =, L through L = Don t Care (ny register length from to ) Rise and Fall Time, Clock Rise and Fall Time, Reset or CE Removal Time, Reset to Clock or CE trem tsu th tr, tf No Limit * The formulas given are for the typical characteristics only at C. #Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. INPUT % twh(cl) bit length: CE = / = L = L = L = L8 = L = L = /fcl tsu % tplh tr, tf TIING DIGR th ttlh % % % tthl tphl % 8 7 trem PWR tphl VOH VOL Hz µs OTOROL COS LOGIC DT C7

4 LOGIC DIGR PIN SSIGNENT L 7 L L CE IT L IT L IT / SELECT L IT L 8 IT L8 IT IT L = PIN = PIN 8 L8 L CE L 7 8 / SEL C7 OTOROL COS LOGIC DT

5 OUTLINE DIENSIONS L SUFFIX CERIC DIP PCKGE CSE ISSUE V T SETING PLNE F 8 E G D PL. (.) T N S C K L J PL. (.) T S NOTES:. DIENSIONING ND TOLERNCING PER NSI Y., 8.. CONTROLLING DIENSION: INCH.. DIENSION L TO CENTER OF LED WHEN FORED PRLLEL.. DIENSION F Y NRROW TO.7 (.) WHERE THE LED ENTERS THE CERIC ODY. INCHES ILLIETERS DI IN X IN X C..8 D.... E. SC.7 SC F.... G. SC. SC H K L. SC 7. SC N.... P SUFFIX PLSTIC DIP PCKGE CSE 8 8 ISSUE R H 8 G F D PL S C K. (.) T SETING T PLNE J L NOTES:. DIENSIONING ND TOLERNCING PER NSI Y., 8.. CONTROLLING DIENSION: INCH.. DIENSION L TO CENTER OF LEDS WHEN FORED PRLLEL.. DIENSION DOES NOT INCLUDE OLD FLSH.. ROUNDED CORNERS OPTIONL. INCHES ILLIETERS DI IN X IN X C..7.. D.... F G. SC. SC H. SC.7 SC J K...8. L S.... OTOROL COS LOGIC DT C7

6 OUTLINE DIENSIONS DW SUFFIX PLSTIC SOIC PCKGE CSE 7G ISSUE X D X G. (.) T S S 8 K C 8X P T SETING PLNE. (.) J F R X NOTES:. DIENSIONING ND TOLERNCING PER NSI Y., 8.. CONTROLLING DIENSION: ILLIETER.. DIENSIONS ND DO NOT INCLUDE OLD PROTRUSION.. XIU OLD PROTRUSION. (.) PER SIDE.. DIENSION D DOES NOT INCLUDE DR PROTRUSION. LLOWLE DR PROTRUSION SHLL E. (.) TOTL IN EXCESS OF D DIENSION T XIU TERIL CONDITION. ILLIETERS INCHES DI IN X IN X C.... D.... F.... G.7 SC. SC J.... K P.... R..7.. otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: US/EUROPE/Locatio Not Listed: otorola Literature Distribution; JPN: Nippon otorola Ltd.; Tatsumi SPD JLDC, F Seibu utsuryu Center, P.O. ox ; Phoenix, rizona or Tatsumi Koto Ku, Tokyo, Japan. 8 8 FX: RFX@ .sps.mot.com TOUCHTONE SI/PCIFIC: otorola Semiconductors H.K. Ltd.; 8 Tai Ping Industrial Park, INTERNET: NET.com Ting Kok Road, Tai Po, N.T., Hong Kong. 8 8 C7 OTOROL COS LOGIC C7/D DT