MC74HC04A. Hex Inverter. High Performance Silicon Gate CMOS
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1 Hex Inverter High Performance Silicon Gate COS The is identical in pinout to the S04 and the C069. The device inputs are compatible with Standard COS outputs; with pullup resistors, they are compatible with STT outputs. The device consists of six three stage inverters. Features Output Drive Capability: 0 STT oads Outputs Directly Interface to COS, NOS and TT Operating oltage Range: to ow Input Current: High Noise Immunity Characteristic of COS Devices In Compliance With the JEDEC Standard No. 7 Requirements Chip Complexity: 36 FETs or 9 Equivalent Gates Pb Free Packages are vailable* OGIC DIGR PDIP N SUFFIX CSE 646 SOIC D SUFFIX CSE 75 RKING DIGRS N WYYWW HC04 WYWW Y Y2 Y3 TSSOP DT SUFFIX CSE 948G HC 04 YW Y4 Y = = ssembly ocation W or = Wafer ot YY or Y = Year WW or W = Work Week 5 0 Y Y6 FUNCTION TBE Inputs Outputs Pinout: ead Packages (Top iew) CC 6 Y6 5 Y5 4 Y H Y H ORDERING INFORTION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet Y 2 Y2 3 Y3 GND *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and ounting Techniques Reference anual, SODERR/D. Semiconductor Components Industries, C, 2005 ay, 2005 Rev. 0 Publication Order Number: /D
2 XIU RTINGS Symbol Parameter alue ÎÎÎ Unit CC DC Supply oltage (Referenced to GND) 0.5 to ÎÎÎ in DC Input oltage (Referenced to GND) 0.5 to CC ÎÎÎ out DC Output oltage (Referenced to GND) 0.5 to CC + 0.5ÎÎÎ I in DC Input Current, per Pin ± 20 m I out DC Output Current, per Pin ± 25 m ICC DC Supply Current, CC and GND Pins ± 50 Î m P Î D Power Dissipation in Still ir, Plastic DIP 750 mw SOIC Package 500 ÎÎÎ TSSOP Package 450 T stg Storage Temperature 65 to + 50 C T Î ead Temperature, mm from Case for 0 Seconds Î C Plastic DIP, SOIC or TSSOP Package aximum ratings are those values beyond which device damage can occur. aximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. Derating Plastic DIP: 0 mw/ C from 65 to 25 C SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed COS Data Book (D29/D). RECOENDED OPERTING CONDITIONS Symbol Parameter in ÎÎÎ ax Unit CC DC Supply oltage (Referenced to GND) ÎÎÎ in, out DC Input oltage, Output oltage (Referenced to GND) 0 CC ÎÎÎ T Operating Temperature, ll Package Types ÎÎÎ ÎÎÎ C t r, t f Input Rise and Fall Time CC = ÎÎ (Figure ) CC = ÎÎÎ ÎÎÎ ÎÎÎ ns CC = ORDERING INFORTION Device Order Number Package Shipping N PDIP 2000 / Rail NG PDIP 2000 / Rail D SOIC 55 / Rail DG SOIC 55 / Rail DR2 SOIC 2500 / Tape & Reel DR2G SOIC 2500 / Tape & Reel DTR2 TSSOP * 2500 / Tape & Reel F SOEIJ 50 / Rail FG SOEIJ 50 / Rail FE SOEIJ 2000 / Tape & Reel FEG SOEIJ 2000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2
3 DC CHRCTERISTICS (oltages Referenced to GND) Symbol Parameter Condition IH I OH O I in I CC inimum High evel Input oltage aximum ow evel Input oltage inimum High evel Output oltage aximum ow evel Output oltage aximum Input eakage Current aximum Quiescent Supply Current (per Package) out = 0. or CC 0. I out 20 out = 0. or CC 0. I out 20 in = IH or I I out 20 in = IH or I in = IH or I I out 20 in = IH or I I out 2.4m I out 4.0m I out 5.2m I out 2.4m I out 4.0m I out 5.2m Guaranteed imit CC 55 to 25 C 85 C 25 C Unit in = CC or GND ± 0. ±.0 ±.0 in = CC or GND I out = NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed COS Data Book (D29/D). C CHRCTERISTICS (C = 50pF, Input t r = t f = 6ns) Symbol t PH, t PH t TH, t TH Parameter aximum Propagation Delay, Input or B to Output Y (Figures and 2) aximum Output Transition Time, ny Output (Figures and 2) Guaranteed imit CC 55 to 25 C 85 C 25 C Unit C in aximum Input Capacitance pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed COS Data Book (D29/D) C, CC = 5.0 C PD Power Dissipation Capacitance (Per Inverter)* 20 pf * Used to determine the no load dynamic power consumption: P D = C PD 2 CC f + I CC CC. For load considerations, see Chapter 2 of the ON Semiconductor High Speed COS Data Book (D29/D) ns ns 3
4 t f t r INPUT 90% 50% 0% CC GND t PH t PH OUTPUT Y 90% 50% 0% t TH t TH Figure. Switching Waveforms TEST POINT DEICE UNDER TEST OUTPUT C * *Includes all probe and jig capacitance Figure 2. Test Circuit Y Figure 3. Expanded ogic Diagram (/6 of the Device Shown) 4
5 PCKGE DIENSIONS PDIP N SUFFIX CSE ISSUE N T N SETING PNE 8 B 7 F C K H G D P 0.3 (0.005) J NOTES:. DIENSIONING ND TOERNCING PER NSI Y.5, CONTROING DIENSION: INCH. 3. DIENSION TO CENTER OF EDS WHEN FORED PRE. 4. DIENSION B DOES NOT INCUDE OD FSH. 5. ROUNDED CORNERS OPTION. INCHES IIETERS DI IN X IN X B C D F G 0.00 BSC 2.54 BSC H J K N SOIC D SUFFIX CSE ISSUE G T SETING PNE G 8 D P 7 B K P 7 P C 0.25 (0.00) T B S S 0.25 (0.00) B R X 45 J F NOTES:. DIENSIONING ND TOERNCING PER NSI Y.5, CONTROING DIENSION: IIETER. 3. DIENSIONS ND B DO NOT INCUDE OD PROTRUSION. 4. XIU OD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIENSION D DOES NOT INCUDE DBR PROTRUSION. OWBE DBR PROTRUSION SH BE 0.27 (0.005) TOT IN EXCESS OF THE D DIENSION T XIU TERI CONDITION. IIETERS INCHES DI IN X IN X B C D F G.27 BSC BSC J K P R
6 PCKGE DIENSIONS TSSOP DT SUFFIX CSE 948G 0 ISSUE 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SETING PNE U U S 2X /2 PIN IDENT. S D C X K REF 0.0 (0.004) T U S S N (0.00) B U 7 G H N J J F DETI E K K ÇÇÇ ÉÉÉ ÇÇÇ SECTION N N DETI E W NOTES:. DIENSIONING ND TOERNCING PER NSI Y.5, CONTROING DIENSION: IIETER. 3. DIENSION DOES NOT INCUDE OD FSH, PROTRUSIONS OR GTE BURRS. OD FSH OR GTE BURRS SH NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIENSION B DOES NOT INCUDE INTERED FSH OR PROTRUSION. INTERED FSH OR PROTRUSION SH NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIENSION K DOES NOT INCUDE DBR PROTRUSION. OWBE DBR PROTRUSION SH BE 0.08 (0.003) TOT IN EXCESS OF THE K DIENSION T XIU TERI CONDITION. 6. TERIN NUBERS RE SHOWN FOR REFERENCE ONY. 7. DIENSION ND B RE TO BE DETERINED T DTU PNE W. IIETERS INCHES DI IN X IN X B C D F G 0.65 BSC BSC H J J K K BSC BSC ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICTION ORDERING INFORTION ITERTURE FUFIENT: iterature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, rizona US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, eguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative. /D
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MC404B, MC4050B Hex Buffer The MC404B Hex Inverter/Buffer and MC4050B Noninverting Hex Buffer are constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. These
MC14584B. Hex Schmitt Trigger
MC4584B Hex Schmitt Trigger The MC4584B Hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
MC74HC157A. Quad 2-Input Data Selectors/Multiplexers. High Performance Silicon Gate CMOS
Quad -Input Data Selectors/Multiplexers High Performance Silicon Gate CMOS The MCHCA is identical in pinout to the S. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
MC10H606, MC100H606. Registered Hex TTL to PECL Translator
Registered ex TT to PEC Translator Description The MC10/100606 is a 6 bit, registered, single supply TT to PEC translator. The device features differential PEC outputs as well as a choice between either
High Performance Silicon Gate CMOS
High Performance Silicon Gate CMOS The MC74HCT14A may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT14A is identical in pinout to the LS14. The HCT14A
MBRB2545CTG, SBRB2545CTG. SWITCHMODE Power Rectifier. D 2 PAK Surface Mount Power Package SCHOTTKY BARRIER RECTIFIER 30 AMPERES, 45 VOLTS
BRB255CTG, SBRB255CTG SWITCHODE Power Rectifier D 2 PK Surface ount Power Package The D 2 PK Power Rectifier is a stateoftheart device that employs the Schottky Barrier principle with a platinum barrier
NL17SZ17. Single Non-Inverting Buffer with Schmitt Trigger
NL7SZ7 Single Non-Inverting Buffer with Schmitt Trigger The NL7SZ7 is a single Non inverting Schmitt Trigger Buffer in two tiny footprint packages. The device performs much as LCX multi gate products in
74HC245. Octal 3 State Noninverting Bus Transceiver. High Performance Silicon Gate CMOS
Octal 3 State Noninverting Bus Traceiver High Performance Silicon Gate CMOS The 74HC245 is identical in pinout to the LS245. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
NL17SZ02. 2-Input NOR Gate
N7SZ0 -Input NOR Gate The N7SZ0 is a single input NOR Gate in three tiny footprint packages. The device performs much as CX multi gate products in speed and drive. Features Tiny SOT, SOT and SOT 9 Packages.
74AC00, 74ACT00 Quad 2-Input NAND Gate
74AC00, 74ACT00 Quad 2-Input NAND Gate Features I CC reduced by 50% Outputs source/sink 24mA ACT00 has TTL-compatible inputs Ordering Information Order Number Package Number General Description The AC00/ACT00
SN74LS74AMEL LOW POWER SCHOTTKY
The SN74S74A dual edge-triggered flip-flop utilizes Schottky TT circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.
MC74VHC1G00. Single 2-Input NAND Gate
MC74CG00 Single 2-Input NND Gate The MC74CG00 is an advanced high speed CMOS 2 input NND gate fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including
SN74LS157MEL LOW POWER SCHOTTKY
The LSTTL/MSI SN74LS157 is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected
MC74AC259, MC74ACT Bit Addressable Latch
8 Bit Addressable Latch The MC74AC259/74ACT259 is a high speed 8 bit addressable latch designed for general purpose storage applicatio in digital systems. It is a multifunctional device capable of storing
SN74LS166MEL. 8 Bit Shift Registers LOW POWER SCHOTTKY
8 Bit Shift Registers The SN74S166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74S standard load. By utilizing input clamping diodes, switching
MC Bit Magnitude Comparator
Bit Magnitude Comparator The MC0 is a high speed expandable bit comparator for comparing the magnitude of two binary words. Two outputs are provided: and. A = B can be obtained by NORing the two outputs
1PMT5920B Series. 3.2 Watt Plastic Surface Mount POWERMITE Package PLASTIC SURFACE MOUNT 3.2 WATT ZENER DIODES VOLTS
PMT90B Series. Watt Plastic Surface Mount POWERMITE Package This complete new line of. Watt Zener Diodes are offered in highly efficient micro miniature, space saving surface mount with its unique heat
MC74VHCT00A. Quad 2-Input NAND Gate
MC74CT00A Quad 2-Input NAND Gate The MC74CT00A is an advanced high speed CMOS 2 input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation while maintaining CMOS low
MC74VHC245. Octal Bus Buffer/Line Driver
MC74HC245 Octal Bus Buffer/Line Driver The MC74HC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent
MC74HCT259A. 8-Bit Addressable Latch 1-of-8 Decoder with LSTTL Inputs. High Performance Silicon Gate CMOS
MC74CT259A 8-Bit Addressable atch -of-8 ecoder with STT Inputs igh Performance Silicon Gate CMOS The MC74CT259A is identical in pinout to the S259. The device inputs are compatible with standard CMOS and
MC74AC00, MC74ACT00. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS
Quad 2Input NAND Gate ighperformance SiliconGate CMOS Features Output Drive Capability: 24 ma Operating oltage Range: 2 to 6 AC00; to ACT00 ow Input Current:.0 A igh Noise Immunity Characteristic of CMOS
High Performance Silicon Gate CMOS
SEIONDUTOR TENI DT igh Performance Silicon ate OS The 5/7T00 may be used as a level converter for interfacing TT or NOS outputs to high speed OS inputs. The T00 is identical in pinout to the S00. Output
NTJD4105C. Small Signal MOSFET. 20 V / 8.0 V, Complementary, A / A, SC 88
NTJD5C Small Signal MOSFET V / 8. V, Complementary, +.63 A /.775 A, SC 88 Features Complementary N and P Channel Device Leading 8. V Trench for Low R DS(on) Performance ESD Protected Gate ESD Rating: Class
MC74VHC1G08. Single 2-Input AND Gate
Single 2-Input AND Gate The is an advanced high speed CMOS 2 input AND gate fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output
MMBZ5221BLT1 Series. Zener Voltage Regulators. 225 mw SOT 23 Surface Mount
MMBZ5BLT Series Preferred Device Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed
The MC10107 is a triple 2 input exclusive OR/NOR gate. P D = 40 mw typ/gate (No Load) t pd = 2.8 ns typ t r, t f = 2.
The MC10107 is a triple input exclusive OR/NOR gate. P D = 0 mw typ/gate (No Load) t pd =. ns typ t r, t f =. ns typ (0% 0%) LOGIC DIAGRAM MARKING DIAGRAMS CDIP 16 L SUFFIX CASE 60 16 1 MC10107L AWLYYWW
LOW POWER SCHOTTKY. ESD > 3500 Volts. GUARANTEED OPERATING RANGES ORDERING INFORMATION V CC 8 7 GND
ESD > 3500 Volts V CC 8 4 3 2 0 9 LOW POWER SCHOTTKY 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage 4.75 5.0 5.25 V T A Operating Ambient Temperature
MARKING DIAGRAMS ORDERING INFORMATION VHC139 AWLYYWW SOIC 16 D SUFFIX CASE 751B VHC 139 AWLYWW TSSOP 16 DT SUFFIX CASE 948F
The MC74HC139 is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while