SEMICONDUCTOR TECHNICAL DATA

Transcription

1 EIONDUTOR TEHNIL DT The is a quad 2 input NOR gate. The provides one gate with OR/NOR outputs. PD = 25 mw typ/gate (No Load) tpd = ns typ tr, tf = ns typ (20% 0%) L UIX ERI PE E LOI DIR P UIX PLTI PE E N UIX PL E V1 DIP PIN INENT 1 16 V2 OUT 2 DOUT V1 = PIN 1 V2 = PIN 16 VEE = PIN OUT IN OUT DIN IN 5 DIN IN 6 11 IN IN 7 10 IN VEE DOUT Pin assignment is for Dual in Line Package. or PL pin assignment, see the Pin onversion Tables on page 6 11 of the otorola ook (DL2/D). 3/3 otorola, Inc REV 5

2 ELETRIL HRTERITI haracteristic ymbol Test Limits Pin Under Test in ax in Typ ax in ax Unit Power upply Drain urrent IE mdc Input urrent IinH µdc Output Voltage Logic 1 VOH Output Voltage Logic 0 VOL Threshold Voltage Logic 1 VOH Threshold Voltage Logic 0 VOL IinL µdc witching Times (50Ω Load) ns Propagation Delay t+ t + t++ t Rise Time (20 to 0%) t+ t+ all Time (20 to 0%) t t DL2 Rev OTOROL

3 ELETRIL HRTERITI (continued) TET VOLTE VLUE (Volts) Test Temperature VIHmax VILmin VIHmin VILmax VEE ymbol Pin TET VOLTE PPLIED TO PIN LITED ELOW Under Test VIHmax VILmin VIHmin VILmax VEE Power upply Drain urrent IE Input urrent IinH Output Voltage Logic 1 VOH Output Voltage Logic 0 VOL Threshold Voltage Logic 1 VOH Threshold Voltage Logic 0 VOL (V) nd IinL witching Times (50Ω Load) Pulse In Pulse Out 3.2 V + V Propagation Delay t+ t + t++ t Rise Time (20 to 0%) t+ t+ all Time (20 to 0%) t t Each EL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. OTOROL 3 DL2 Rev 6

4 OUTLINE DIENION N UIX PLTI PL PE E IUE (0.10) T L N N Y R U (0.10) T L N D L Z W 20 1 D X (0.250) T L N V VIEW D D (0.10) T L N Z R (0.10) T L N H (0.10) T L N E (0.250) T L N (0.100) J T ETIN PLNE VIEW VIEW (0.10) T L N NOTE: 1. DTU L,, ND N DETERINED WHERE TOP O LED HOULDER EXIT PLTI ODY T OLD PRTIN LINE. 2. DIENION 1, TRUE POITION TO E EURED T DTU T, ETIN PLNE. 3. DIENION R ND U DO NOT INLUDE OLD LH. LLOWLE OLD LH I (0.250) PER IDE. 4. DIENIONIN ND TOLERNIN PER NI Y14.5,. 5. ONTROLLIN DIENION: INH. 6. THE PE TOP Y E LLER THN THE PE OTTO Y UP TO 0.0 (0.300). DIENION R ND U RE DETERINED T THE OUTEROT EXTREE O THE PLTI ODY EXLUIVE O OLD LH, TIE R URR, TE URR ND INTERLED LH, UT INLUDIN NY ITH ETWEEN THE TOP ND OTTO O THE PLTI ODY. 7. DIENION H DOE NOT INLUDE DR PROTRUION OR INTRUION. THE DR PROTRUION() HLL NOT UE THE H DIENION TO E RETER THN (0.40). THE DR INTRUION() HLL NOT UE THE H DIENION TO E LLER THN (0.635). INHE ILLIETER E H J R U V W X Y Z DL2 Rev 6 3 OTOROL

5 OUTLINE DIENION T ETIN PLNE 16 1 E D 16 PL N L UIX ERI DIP PE E IUE V L J 16 PL NOTE: 1. DIENIONIN ND TOLERNIN PER NI Y14.5,. 2. ONTROLLIN DIENION: INH. 3. DIENION L TO ENTER O LED WHEN ORED PRLLEL. 4. DIENION Y NRROW TO 0.76 (0.030) WHERE THE LED ENTER THE ERI ODY. INHE ILLIETER D E H L N H 1 D 16 PL ETIN T PLNE P UIX PLTI DIP PE E 64 0 IUE R J L NOTE: 1. DIENIONIN ND TOLERNIN PER NI Y14.5,. 2. ONTROLLIN DIENION: INH. 3. DIENION L TO ENTER O LED WHEN ORED PRLLEL. 4. DIENION DOE NOT INLUDE OLD LH. 5. ROUNDED ORNER OPTIONL. INHE ILLIETER D H J L otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. hould uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: U/EUROPE/Locations Not Listed: otorola Literature Distribution; JPN: Nippon otorola Ltd.; Tatsumi PD JLD, 6 eibu utsuryu enter, P.O. ox 5405, Denver, olorado Tatsumi oto u, Tokyo 5, Japan fax : RX0@ .sps.mot.com TOUHTONE I/PII: otorola emiconductors H.. Ltd.; Tai Ping Industrial Park, INTERNET: NET.com 51 Ting ok Road, Tai Po, N.T., Hong ong OTOROL /D DL2 Rev 6