High Performance Silicon Gate CMOS
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1 SEIODUTOR TEHI DT High Performance Silicon ate OS The 54/74H02 is identical in pinout to the S02. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with STT outputs. Output Drive apability: 0 STT oads Outputs Directly Interface to OS, OS, and TT Operating Range: 2.0 to 6.0 V ow Input urrent:.0 µ High oise Immunity haracteristic of OS Devices In ompliance with the Requirements Defined by EDE Standard o. 7 hip omplexity: 40 ETs or 0 Equivalent ates SUIX ERI PE SE SUIX PSTI PE SE D SUIX SOI PE SE OI DIR DT SUIX TSSOP PE SE Y 4 Y2 0 Y3 Y = + ORDERI IORTIO 54HXX 74HXX 74HXXD 74HXXDT eramic Plastic SOI TSSOP PI SSIET PI = V PI 7 = D 3 Y4 Y Y V Y Y D 7 3 UTIO TE Inputs H H H H Output Y H 0/95 otorola, Inc REV 7
2 54/74H02 ÎÎ XIU RTIS* SymbolÎ Parameter Value Unit ÎÎ V D Supply (Referenced to D) 0.5 to V ÎÎ V ÎÎ in D Input (Referenced to D) 0.5 to V V ÎÎ ÎÎ Vout D Output (Referenced to D) 0.5 to V V ÎÎ I in D Input urrent, per Pin ± 20 m ÎÎ I out D Output urrent, per Pin ± 25 m ÎÎ I D Supply urrent, V and D Pins ± 50 m ÎÎ PD Power Dissipation in Still ir, Plastic or eramic DIP 750 mw ÎÎ SOI Package ÎÎ 500 Î TSSOP Package 450 ÎÎ Î Î T stg Storage Temperature 65 to + 50 ÎÎ T ead Temperature, mm from ase for 0 Seconds Î Plastic DIP, SOI or TSSOP Package 260 eramic DIPÎÎ 300 * aximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditions. Derating Plastic DIP: 0 mw/ from 65 to 25 eramic DIP: 0 mw/ from 00 to 25 SOI Package: 7 mw/ from 65 to 25 TSSOP Package: 6. mw/ from 65 to 25 or high frequency or heavy load considerations, see hapter 2 of the otorola High Speed OS Data ook (D29/D). REOEDED OPERTI ODITIOS This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. or proper operation, Vin and Vout should be constrained to the range D (Vin or Vout) V. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either D or V). Unused outputs must be left open. Symbol Parameter in ax Unit V D Supply (Referenced to D) V Î Vin, Vout D Input, Output (Referenced to D) 0 V V T Operating Temperature, ll Package Types tr, tf Input Rise and all Time V = 2.0 V ns Î (igure ) V = 4.5 V Î V = 6.0 V Î D EETRI HRTERISTIS (s Referenced to D) Î uaranteed imit Î V 55 to Symbol Î Parameter Î Test onditions V Unit VIH Î inimum High evel Input Î Vout = 0. V or V 0. V V 20 µ ÎÎ VI Î aximum ow evel Input Î Vout = 0. V or V 0. V V 20 µ ÎÎ VOH Î inimum High evel Output Î Vin = VIH or VI V 20 µ Vin = VIH or VI ÎÎ 2.4 m m ÎÎ 5.2 m ÎÎ ÎÎ ÎÎ ÎÎ Î OTORO 3 2 High Speed OS ogic Data D29 Rev 6
3 54/74H02 Î D EETRI HRTERISTIS (s Referenced to D) Î uaranteed imit Î V 55 to Symbol Î Parameter Î Test onditions V Unit VO Î aximum ow evel Output Î Vin = VIH or VI 2.0 Î 20 µ 4.5 ÎÎ ÎÎ V Vin = VIH or VI ÎÎ 2.4 m m m ÎÎ Iin aximum Input eakage urrent Î Î Vin = V or D 6.0 ± 0. ±.0 ±.0 ÎÎ µ I aximum Quiescent Supply Î Î Vin = V or D 6.0 ÎÎ ÎÎ µ urrent (per Package) = 0 µ OTE: Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS Data ook (D29/D). EETRI HRTERISTIS ( = 50 p, Input tr = tf = 6.0 ns) uaranteed imit Î V 55 to Symbol Parameter V Unit Î tph, aximum Propagation Delay, Input or to Output Y ns tph Î (igures and 2) Î Î tth, aximum Output Transition Time, ny Output ns tth Î (igures and 2) Î aximum Input apacitance p in OTE: or propagation delays with loads other than 50 p, and information on typical parametric values, see hapter 2 of the otorola High Speed OS Data ook (D29/D). 25, V = 5.0 V PD Power Dissipation apacitance (Per ate)* 22 p * Used to determine the no load dynamic power consumption: PD = PD V 2 f + I V. or load considerations, see hapter 2 of the otorola High Speed OS Data ook (D29/D). High Speed OS ogic Data D29 Rev OTORO
4 54/74H02 tf tr TEST POIT IPUT OR OUTPUT Y 90% 50% 0% 90% 50% 0% tph tph V D DEVIE UDER TEST OUTPUT * tth tth * Includes all probe and jig capacitance igure. Switching Waveforms igure 2. Test ircuit EXPDED OI DIR (/4 O THE DEVIE) Y OTORO 3 4 High Speed OS ogic Data D29 Rev 6
5 54/74H02 OUTIE DIESIOS SUIX ERI DIP PE SE ISSUE Y -- -T- SETI PE 7 -- D P P 0.25 (0.00) T S 0.25 (0.00) T S. DIESIOI D TOERI PER SI Y.5, OTROI DIESIO: IH. 3. DIESIO TO ETER O ED WHE ORED PRE. 4. DIESIO Y RROW TO 0.76 (0.030) WHERE THE ED ETERS THE ERI ODY. DI D IHES I X S S IIETERS I X S S H D SETI PE SUIX PSTI DIP PE SE ISSUE. EDS WITHI 0.3 (0.005) RDIUS O TRUE POSITIO T SETI PE T XIU TERI ODITIO. 2. DIESIO TO ETER O EDS WHE ORED PRE. 3. DIESIO DOES OT IUDE OD SH. 4. ROUDED ORERS OPTIO. IHES IIETERS DI I X I X D S 2.54 S H S 7.62 S High Speed OS ogic Data D29 Rev OTORO
6 54/74H02 OUTIE DIESIOS D SUIX PSTI SOI PE SE ISSUE SETI PE 7 P 7 P D P 0.25 (0.00) T S S 0.25 (0.00) R X 45. DIESIOI D TOERI PER SI Y.5, OTROI DIESIO: IIETER. 3. DIESIOS D DO OT IUDE OD PROTRUSIO. 4. XIU OD PROTRUSIO 0.5 (0.006) PER SIDE. 5. DIESIO D DOES OT IUDE DR PROTRUSIO. OWE DR PROTRUSIO SH E 0.27 (0.005) TOT I EXESS O THE D DIESIO T XIU TERI ODITIO. DI D P R IIETERS I X S S IHES I X DT SUIX PSTI TSSOP PE SE 94 0 ISSUE O 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SETI PE U U S 2X /2 PI IDET. S D X RE 0.0 (0.004) T U S V S 0.25 (0.00) U 7 V H DETI E ÇÇÇ ÉÉÉ SETIO DETI E W. DIESIOI D TOERI PER SI Y.5, OTROI DIESIO: IIETER. 3. DIESIO DOES OT IUDE OD SH, PROTRUSIOS OR TE URRS. OD SH OR TE URRS SH OT EXEED 0.5 (0.006) PER SIDE. 4. DIESIO DOES OT IUDE ITERED SH OR PROTRUSIO. ITERED SH OR PROTRUSIO SH OT EXEED 0.25 (0.00) PER SIDE. 5. DIESIO DOES OT IUDE DR PROTRUSIO. OWE DR PROTRUSIO SH E 0.0 (0.003) TOT I EXESS O THE DIESIO T XIU TERI ODITIO. 6. TERI UERS RE SHOW OR REEREE OY. 7. DIESIO D RE TO E DETERIED T DTU PE W. IIETERS IHES DI I X I X D S S H S S 0 0 OTORO 3 6 High Speed OS ogic Data D29 Rev 6
7 54/74H02 otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/ffirmative ction Employer. How to reach us: US/EUROPE: otorola iterature Distribution; P: ippon otorola td.; Tatsumi SPD D, Toshikatsu Otsuki, P.O. ox 2092; Phoenix, rizona Seibu utsuryu enter, 3 2 Tatsumi oto u, Tokyo 35, apan X: RX0@ .sps.mot.com TOUHTOE (602) HO O: otorola Semiconductors H.. td.; Tai Ping Industrial Park, ITERET: ET.com 5 Ting ok Road, Tai Po,.T., Hong ong High Speed OS ogic Data D29 Rev 6 ODEIE 54/74H02/D 3 7 OTORO
High Performance Silicon Gate CMOS
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Is Now Part of To learn more about ON Semiconductor, please visit our website at
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MC74AC138, MC74ACT of 8 Decoder/Demultiplexer
1 of 8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple
NE522 High Speed Dual Differential Comparator/Sense Amp
HighSpeed DualDifferential Comparator/Sense Amp Features 5 ns Maximum Guaranteed Propagation Delay 0 A Maximum Input Bias Current TTL-Compatible Strobes and Outputs Large Common-Mode Input oltage Range
MC74HC244A Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver
Octal 3 State Noninverting Buffer/Line Driver/ Line Receiver High Performance Silicon Gate CMOS The MC74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs;
74HC74. Dual D Flip Flop with Set and Reset. High Performance Silicon Gate CMOS
Dual D Flip Flop with Set and Reset High Performance Silicon Gate CMOS The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
74HCT245. Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs. High-Performance Silicon-Gate CMOS
Octal 3-State Noninverting Bus Transceiver with LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The 74HCT245 is identical in pinout to LS245. The device has TTL-Compatible Inputs. The HCT245
Dual 4-Input AND Gate
TENIAL DATA Dual 4-Input AND ate The is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND function. Outputs Directly Interface
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620 MC10173L AWLYYWW
The MC03 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data
Triple 3-Input NOR Gate
TENIAL DATA IN4T2A Triple 3-Input NOR ate The IN4T2A is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Triple 3-input NOR function. Outputs
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS247 is a BCD-to-Seven-Segment Decoder/Drivers. The LS247 composes the and with the tails. The LS247 has active-low outputs for direct drive of indicators. The LS247 features a lamp test input
NL27WZU04. Dual Unbuffered Inverter
Dual Unbuffered Inverter The N27WZU04 is a high performance dual unbuffered inverter operating from a.5 to 5.5 V supply. These devices are well suited for use as oscillators, pulse shapers, and in many
MC74HC00A. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS
MC74C00A Quad 2 Input NAND Gate igh Performance Silicon Gate CMOS The MC74C00A is identical in pinout to the S00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they
MC74HCT138A. 1 of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT38A is identical in pinout to the LS38. The HCT38A may be used as a level converter for interfacing
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES ORDERING INFORMATION. SN74LS37xN AWLYYWW PDIP 20 N SUFFIX CASE 738
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B
MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC10176 contains six high-speed, master slave type D flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1. JFET Switching Transistors. N Channel. Pb Free Packages are Available.
LT1, LT1, LT1 JFET Switching Transistors NChannel Features PbFree Packages are Available MAXIMUM RATINGS Rating Symbol Value Unit DrainSource Voltage V DS Vdc DrainGate Voltage V DG Vdc GateSource Voltage
MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Pin Assignment VHCT139A AWLYYWW SOIC 16 D SUFFIX CASE 751B VHCT139A AWLYWW
The MC74HCT139A is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices
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MC74VHC00. Quad 2-Input NAND Gate
MC4C00 Quad 2-Input NAND Gate The MC4C00 is an advanced high speed CMOS 2 input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky
MUR405, MUR410, MUR415, MUR420, MUR440, MUR460
4, 4, 41, 42, 44, 46 42 and 46 are Preferred Devices SWITCHMODE Power Rectifiers These state of the art devices are a series designed for use in switching power supplies, inverters and as free wheeling
MARKING DIAGRAMS 16 LOGIC DIAGRAM DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE ORDERING INFORMATION CDIP 16 L SUFFIX CASE 620
The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place
NGTG50N60FLWG IGBT. 50 A, 600 V V CEsat = 1.65 V
NGTGN6FLWG IGBT This Insulated Gate Bipolar Transistor (IGBT) features a robust and cost effective Trench construction, and provides superior performance in demanding switching applications, offering both
IN74HC05A Hex Inverter with Open-Drain Outputs
TECNICL DT IN74C05 ex Inverter with Open-Drain Outputs The IN74C05 is identical in pinout to the LS/LS05. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible
MMBZ5221BLT1 Series. Zener Voltage Regulators. 225 mw SOT 23 Surface Mount
MMBZ5BLT Series Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed to provide voltage
NL27WZ00. Dual 2-Input NAND Gate. The NL27WZ00 is a high performance dual 2 input NAND Gate operating from a 1.65 V to 5.5 V supply.
Dual 2-Input NAND Gate The N27WZ00 is a high performance dual 2 input NAND Gate operating from a.65 to 5.5 supply. Features Extremely igh Speed: t PD ns (typical) at = 5.0 Designed for.65 to 5.5 Operation