SN54HC259, SN74HC259 8-BIT ADDRESSABLE LATCHES
|
|
- Marilynn Ross
- 6 years ago
- Views:
Transcription
1 SN4H29, SN4H29 8-BIT ARESSABLE LATHES 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel onversion With Storage Asynchronous Parallel lear Active-High ecoder Enable Input Simplifies Expansion Expandable for n-bit Applications Four istinct Functional Modes Package Options Include Plastic Small-Outline (), Thin Shrink Small-Outline (PW), and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J) 00-mil IPs SN4H29...J OR W PAKAGE SN4H29..., N, OR PW PAKAGE (TOP VIEW) S0 S1 S2 Q0 Q1 Q2 Q GN V LR G Q Q6 Q Q4 SN4H29... FK PAKAGE (TOP VIEW) description These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear (LR) and enable (G) inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs The SN4H29 is characterized for operation over the full military temperature range of to 12. The SN4H29 is characterized for operation from 40 to 8. S2 Q0 N Q1 Q2 S1 S0 N Q GN N V Q4 Q LR N No internal connection G N Q Q6 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PROUTION ATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 199, Texas Instruments Incorporated POST OFFIE BOX 60 ALLAS, TEXAS 26 1
2 SN4H29, SN4H29 8-BIT ARESSABLE LATHES Function Tables FUNTION INPUTS OUTPUT OF EAH ARESSE OTHER FUNTION LR G LATH OUTPUT H L QiO Addressable latch H H QiO QiO Memory L L L 8-line demultiplexer L H L L lear LATH SELETION SELET INPUTS LATH S2 S1 S0 ARESSE L L L 0 L L H 1 L H L 2 L H H H L L 4 H L H H H L 6 H H H 2 POST OFFIE BOX 60 ALLAS, TEXAS 26
3 SN4H29, SN4H29 8-BIT ARESSABLE LATHES logic symbol S0 S1 S2 G LR M 0 2 G8 Z9 Z10 9, 0 10, 0R 9, 10, 9, 2 10, 2R 9, 10, R 9, 4 10, 4R 9, 10, R 9, 6 10, 6R 9, 10, R Q0 Q1 Q2 Q Q4 Q Q6 Q This symbol is in accordance with ANSI/IEEE Std and IE Publication Pin numbers shown are for the, J, N, PW, and W packages. POST OFFIE BOX 60 ALLAS, TEXAS 26
4 SN4H29, SN4H29 8-BIT ARESSABLE LATHES logic diagram (positive logic) S0 1 4 Q0 Q1 S1 2 6 Q2 S2 9 Q Q4 10 Q G LR Q6 Q Pin numbers shown are for the, J, N, PW, and W packages. 4 POST OFFIE BOX 60 ALLAS, TEXAS 26
5 SN4H29, SN4H29 8-BIT ARESSABLE LATHES logic symbol, each internal latch R Q logic diagram, each internal latch (positive logic) TG Q TG R absolute maximum ratings over operating free-air temperature range Supply voltage range, V V to V Input clamp current, I IK (V I < 0 or V I > V ) (see Note 1) ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note 1) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±2 ma ontinuous current through V or GN ±0 ma Package thermal impedance, θ JA (see Note 2): package /W N package /W PW package /W Storage temperature range, T stg to 10 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JES 1, except for through-hole packages, which use a trace length of zero. POST OFFIE BOX 60 ALLAS, TEXAS 26
6 SN4H29, SN4H29 8-BIT ARESSABLE LATHES recommended operating conditions SN4H29 SN4H29 MIN NOM MAX MIN NOM MAX UNIT V Supply voltage V V = 2 V VIH High-level input voltage V = 4. V.1.1 V V = 6 V V = 2 V VIL Low-level input voltage V = 4. V V V = 6 V VI Input voltage V VO Output voltage V V = 2 V tt Input transition (rise and fall) time V = 4. V ns V = 6 V TA Operating free-air temperature electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONITIONS V TA = 2 SN4H29 SN4H29 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa 4. V VOH VI = VIH or VIL 6 V V IOH = 4 ma 4. V IOH =.2 ma 6 V V IOL = 20 µa 4. V VOL VI = VIH or VIL 6 V V IOL = 4 ma 4. V IOL =.2 ma 6 V II VI = V or 0 6 V ±0.1 ±100 ±1000 ±1000 na I VI = V or 0, IO = 0 6 V µa i 2 V to 6 V pf UNIT 6 POST OFFIE BOX 60 ALLAS, TEXAS 26
7 SN4H29, SN4H29 8-BIT ARESSABLE LATHES timing requirements over recommended operating free-air temperature range (unless otherwise noted) tw Pulse duration V TA = 2 SN4H29 SN4H29 MIN MAX MIN MAX MIN MAX 2 V LR low 4. V V V G low 4. V V V 11 9 tsu Setup time, data or address before G 4. V ns 6 V V th Hold time, data or address after G 4. V ns 6 V UNIT ns switching characteristics over recommended operating free-air temperature range, L = 0 pf (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) V TA = 2 SN4H29 SN4H29 MIN TYP MAX MIN MAX MIN MAX 2 V tphl LR Any Q 4. V ns 6 V V ata Any Q 4. V V V tpd Address Any Q 4. V ns 6 V V G Any Q 4. V V V tt Any 4. V ns 6 V UNIT operating characteristics, T A = 2 PARAMETER TEST ONITIONS TYP UNIT pd Power dissipation capacitance per latch No load pf POST OFFIE BOX 60 ALLAS, TEXAS 26
8 SN4H29, SN4H29 8-BIT ARESSABLE LATHES PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point L = 0 pf (see Note A) High-Level Pulse Low-Level Pulse tw V V LOA IRUIT VOLTAGE WAVEFORMS PULSE URATIONS Input V tplh tphl Reference Input ata Input 10% tsu th 90% 90% tr V V 10% tf In-Phase Output Out-of-Phase Output 10% tphl 90% 90% 90% tr 10% 10% tf tplh VOH 10% VOL tf VOH 90% VOL tr VOLTAGE WAVEFORMS SETUP AN HOL AN INPUT RISE AN FALL TIMES VOLTAGE WAVEFORMS PROPAGATION ELAY AN OUTPUT TRANSITION TIMES NOTES: A. L includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 0 Ω, tr = 6 ns, tf = 6 ns.. The outputs are measured one at a time with one input transition per measurement.. tplh and tphl are the same as tpd. Figure 1. Load ircuit and Voltage Waveforms 8 POST OFFIE BOX 60 ALLAS, TEXAS 26
9 IMPORTANT NOTIE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. ERTAIN APPLIATIONS USING SEMIONUTOR PROUTS MAY INVOLVE POTENTIAL RISKS OF EATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL AMAGE ( RITIAL APPLIATIONS ). TI SEMIONUTOR PROUTS ARE NOT ESIGNE, AUTHORIZE, OR WARRANTE TO BE SUITABLE FOR USE IN LIFE-SUPPORT EVIES OR SYSTEMS OR OTHER RITIAL APPLIATIONS. INLUSION OF TI PROUTS IN SUH APPLIATIONS IS UNERSTOO TO BE FULLY AT THE USTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. opyright 1998, Texas Instruments Incorporated
SN54HC42, SN74HC42 4-LINE TO 10-LINE DECODERS (1 of 10)
SNH, SNH -LINE TO -LINE EOERS ( of ) SLS EEMER REVISE MY Full ecoding of Input Logic ll Outputs re High for Invalid onditions lso for pplications as -Line to -Line ecoders Package Options Include Plastic
More informationSN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SNH8, SNH8 -LINE TO 8-LINE DEODERS/DEMULTIPLEXERS Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify ascading and/or Data Reception
More informationSN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B DECEMBER 1982 REVISED MAY 1997
ontain Eight Flip-Flops With Single-ail Outputs Direct lear Input Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Options
More informationSN54HC151, SN74HC151 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SNH, SNH 8-Line to -Line Multiplexers an Perform as: oolean Function enerators Parallel-to-Serial onverters Data Source Selectors Package Options Include Plastic Small-Outline (D) and eramic Flat () Packages,
More informationSN54HC682, SN74HC682 8-BIT MAGNITUDE COMPARATORS
SCLS0C MARCH 9 REVISED MAY 99 Compare Two -Bit Words 00-kΩ Pullup Resistors Are on the Q Inputs Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
More informationSN54HC20, SN74HC20 DUAL 4-INPUT POSITIVE-NAND GATES
SNHC0, SN7HC0 DUAL -INPUT POSITIVE-NAND GATES SCLS0C DECEMBER REVISED MAY 7 Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic
More informationSN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage ompatible ontain Eight D-Type Flip-Flops Direct lear Input Applicatio Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Optio Include Plastic Small-Outline
More informationSN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B DECEMBER 1982 REVISED MAY 1997
Package Optio Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J)
More informationSN54HC153, SN74HC153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
Permit Multiplexing from n Lines to One Line Perform Parallel-to-Serial Conversion Strobe (Enable) Line Provided for Cascading (N Lines to n Lines) Package Options Include Plastic Small-Outline (D), Thin
More informationSN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops.
More informationSN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SNH, SN7H -IT PLLEL-OUT SEIL SHIFT EGISTES SCLS DECEME 92 EVISED MY 997 ND-Gated (Enable/ Disable) Serial Inputs Fully uffered Clock and Serial Inputs Direct Clear Package Options Include Plastic Small-Outline
More informationSN54F251B, SN74F251B 1-OF-8 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
-State Versio of SNFB and SNFB -State Outputs Interface Directly ith System Bus Performs Parallel-to-Serial onversion omplementary Outputs Provide True and Inverted Data Package Optio Include Plastic Small-Outline
More informationSN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
Contain Four Flip-Flops With Double-ail Outputs Buffered Clock and Direct Clear Inputs Applicatio Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Optio Include Plastic Small-Outline
More informationSN54HC393, SN74HC393 DUAL 4-BIT BINARY COUNTERS
Dual 4-Bit Binary Counters With Individual Clocks Direct Clear for Each 4-Bit Counter Can Significantly Improve System Densities by educing Counter Package Count by 0 Percent Package Options Include Plastic
More informationSN54HC4060, SN74HC STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS
-SAGE ASYHONOUS BINAY COUNES AND OSCILLAOS SCLSB DECEMBE 82 EVISED MAY Allow Design of Either C or Crystal Oscillator Circuits Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages,
More informationTIL308, TIL309 NUMERIC DISPLAYS WITH LOGIC
SOLI-STTE ISPLYS WITH INTEGRL TTL MSI IRUIT HIP FOR USE IN LL SYSTEMS REQUIRING ISPLY OF B T 6,9-mm (0.270-Inch) haracter Height TIL308 Has Left ecimal TIL309 Has Right ecimal Easy System Interface Wide
More informationSN54F280B, SN74F280B 9-BIT PARITY GENERATORS/CHECKERS
SN0, SN70 -T PRTY NRTORS/KRS SS00 3, PRL RVS OTOR 3 enerates ither Odd or ven Parity for Nine ata Lines ascadable for N-its Parity Package Options nclude Plastic Small-Outline Packages, eramic hip arriers,
More informationTIL308, TIL309 NUMERIC DISPLAYS WITH LOGIC
SOLI-STTE ISPLYS WITH INTEGRL TTL MSI IRUIT HIP FOR USE IN LL SYSTEMS REQUIRING ISPLY OF B T 6,9-mm (0.270-Inch) haracter Height TIL308 Has Left ecimal TIL309 Has Right ecimal Easy System Interface Wide
More informationAVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) CERAMIC DIP (JG) TL7702ACD TL7715ACD TL7702ACP TL7715ACP TL7702ACY TL7715ACY
Power-On Reset Generator Automatic Reset Generation After Voltage Drop Wide Supply Voltage Range Precision Voltage Sensor Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally
More informationCD74HC165, CD74HCT165
Data sheet acquired from Harris Semiconductor SCHS156 February 1998 CD74HC165, CD74HCT165 High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register Features [ /Title (CD74H C165, CD74H CT165) /Subject
More informationCD74HC195. High Speed CMOS Logic 4-Bit Parallel Access Register. Features. Description. Ordering Information. PInout. [ /Title (CD74 HC195 ) /Subject
Data sheet acquired from Harris Semiconductor SCHS165 September 1997 High Speed CMOS Logic 4-Bit Parallel Access Register [ /Title (CD74 HC195 ) /Subject High peed MOS ogic -Bit aralel ccess egiser) /Autho
More informationCD74HC109, CD74HCT109
Data sheet acquired from Harris Semiconductor SCHS140 March 1998 CD74HC109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject Dual J- Fliplop
More informationCD54/74HC164, CD54/74HCT164
Data sheet acquired from Harris Semiconductor SCHS155A October 1997 - Revised May 2000 CD54/74HC164, CD54/74HCT164 High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register Features Description
More informationCD54/74AC153, CD54/74ACT153
CD4/74AC13, CD4/74ACT13 Data sheet acquired from Harris Semiconductor SCHS237A September 1998 - Revised May 2000 Dual 4-Input Multiplexer Features Description [ /Title (CD74 AC13, CD74 ACT1 3) /Subject
More informationCD74HC93, CD74HCT93. High Speed CMOS Logic 4-Bit Binary Ripple Counter. Description. Features. Pinout. Ordering Information
Data sheet acquired from Harris Semiconductor SCHS138 August 1997 CD74HC93, CD74HCT93 High Speed CMOS Logic 4-Bit Binary Ripple Counter [ /Title (CD74 HC93, CD74 HCT93 ) /Subject High peed MOS ogic -Bit
More informationCD74HC151, CD74HCT151
Data sheet acquired from Harris Semiconductor SCHS150 September 1997 CD74HC151, CD74HCT151 High Speed CMOS Logic 8-Input Multiplexer [ /Title (CD74H C151, CD74H CT151) /Subject High peed MOS ogic 8- nput
More informationTL7702B, TL7702BY, TL7705B, TL7705BY SUPPLY VOLTAGE SUPERVISORS
Power-On Reset Generator Automatic Reset Generation After Voltage Drop Output Defined From V CC 1 V Precision Voltage Seor Temperature-Compeated Voltage Reference True and Complement Reset Outputs Externally
More informationCD74HC147, CD74HCT147
Data sheet acquired from Harris Semiconductor SCHS149 September 1997 CD74HC147, CD74HCT147 High Speed CMOS Logic 10-to-4 Line Priority Encoder [ /Title (CD74 HC147, CD74 HCT14 7) /Subject (High Speed CMOS
More informationCD54/74HC393, CD54/74HCT393
CD54/74HC393, CD54/74HCT393 Data sheet acquired from Harris Semiconductor SCHS186A September 1997 - Revised May 2000 High Speed CMOS Logic Dual 4-Stage Binary Counter /Title CD74 C393 D74 CT39 ) Subect
More informationCD54/74HC151, CD54/74HCT151
CD54/74HC151, CD54/74HCT151 Data sheet acquired from Harris Semiconductor SCHS150A September 1997 - Revised May 2000 High Speed CMOS Logic 8-Input Multiplexer [ /Title (CD74H C151, CD74H CT151) /Subject
More informationHEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder
Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.
More informationDual 3-channel analog multiplexer/demultiplexer with supplementary switches
with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer
More informationCD54/74HC30, CD54/74HCT30
CD/7HC0, CD/7HCT0 Data sheet acquired from Harris Semiconductor SCHSA August 997 - Revised May 000 High Speed CMOS Logic 8-Input NAND Gate [ /Title (CDH C0, CD7H C0, CD7H CT0) /Subject High peed MOS ogic
More information74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:
Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
More informationCD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Data sheet acquired from Harris Semiconductor SCHS147C October 1997 - Revised August 2001 CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer
More information74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting
3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
More informationINTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 May 20 FEATURES Optimized for low voltage applicatio: 1.0 to 3.6 V Accepts TTL input levels between = 2.7 V and = 3.6 V Typical
More information2-input EXCLUSIVE-OR gate
Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
More information2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.
74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
More information74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter
Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
More informationINTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28
INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower
More informationTemperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.
Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
More informationTL601, TL604, TL607, TL610 P-MOS ANALOG SWITCHES
TL0, TL0, TL0, TL0 P-MO NLOG WITCHE L0 D, JUNE 9 REVIED OCTOBER 9 witch ± 0-V nalog ignals TTL Logic Capability -to 0-V upply Ranges Low (00 Ω) On-tate Resistance High (0 Ω) Off-tate Resistance -Pin Functions
More informationINTEGRATED CIRCUITS. 74ALS138 1-of-8 decoder/demultiplexer. Product specification 1996 Jul 03 IC05 Data Handbook
INTEGRATED CIRCUITS 1996 Jul 03 IC05 Data Handbook FEATURES Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding DESCRIPTION The decoder accepts three
More information74LV General description. 2. Features. 8-bit addressable latch
Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed
More information74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.
Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
More informationXC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger
Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
More information74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
More informationThe 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
More information74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.
Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
More information5-stage Johnson decade counter
Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
More informationINTEGRATED CIRCUITS. 74F154 1-of-16 decoder/demultiplexer. Product specification Jan 08. IC15 Data Handbook
INTEGRATED CIRCUITS 1-of-16 decoder/demultiplexer 1990 Jan 08 IC15 Data Handbook Decoder/demultiplexer FEATURES 16-line demultiplexing capability Mutually exclusive outputs 2-input enable gate for strobing
More informationThe 74LVC1G02 provides the single 2-input NOR function.
Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
More informationINTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels
More informationThe 74LV32 provides a quad 2-input OR function.
Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
More information74LVC374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS
INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of February 1996 IC24 ata Handbook 1997 Mar 12 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance
More information3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
with 30 Ω termination resistors; 3-state Rev. 03 17 January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The
More informationINTEGRATED CIRCUITS. 74F521 8-bit identity comparator. Product specification May 15. IC15 Data Handbook
INTEGRATED CIRCUITS 1990 May IC Data Handbook FEATURES Compares two 8-bit words in 6.5ns typical Expandable to any word length DESCRIPTION The is an expandable 8-bit comparator. It compares two words of
More information74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance
More information74AHC1G00; 74AHCT1G00
74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input
More information5.0 V 256 K 16 CMOS SRAM
February 2006 5.0 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C4098 Industrial and commercial temperature Organization: 262,144 words 16 bits Center power and ground pins High speed - 10/12/15/20
More information3.3 V 256 K 16 CMOS SRAM
August 2004 AS7C34098A 3.3 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C34098 Industrial and commercial temperature Organization: 262,144 words 16 bits Center power and ground pins High speed
More information74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More information74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger
INTEGRATED IRUITS positive-edge trigger Supersedes data of 1996 Nov 07 I24 Data andbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0 to 3.6V Accepts
More information74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
More informationThe 74LVC1G11 provides a single 3-input AND gate.
Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
More informationThe 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
More information4-bit magnitude comparator
Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than
More information74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
INTEGRATED CIRCUITS inputs/outputs; positive edge-trigger (3-State) 1998 Jul 29 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7 to 3.6 Complies with
More informationINTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels
More information74LV373 Octal D-type transparent latch (3-State)
INTEGRATED CIRCUITS 74V373 Supersedes data of 1997 March 04 IC24 Data andbook 1998 Jun 10 74V373 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0V to 3.6V Accepts
More informationINTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook
INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground
More informationPHD/PHP36N03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 General description. 1.
Rev. 2 8 June 26 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2
More information74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS
INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of 1996 Feb IC24 ata Handbook 1997 Mar 20 FEATURES Wide operating voltage: 1.0 to 5.5 Optimized for Low oltage
More information8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).
Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
More information8-bit binary counter with output register; 3-state
Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
More information93L34 8-Bit Addressable Latch
93L34 8-Bit Addressable Latch General Description The 93L34 is an 8-bit addressable latch designed for general purpose storage applications in digital systems It is a multifunctional device capable of
More information74AHC1G14; 74AHCT1G14
Rev. 6 18 May 29 Product data sheet 1. General description 2. Features 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt
More information74AHC14; 74AHCT14. Hex inverting Schmitt trigger
Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
More informationINTEGRATED CIRCUITS. 74F85 4-bit magnitude comparator. Product specification 1994 Sep 27 IC15 Data Handbook. Philips Semiconductors
INTEGRATED CIRCUITS 1994 Sep 27 IC15 Data Handbook Philips Semiconductors FEATURES High-impedance NPN base inputs for reduced loading (20µA in High and ow states) Magnitude comparison of any binary words
More informationApril 2004 AS7C3256A
pril 2004 S7C3256 3.3V 32K X 8 CMOS SRM (Common I/O) Features Pin compatible with S7C3256 Industrial and commercial temperature options Organization: 32,768 words 8 bits High speed - 10/12/15/20 ns address
More information74LVC573 Octal D-type transparent latch (3-State)
INTEGRATED CIRCUITS 74VC573 Supersedes data of February 1996 IC24 Data andbook 1997 Mar 12 74VC573 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance with JEDEC standard no. 8-1A Inputs accept
More informationORDERING INFORMATION T A PACKAGE ORDERABLE PARTNUMBER. SOIC - D -40 to 85 SOP NS Reel of 2000 MC74HC164NSR HC164
Wide Operating Voltage Range of 2 V to 6V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80- A Max I CC Typical t pd =20 ns 4-mA Output Drive at 5V Low Input Current of 1 A Max AND-Gated
More information5 V 64K X 16 CMOS SRAM
September 2006 A 5 V 64K X 16 CMOS SRAM AS7C1026C Features Industrial (-40 o to 85 o C) temperature Organization: 65,536 words 16 bits Center power and ground pins for low noise High speed - 15 ns address
More information74AHC2G126; 74AHCT2G126
Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line
More informationBCD to 7-segment latch/decoder/driver
Rev. 04 17 March 2009 Product data sheet 1. General description The is a for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH
More information74LV393 Dual 4-bit binary ripple counter
INTEGRATED CIRCUITS Supersedes data of 1997 Mar 04 IC24 Data Handbook 1997 Jun 10 FEATURES Optimized for Low Voltage applications: 1.0 to.6v Accepts TTL input levels between V CC = 2.7V and V CC =.6V Typical
More informationDM Bit Addressable Latch
8-Bit Addressable Latch General Description The DM9334 is a high speed 8-bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable
More informationDM54LS259 DM74LS259 8-Bit Addressable Latches
DM54LS259 DM74LS259 8-Bit Addressable Latches General Description These 8-bit addressable latches are designed for general purpose storage applications in digital systems Specific uses include working
More informationN-channel TrenchMOS logic level FET
Rev. 1 22 April 29 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This
More information74LVC823A 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State)
INTEGRATED CIRCUITS inputs/outputs; positive-edge trigger (3-State) 1998 Sep 24 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7V to 3.6V Complies
More informationINTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors
INTEGRATED CIRCUITS Supersedes data of 2001 May 09 2002 Dec 13 Philips Semiconductors FEATURES General purpose and PCI-X 1:4 clock buffer 8-pin TSSOP package See PCK2001 for 48-pin 1:18 buffer part See
More informationN-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package using
Rev. 24 March 29 Product data sheet. Product profile. General description N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package
More informationHex inverting Schmitt trigger with 5 V tolerant input
Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
More informationQuad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
More information74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state
Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
More informationMM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general
More informationφ φ0.2 Bare copper wire 2352 Walsh Ave., Santa Clara, CA 95051, U. S. A. Tel.: (408) , Fax: (408)
Figure 1. Physical Photo of Figure 2. Physical Photo of T70 MAIN FEATURES Glass Encapsulated for Long Term Stability & Reliability High Resistance Accuracy: 0.1% Temperature error: ±0.2 C Maximum Temp.
More information74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.
Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage
More informationINTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook
INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger 1997 Apr 07 IC24 Data Handbook FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V
More information