SN54HC20, SN74HC20 DUAL 4-INPUT POSITIVE-NAND GATES
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1 SNHC0, SN7HC0 DUAL -INPUT POSITIVE-NAND GATES SCLS0C DECEMBER REVISED MAY 7 Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain two independent -input NAND gates. They perform the Boolean function Y = A B C D or Y = A + B + C + D in positive logic. The SNHC0 is characterized for operation over the full military temperature range of C to C. The SN7HC0 is characterized for operation from 0 C to C. FUTION TABLE (each gate) INPUTS OUTPUT A B C D Y H H H H L L X X X H X L X X H X X L X H X X X L H SNHC0... J OR W PACKAGE SN7HC0...D OR N PACKAGE (TOP VIEW) GND 7 0 V CC SNHC0... FK PACKAGE (TOP VIEW) GND V CC No internal connection logic symbol 0 & This symbol is in accordance with ANSI/IEEE Std - and IEC Publication 7-. Pin numbers shown are for the D, J, N, and W packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Insuments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Insuments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 7, Texas Insuments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 7
2 SNHC0, SN7HC0 DUAL -INPUT POSITIVE-NAND GATES SCLS0C DECEMBER REVISED MAY 7 logic diagram (positive logic) Pin numbers shown are for the D, J, N, and W packages. 0 absolute maximum ratings over operating free-air temperature range Supply voltage range, V CC V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ) ±0 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note ) ±0 ma Continuous output current, I O (V O = 0 to V CC ) ± ma Continuous current through V CC or GND ±0 ma Package thermal impedance, θ JA (see Note ): D package C/W N package C/W Storage temperature range, T stg C to 0 C Sesses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are sess ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a ace length of zero. recommended operating conditions SNHC0 SN7HC0 MIN NOM MAX MIN NOM MAX Supply voltage V = V.. VIH High-level input voltage =. V.. V = V.. = V VIL Low-level input voltage =. V V = V VI Input voltage 0 0 V VO Output voltage 0 0 V = V tt Input ansition (rise and fall) time =. V ns = V TA Operating free-air temperature 0 C POST OFFICE BOX 0 DALLAS, TEXAS 7
3 SNHC0, SN7HC0 DUAL -INPUT POSITIVE-NAND GATES SCLS0C DECEMBER REVISED MAY 7 elecical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = C SNHC0 SN7HC0 MIN TYP MAX MIN MAX MIN MAX V.... IOH = 0 µa. V.... VOH VI = VIH or VIL V.... V IOH = ma. V...7. IOH =. ma V.... V IOL = 0 µa. V VOL VI = VIH or VIL V V IOL = ma. V IOL =. ma V II VI = or 0 V ±0. ±00 ±000 ±000 na ICC VI = or 0, IO = 0 V 0 0 µa Ci V to V pf switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) TA = C SNHC0 SN7HC0 MIN TYP MAX MIN MAX MIN MAX V 0 0 tpd A, B, C, or D Y. V ns V V tt Y. V ns V 7 operating characteristics, T A = C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance per gate No load pf POST OFFICE BOX 0 DALLAS, TEXAS 7
4 SNHC0, SN7HC0 DUAL -INPUT POSITIVE-NAND GATES SCLS0C DECEMBER REVISED MAY 7 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 0 pf (see Note A) Input tplh tphl 0 V LOAD CIRCUIT In-Phase Output 0% 0% VOH VOL Input 0% 0% 0 V Out-of-Phase Output tphl 0% tplh VOH 0% VOL VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbiarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, = ns, = ns. C. The outputs are measured one at a time with one input ansition per measurement. D. tplh and tphl are the same as tpd. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS 7
5 IMPORTANT NOTICE Texas Insuments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality conol techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. ILUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright, Texas Insuments Incorporated
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