CD54/74HC30, CD54/74HCT30
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1 CD/7HC0, CD/7HCT0 Data sheet acquired from Harris Semiconductor SCHSA August Revised May 000 High Speed CMOS Logic 8-Input NAND Gate [ /Title (CDH C0, CD7H C0, CD7H CT0) /Subject High peed MOS ogic 8- Features Buffered Inputs Typical Propagation Delay: 0ns at = V, C L = pf, T A = o C Fanout (Over Temperature Range) - Standard Outputs LS - Bus Driver Outputs LS Wide Operating Temperature Range... - o C to o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - V to 6V Operation - High Noise Immunity: N IL = 0%, N IH = 0% of at = V HCT Types -.V to.v Operation - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V IH = V (Min) - CMOS Input Compatibility, I l µa at V OL, V OH Description The HC0 and HCT0 each contain an 8-input NAND gate in one package. They provide the system designer with the direct implementation of the positive logic 8-input NAND function. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 0 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CDHC0F - to Ld CERDIP CDHC0FA - to Ld CERDIP CD7HC0E - to Ld PDIP CD7HC0M - to Ld SOIC CDHCT0FA - to Ld CERDIP CDHCT0H - to Die CD7HCT0E - to Ld PDIP CD7HCT0M - to Ld SOIC NOTES:. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.. Die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinout CDHC0, CDHCT0 (CERDIP) CD7HC0, CD7HCT0 (PDIP, SOIC) TOP VIEW A B NC C H D G E 0 NC F 6 9 NC 7 8 Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 000, Texas Instruments Incorporated.
2 CD/7HC0, CD/7HCT0 Functional Diagram A B C D E F G H 6 8 Y Y = ABCDEFGH TRUTH TABLE INPUTS A B C D E F G H OUTPUT L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L NOTE: H = HIGH Level, L = LOW Level, X = Irrelevant Logic Symbol A B C D E 8 Y F 6 G H
3 CD/7HC0, CD/7HCT0 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode, I IK For V I < -0.V or V I > + 0.V ±0mA DC Output Diode, I OK For V O < -0.V or V O > + 0.V ±0mA DC Output Source or Sink per Output Pin, I O For V O > -0.V or V O < + 0.V ±mA DC or Ground, I CC or I ±0mA Operating Conditions Temperature Range (T A ) o C to o C Supply Range, HC Types V to 6V HCT Types V to.v DC Input or Output, V I, V O V to Input Rise and Fall Time V ns (Max).V ns (Max) 6V ns (Max) Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIP Package N/A CERDIP Package SOIC Package N/A Maximum Junction Temperature (Hermetic Package or Die)... 7 o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering 0s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications HC TYPES High Level Input Low Level Input Input Leakage o C -0 o C TO +8 o C - o C TO o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V V V V OH V OL I I V IH or V V V V V V V IH or V V V or V V V ±0. - ± - ± µa
4 CD/7HC0, CD/7HCT0 DC Electrical Specifications (Continued) Quiescent Device HCT TYPES High Level Input Low Level Input Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: Unit Load (Note ) I CC or V IH - -. to to. V OH V OL I I I CC I CC o C -0 o C TO +8 o C - o C TO o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX µa V V V IH or V V V IH or V and or V -. - ±0. - ± - ± µa µa -. to. NOTE:. For dual-supply systems theoretical worst case (V I =.V, =.V) specification is.8ma. HCT Input Loading Table µa INPUT UNIT LOADS All 0.6 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g. 60µA max at o C. Switching Specifications Input t r, t f = 6ns HC TYPES Propagation Delay, Input to Output (Figure ) Propagation Delay, Data Input to Output Y (V) o C -0 o C TO 8 o C - o C TO o C MIN TYP MAX MIN MAX MIN MAX t PLH, t PHL C L = 0pF ns ns ns t PLH, t PHL C L = pf ns
5 CD/7HC0, CD/7HCT0 Switching Specifications Input t r, t f = 6ns (Continued) Transition Times (Figure ) t TLH, t THL C L = 0pF ns ns ns Input Capacitance C I pf Power Dissipation Capacitance (Notes, 6) C PD pf HCT TYPES Propagation Delay, Input to Output (Figure ) Propagation Delay, Data Input to Output Y t RHL, t PHL C L = 0pF ns t PLH, t PHL C L = pf ns Transition Times (Figure ) t TLH, t THL C L = 0pF ns Input Capacitance C I pf Power Dissipation Capacitance (Notes, 6) C PD pf NOTES:. C PD is used to determine the dynamic power consumption, per gate. 6. P D = V CC f i (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, = Supply. (V) o C -0 o C TO 8 o C - o C TO o C MIN TYP MAX MIN MAX MIN MAX Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 0% 0% INPUT.7V.V 0.V V t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 90% 0% 0% INVERTING OUTPUT t PHL t PLH 90%.V 0% FIGURE. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 000, Texas Instruments Incorporated
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