CD54/74HC30, CD54/74HCT30

Transcription

1 CD54/74HC30, CD54/74HCT30 Data sheet acquired from Harris Semiconductor SCHS121D August Revised September 2003 High Speed CMOS Logic 8-Input NAND Gate [ /Title (CD54H C30, CD74H C30, CD74H CT30) /Subject (High Speed CMOS Logic 8- Features Buffered Inputs Typical Propagation Delay: 10ns at V CC = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The HC30 and HCT30 each contain an 8-input NAND gate in one package. They provide the system designer with the direct implementation of the positive logic 8-input NAND function. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC30F3A -55 to Ld CERDIP CD54HCT30F3A -55 to Ld CERDIP CD74HC30E -55 to Ld PDIP CD74HC30M -55 to Ld SOIC CD74HC30MT -55 to Ld SOIC CD74HC30M96-55 to Ld SOIC CD74HC30NSR -55 to Ld SOP Pinout CD54HC30, CD54HCT30 (CERDIP) CD74HC30 (PDIP, SOIC, SOP, TSSOP) CD74HCT30 (PDIP, SOIC) TOP VIEW CD74HC30PW -55 to Ld TSSOP CD74HC30PWR -55 to Ld TSSOP CD74HC30PWT -55 to Ld TSSOP CD74HCT30E -55 to Ld PDIP A 1 14 V CC CD74HCT30M -55 to Ld SOIC B C D NC H G CD74HCT30MT -55 to Ld SOIC CD74HCT30M96-55 to Ld SOIC E F GND NC NC Y NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2003, Texas Instruments Incorporated. 1

2 CD54/74HC30, CD54/74HCT30 Functional Diagram A B C D E F G H Y Y = ABCDEFGH TRUTH TABLE INPUTS A B C D E F G H OUTPUT L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L NOTE: H = HIGH Level, L = LOW Level, X = Irrelevant Logic Symbol A 1 B 2 C 3 D E Y F 6 11 G 12 H 2

3 CD54/74HC30, CD54/74HCT30 Absolute Maximum Ratings DC Supply, V CC V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > V CC + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > V CC + 0.5V ±20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V ±25mA DC V CC or Ground Current, I CC or I GND ±50mA Operating Conditions Temperature Range (T A ) o C to 125 o C Supply Range, V CC HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to V CC Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) Thermal Information Package Thermal Impedance, θ JA (see Note 1) E (PDIP) Package o C/W M (SOIC) Package o C/W NS (SOP) Package o C/W PW (TSSOP) Package o C/W Maximum Junction Temperature (Hermetic Package or Die) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current SYMBOL TEST CONDITIONS 25 o C -40 o C TO +85 o C -55 o C TO 125 o C V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V OL I I UNITS V IH or V V IL V V V V V V IH or V V IL V V V CC or GND V V V ±0.1 - ±1 - ±1 µa 3

4 CD54/74HC30, CD54/74HCT30 DC Electrical Specifications (Continued) PARAMETER Quiescent Device Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 2) SYMBOL I CC V CC or GND V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC TEST CONDITIONS 25 o C -40 o C TO +85 o C -55 o C TO 125 o C V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX µa V V V IH or V V IL V V IH or V V IL V CC and GND V CC or GND V CC V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTE: 2. For dual-supply systems theoretical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA. HCT Input Loading Table UNITS µa INPUT UNIT LOADS All 0.6 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25 o C. Switching Specifications Input t r, t f = 6ns PARAMETER HC TYPES Propagation Delay, Input to Output (Figure 1) Propagation Delay, Data Input to Output Y SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS t PLH, t PHL C L = 50pF ns ns ns t PLH, t PHL C L = 15pF ns 4

5 CD54/74HC30, CD54/74HCT30 Switching Specifications Input t r, t f = 6ns (Continued) PARAMETER Transition Times (Figure 1) t TLH, t THL C L = 50pF ns ns ns Input Capacitance C I pf Power Dissipation Capacitance (Notes 3, 4) C PD pf HCT TYPES Propagation Delay, Input to Output (Figure 2) Propagation Delay, Data Input to Output Y SYMBOL TEST CONDITIONS t RHL, t PHL C L = 50pF ns t PLH, t PHL C L = 15pF ns Transition Times (Figure 2) t TLH, t THL C L = 50pF ns Input Capacitance C I pf Power Dissipation Capacitance (Notes 3, 4) C PD pf NOTES: 3. C PD is used to determine the dynamic power consumption, per gate. 4. P D = V 2 CC f i (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, V CC = Supply. V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 50% 10% V CC GND INPUT 2.7V 1.3V 0.3V 3V GND t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 90% 50% 10% INVERTING OUTPUT t PHL t PLH 90% 1.3V 10% FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5

6 PACKAGE OPTION ADDENDUM 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to CA CD54HCT30F3A CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to CA CD54HC30F3A CD54HC30F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC30F (4/5) Samples CD54HC30F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to CA CD54HC30F3A CD54HCT30F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to CA CD54HCT30F3A CD74HC30E ACTIVE PDIP N Pb-Free (RoHS) CD74HC30EE4 ACTIVE PDIP N Pb-Free (RoHS) CD74HC30M ACTIVE SOIC D Green (RoHS CD74HC30M96 ACTIVE SOIC D Green (RoHS CD74HC30M96G4 ACTIVE SOIC D Green (RoHS CD74HC30MG4 ACTIVE SOIC D Green (RoHS CD74HC30MT ACTIVE SOIC D Green (RoHS CD74HC30MTE4 ACTIVE SOIC D Green (RoHS CD74HC30NSR ACTIVE SO NS Green (RoHS CD74HC30PW ACTIVE TSSOP PW Green (RoHS CD74HC30PWG4 ACTIVE TSSOP PW Green (RoHS CD74HC30PWR ACTIVE TSSOP PW Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC30E CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC30E CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30 CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30 CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30 Addendum-Page 1

7 PACKAGE OPTION ADDENDUM 10-Jun-2014 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan CD74HC30PWRG4 ACTIVE TSSOP PW Green (RoHS CD74HC30PWT ACTIVE TSSOP PW Green (RoHS CD74HCT30E ACTIVE PDIP N Pb-Free (RoHS) CD74HCT30EE4 ACTIVE PDIP N Pb-Free (RoHS) CD74HCT30M ACTIVE SOIC D Green (RoHS CD74HCT30M96 ACTIVE SOIC D Green (RoHS CD74HCT30MT ACTIVE SOIC D Green (RoHS (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30 CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30 CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT30E CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT30E CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2

8 PACKAGE OPTION ADDENDUM 10-Jun-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC30, CD54HCT30, CD74HC30, CD74HCT30 : Catalog: CD74HC30, CD74HCT30 Military: CD54HC30, CD54HCT30 NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page 3

9 PACKAGE MATERIALS INFORMATION 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CD74HC30M96 SOIC D Q1 CD74HC30MT SOIC D Q1 CD74HC30NSR SO NS Q1 CD74HC30PWR TSSOP PW Q1 CD74HC30PWT TSSOP PW Q1 CD74HCT30M96 SOIC D Q1 CD74HCT30MT SOIC D Q1 Pack Materials-Page 1

10 PACKAGE MATERIALS INFORMATION 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC30M96 SOIC D CD74HC30MT SOIC D CD74HC30NSR SO NS CD74HC30PWR TSSOP PW CD74HC30PWT TSSOP PW CD74HCT30M96 SOIC D CD74HCT30MT SOIC D Pack Materials-Page 2

11

12

13

14

15

16

17 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated ( TI ) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, TI Resources ) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. TI s provision of TI Resources does not expand or otherwise alter TI s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications (and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED AS IS AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice. This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services. These include; without limitation, TI s standard terms for semiconductor products evaluation modules, and samples ( Mailing Address: Texas Instruments, Post Office Box , Dallas, Texas Copyright 2017, Texas Instruments Incorporated