SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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1 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS Operating Range -V to.-v V CC Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception SNAHC8...J OR W PACKAGE SNAHC8...D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) A B C GA GB G Y GND V CC Y0 Y Y Y Y Y Y description/ordering information SNAHC8... RGY PACKAGE (TOP VIEW) B C GA GB G Y A 8 9 GND SCLS8L DECEMBER 99 REVISED JULY 00 Latch-Up Performance Exceeds 0 ma Per JESD ESD Protection Exceeds JESD 000-V Human-Body Model (A-A) 00-V Machine Model (A-A) 000-V Charged-Device Model (C0) CC Y V 0 Y0 Y Y Y Y Y SNAHC8...FK PACKAGE (TOP VIEW) C GA NC GB G B A NC V CC Y Y GND NC Y Y NC No internal connection The AHC8 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. ORDERING INFORMATION T A PACKAGE ORDERABLE TOP-SIDE PART NUMBER MARKING QFN RGY Tape and reel SNAHC8RGYR HA8 PDIP N Tube SNAHC8N SNAHC8N Tube SNAHC8D SOIC D Tape and reel SNAHC8DR AHC8 0 C to 8 C SOP NS Tape and reel SNAHC8NSR AHC8 SSOP DB Tape and reel SNAHC8DBR HA8 TSSOP PW Tube Tape and reel SNAHC8PW SNAHC8PWR HA8 TVSOP DGV Tape and reel SNAHC8DGVR HA8 CDIP J Tube SNJAHC8J SNJAHC8J C to C CFP W Tube SNJAHC8W SNJAHC8W LCCC FK Tube SNJAHC8FK SNJAHC8FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Y Y NC Y Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 00, Texas Instruments Incorporated On products compliant to MIL-PRF-8, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 0 DALLAS, TEXAS

2 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS8L DECEMBER 99 REVISED JULY 00 description/ordering information (continued) The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A -line decoder can be implemented without external inverters, and a -line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. FUNCTION TABLE ENABLE INPUTS SELECT INPUTS OUTPUTS G GA GB C B A Y0 Y Y Y Y Y Y Y X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L logic diagram (positive logic) A Y0 Y Select Inputs B Y Y C Y Data Outputs 0 Y 9 Y Enable Inputs GA GB G Y Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. POST OFFICE BOX 0 DALLAS, TEXAS

3 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS8L DECEMBER 99 REVISED JULY 00 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to V Input voltage range, V I (see Note ) V to V Output voltage range, V O (see Note ) V to V CC + 0. V Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0 or V O > V CC ) ±0 ma Continuous output current, I O (V O = 0 to V CC ) ± ma Continuous current through V CC or GND ± ma Package thermal impedance, θ JA (see Note ): D package C/W (see Note ): DB package C/W (see Note ): DGV package C/W (see Note ): N package C/W (see Note ): NS package C/W (see Note ): PW package C/W (see Note ): RGY package C/W Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.. The package thermal impedance is calculated in accordance with JESD -.. The package thermal impedance is calculated in accordance with JESD -. recommended operating conditions (see Note ) SNAHC8 SNAHC8 MIN MAX MIN MAX UNIT V CC Supply voltage.. V V CC = V.. V IH High-level input voltage V CC = V.. V V CC =. V.8.8 V CC = V V IL Low-level input voltage V CC = V V V CC =. V.. V I Input voltage V V O Output voltage 0 V CC 0 V CC V V CC = V 0 0 A I OH High-level output current V CC =. V ± 0. V V CC = V ± 0. V 8 8 ma V CC = V 0 0 A I OL Low-level output current V CC =. V ± 0. V V CC = V ± 0. V 8 8 Δt/Δv Input transition rise or fall rate V CC =. V ± 0. V V CC = V ± 0. V 0 0 T A Operating free-air temperature 0 8 C NOTE : All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA00. ma ns/v POST OFFICE BOX 0 DALLAS, TEXAS

4 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS8L DECEMBER 99 REVISED JULY 00 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) T A = C SNAHC8 SNAHC8 PARAMETER TEST CONDITIONS V CC MIN TYP MAX MIN MAX MIN MAX UNIT V OH V V.... V I OH = 0 A V I OH = ma V V OL I OH = 8 ma. V V V V I OL = 0 A V I OL = ma V I OL = 8 ma. V I I V I =. V or GND 0 V to. V ±0. ±* ± A I CC V I = V CC or GND, I O = 0. V 0 0 A C i V I = V CC or GND V 0 0 pf * On products compliant to MIL-PRF-8, this parameter is not production tested at V CC = 0 V. switching characteristics over recommended operating free-air temperature range, V CC =. V ± 0. V (unless otherwise noted) (see Figure ) FROM TO LOAD T A = C SNAHC8 SNAHC8 PARAMETER (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX t PLH 8.**.** ** ** A, B, C Any Y C t L = pf PHL 8.**.** ** ** t PLH 8.**.8** ** ** G Any Y C L = pf t PHL 8.**.8** ** ** t PLH 8.**.** **.**. GA, GB Any Y C L = pf t PHL 8.**.** **.**. t PLH A, B, C Any Y C L = 0 pf t PHL t PLH G Any Y C L = 0 pf t PHL t PLH 0..9 GA, GB Any Y C L =0pF t PHL 0..9 ** On products compliant to MIL-PRF-8, this parameter is not production tested. UNIT ns ns ns ns ns ns POST OFFICE BOX 0 DALLAS, TEXAS

5 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS8L DECEMBER 99 REVISED JULY 00 switching characteristics over recommended operating free-air temperature range, V CC = V ± 0. V (unless otherwise noted) (see Figure ) FROM TO LOAD T A = C SNAHC8 SNAHC8 PARAMETER (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX t PLH.* 8.* * 9.* 9. A, B, C Any Y C t L = pf PHL.* 8.* * 9.* 9. t PLH.* 8.* * 9.* 9. G Any Y C L = pf t PHL.* 8.* * 9.* 9. t PLH.8* 8.* * 9.* 9. GA, GB Any Y C L = pf t PHL.8* 8.* * 9.* 9. t PLH A, B, C Any Y C L = 0 pf t PHL t PLH G Any Y C L = 0 pf t PHL t PLH GA, GB Any Y C L =0pF t PHL * On products compliant to MIL-PRF-8, this parameter is not production tested. UNIT ns ns ns ns ns ns operating characteristics, V CC = V, T A = C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance No load, f = MHz pf POST OFFICE BOX 0 DALLAS, TEXAS

6 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS8L DECEMBER 99 REVISED JULY 00 PARAMETER MEASUREMENT INFORMATION From Output Under Test C L (see Note A) Test Point From Output Under Test C L (see Note A) R L = kω S V CC Open GND TEST t PLH /t PHL t PLZ /t PZL t PHZ /t PZH Open Drain S Open V CC GND V CC LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR -STATE AND OPEN-DRAIN OUTPUTS Input 0% V CC t w 0% V CC V CC 0 V Timing Input Data Input t su 0% V CC t h 0% V CC 0% V CC V CC 0 V V CC 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 0% V CC 0% V CC V CC 0 V Output Control 0% V CC 0% V CC V CC 0 V In-Phase Output t PLH 0% V CC t PHL V OH 0% V CC V OL Output Waveform S at V CC (see Note B) t PZL t PLZ 0% V CC V OL + 0. V V CC V OL Out-of-Phase Output t PHL 0% V CC t PLH V OH 0% V CC V OL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform S at GND (see Note B) t PZH t PHZ V OH 0% V CC V OH 0. V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. C L includes probe and jig capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, Z O = 0 Ω, t r ns, t f ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS

7 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS APPLICATION INFORMATION SCLS8L DECEMBER 99 REVISED JULY 00 SNAHC8 V CC BIN/OCT & EN SNAHC8 A0 A A A A BIN/OCT & EN SNAHC8 BIN/OCT & EN Figure. -Bit Decoding Scheme POST OFFICE BOX 0 DALLAS, TEXAS

8 SNAHC8, SNAHC8 -LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS8L DECEMBER 99 REVISED JULY 00 APPLICATION INFORMATION SNAHC8 A0 A A V CC A A BIN/OCT & EN SNAHC8 BIN/OCT & EN SNAHC8 BIN/OCT & EN SNAHC8 BIN/OCT & EN Figure. -Bit Decoding Scheme 8 POST OFFICE BOX 0 DALLAS, TEXAS

9 PACKAGE OPTION ADDENDUM -Aug-08 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) 9-980QA ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type - to 9-980QA SNJAHC 8FK Device Marking 9-980QEA ACTIVE CDIP J TBD A N / A for Pkg Type - to 9-980QE A SNJAHC8J 9-980QFA ACTIVE CFP W TBD A N / A for Pkg Type - to 9-980QF A SNJAHC8W SNAHC8D ACTIVE SOIC D 0 Green (RoHS & no Sb/Br) SNAHC8DBR ACTIVE SSOP DB 000 Green (RoHS & no Sb/Br) SNAHC8DGVR ACTIVE TVSOP DGV 000 Green (RoHS & no Sb/Br) SNAHC8DR ACTIVE SOIC D 00 Green (RoHS & no Sb/Br) SNAHC8DRE ACTIVE SOIC D 00 Green (RoHS & no Sb/Br) SNAHC8DRG ACTIVE SOIC D 00 Green (RoHS & no Sb/Br) SNAHC8N ACTIVE PDIP N Green (RoHS & no Sb/Br) SNAHC8NSR ACTIVE SO NS 000 Green (RoHS & no Sb/Br) SNAHC8PW ACTIVE TSSOP PW 90 Green (RoHS & no Sb/Br) SNAHC8PWR ACTIVE TSSOP PW 000 Green (RoHS & no Sb/Br) SNAHC8PWRE ACTIVE TSSOP PW 000 Green (RoHS & no Sb/Br) SNAHC8PWRG ACTIVE TSSOP PW 000 Green (RoHS & no Sb/Br) CU NIPDAU Level--0C-UNLIM -0 to 8 AHC8 CU NIPDAU Level--0C-UNLIM -0 to 8 HA8 CU NIPDAU Level--0C-UNLIM -0 to 8 HA8 CU NIPDAU Level--0C-UNLIM -0 to 8 AHC8 CU NIPDAU Level--0C-UNLIM -0 to 8 AHC8 CU NIPDAU Level--0C-UNLIM -0 to 8 AHC8 CU NIPDAU N / A for Pkg Type -0 to 8 SNAHC8N CU NIPDAU Level--0C-UNLIM -0 to 8 AHC8 CU NIPDAU Level--0C-UNLIM -0 to 8 HA8 CU NIPDAU Level--0C-UNLIM -0 to 8 HA8 CU NIPDAU Level--0C-UNLIM -0 to 8 HA8 CU NIPDAU Level--0C-UNLIM -0 to 8 HA8 (/) Samples Addendum-Page

10 PACKAGE OPTION ADDENDUM -Aug-08 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan SNAHC8RGYR ACTIVE VQFN RGY 000 Green (RoHS & no Sb/Br) () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) CU NIPDAU Level--0C- YEAR -0 to 8 HA8 SNJAHC8FK ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type - to 9-980QA SNJAHC 8FK Device Marking SNJAHC8J ACTIVE CDIP J TBD A N / A for Pkg Type - to 9-980QE A SNJAHC8J SNJAHC8W ACTIVE CFP W TBD A N / A for Pkg Type - to 9-980QF A SNJAHC8W (/) Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 0 RoHS substances, including the requirement that RoHS substance do not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS09B low halogen requirements of <=000ppm threshold. Antimony trioxide based flame retardants must also meet the <=000ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. () Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page

11 PACKAGE OPTION ADDENDUM -Aug-08 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SNAHC8, SNAHC8 : Catalog: SNAHC8 Military: SNAHC8 NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page

12 PACKAGE MATERIALS INFORMATION 8-Apr-0 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant SNAHC8DBR SSOP DB Q SNAHC8DGVR TVSOP DGV Q SNAHC8DR SOIC D Q SNAHC8PWR TSSOP PW Q SNAHC8RGYR VQFN RGY Q Pack Materials-Page

13 PACKAGE MATERIALS INFORMATION 8-Apr-0 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SNAHC8DBR SSOP DB SNAHC8DGVR TVSOP DGV SNAHC8DR SOIC D SNAHC8PWR TSSOP PW SNAHC8RGYR VQFN RGY Pack Materials-Page

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17 SCALE.00 PW00A PACKAGE OUTLINE TSSOP -. mm max height SMALL OUTLINE PACKAGE A. TYP. PIN INDEX AREA X 0. C SEATING PLANE 0. C X..9 NOTE. 8 B.. NOTE 9 X C A B. MAX SEE DETAIL A (0.) TYP 0. GAGE PLANE A 0 DETAIL A TYPICAL 00/A 0/0 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y.M.. This drawing is subject to change without notice.. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0. mm per side.. This dimension does not include interlead flash. Interlead flash shall not exceed 0. mm per side.. Reference JEDEC registration MO-.

18 .000 PW00A EXAMPLE BOARD LAYOUT TSSOP -. mm max height SMALL OUTLINE PACKAGE X (.) SYMM X (0.) (R0.0) TYP SYMM X (0.) 8 9 (.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 0X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.0 MAX ALL AROUND 0.0 MIN ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS SOLDER MASK DEFINED 00/A 0/0 NOTES: (continued). Publication IPC- may have alternate designs.. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

19 PW00A EXAMPLE STENCIL DESIGN TSSOP -. mm max height SMALL OUTLINE PACKAGE X (0.) X (.) SYMM (R0.0) TYP SYMM X (0.) 8 9 (.8) SOLDER PASTE EXAMPLE BASED ON 0. mm THICK STENCIL SCALE: 0X 00/A 0/0 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC- may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

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21 MECHANICAL DATA MPDS00C FEBRUARY 99 REVISED AUGUST 000 DGV (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE 0,0 0, 0, 0,0 M 0, NOM,0,0,0,0 Gage Plane A 0 8 0, 0, 0,0,0 MAX 0, 0,0 Seating Plane 0,08 DIM PINS ** A MAX,0,0,0,0,90 9,80,0 A MIN,0,0,90,90,0 9,0,0 0/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0, per side. D. Falls within JEDEC: /8 Pins MO- //0/ Pins MO-9 POST OFFICE BOX 0 DALLAS, TEXAS

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24 MECHANICAL DATA MSSO00E JANUARY 99 REVISED DECEMBER 00 DB (R-PDSO-G**) 8 PINS SHOWN PLASTIC SMALL-OUTLINE 0, 0,8 0, 0, M 8,0,00 8,0,0 0, 0,09 Gage Plane 0, A 0 8 0,9 0,,00 MAX 0,0 MIN Seating Plane 0,0 DIM PINS ** A MAX,0,0,0 8,0 0,0 0,0,90 A MIN,90,90,90,90 9,90 9,90,0 000 /E /0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,. D. Falls within JEDEC MO-0 POST OFFICE BOX 0 DALLAS, TEXAS

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