CD54/74AC153, CD54/74ACT153

Transcription

1 CD4/74AC13, CD4/74ACT13 Data sheet acquired from Harris Semiconductor SCHS237A September Revised May 2000 Dual 4-Input Multiplexer Features Description [ /Title (CD74 AC13, CD74 ACT1 3) /Subject (Dual 4-Input Multiplexer) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS ) /Creator () /DOCI NFO pdfmark Buffered Inputs Typical Propagation Delay - 6.3ns at V CC = V, T A = 2 o C, C L = 0pF Exceeds 2kV ESD Protection MIL-STD-883, Method 301 SCR-Latchup-Resistant CMOS Process and Circuit Design Speed of Bipolar FAST /AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature 1.V to.v Operation and Balanced Noise Immunity at 30% of the Supply ±24mA Output Drive Current - Fanout to 1 FAST ICs - Drives 0Ω Transmission Lines Pinout CD4AC13, CD4ACT13 (CERDIP) CD74AC13, CD74ACT13 (PDIP, SOIC) TOP VIEW 1E S1 1I 3 1I 2 1I 1 1I 0 1Y The AC13 and ACT13 are dual 4-input multiplexers that utilize Advanced CMOS Logic technology. One of the four sources for each section is selected by the common Select inputs, S0 and S1. When the Enable inputs (1E, 2E) are HIGH, the outputs are in the low state. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD4AC13F3A 16 Ld CERDIP CD74AC13E 0 to 70 o C, -40 to 8, CD74AC13M96 0 to 70 o C, -40 to 8, 16 Ld PDIP 16 Ld SOIC CD4ACT13F3A 16 Ld CERDIP CD74ACT13E 0 to 70 o C, -40 to 8, 16 Ld PDIP CD74ACT13M 0 to 70 o C, -40 to 8, 16 Ld SOIC 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. 16 V CC 1 2E 14 S0 13 2I I I I 0 9 2Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST is a Trademark of Fairchild Semiconductor. 1 Copyright 2000, Texas Instruments Incorporated.

2 Functional Diagram 1 1E 6 1I 0 1I 1 4 1I 2 3 1I 3 14 S0 2 S1 10 2I I I I 3 1 2E SEL/MUX SEL/MUX 7 1Y 9 2Y = 8 V CC = 16 TRUTH TABLE SELECT INPUTS DATA INPUTS ENABLE INPUTS S1 S0 ni 0 ni 1 ni 2 ni 3 ne ny X X X X X X H L L L L X X X L L L L H X X X L H L H X L X X L L L H X H X X L H H L X X L X L L H L X X H X L H H H X X X L L L H H X X X H L H Select inputs S1 and S0 are common to both sections. H = High Level, L = Low Level, X = Don t Care, Z = High Impedance. 2

3 Absolute Maximum Ratings DC Supply Voltage, V CC V to 6V DC Input Diode Current, I IK For V I < -0.V or V I > V CC + 0.V ±20mA DC Output Diode Current, I OK For V O < -0.V or V O > V CC + 0.V ±0mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.V or V O < V CC + 0.V ±0mA DC V CC or Ground Current, I CC or I (Note 3) ±100mA Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 10 o C Maximum Lead Temperature (Soldering 10s) o C Operating Conditions Temperature Range, T A o C to 12 o C Supply Voltage Range, V CC (Note 4) AC Types V to.v ACT Types V to.v DC Input or Output Voltage, V I, V O V to V CC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.V to 3V ns (Max) AC Types, 3.6V to.v ns (Max) ACT Types, 4.V to.v ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 3. For up to 4 outputs per device, add ±2mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground.. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS V CC 2 o C -40 o C TO 8 o C - o C TO 12 o C PARAMETER SYMBOL V I (V) I O (ma) (V) MIN MAX MIN MAX MIN MAX UNITS AC TYPES High Level Input Voltage V IH V V V Low Level Input Voltage V IL V V V High Level Output Voltage V OH V IH or V IL V V V V V V V 3

4 DC Electrical Specifications (Continued) PARAMETER Low Level Output Voltage V OL V IH or V IL V V V V V V V Input Leakage Current I I V CC or -. - ±0.1 - ±1 - ±1 µa Quiescent Supply Current MSI ACT TYPES I CC V CC or µa High Level Input Voltage V IH to V. Low Level Input Voltage V IL to V. High Level Output Voltage V OH V IH or V IL V V V V Low Level Output Voltage V OL V IH or V IL V V V V Input Leakage Current I I V CC or -. - ±0.1 - ±1 - ±1 µa Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load I CC I CC V CC or V CC µa - 4. to ma 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 0Ω transmission-line-drive capability at 8 o C, 7Ω at 12 o C. ACT Input Load Table SYMBOL TEST CONDITIONS V CC 2 o C -40 o C TO 8 o C - o C TO 12 o C V I (V) I O (ma) (V) MIN MAX MIN MAX MIN MAX UNITS INPUT UNIT LOAD S0, S1, ni0, ni1 1 ne 0.47 NOTE: Unit load is I CC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 2 o C. 4

5 Switching Specifications Input t r, t f = 3ns, C L = 0pF (Worst Case) -40 o C TO 8 o C - o C TO 12 o C PARAMETER SYMBOL V CC (V) MIN TYP MAX MIN TYP MAX UNITS AC TYPES Propagation Delay, S0, S1, to Y t PLH, t PHL ns ns (Note 9) (Note 10) ns Propagation Delay, ni to Y t PLH, t PHL ns ns ns Propagation Delay, ne to Y t PLH, t PHL ns ns ns Input Capacitance C I pf Power Dissipation Capacitance C PD (Note 11) pf ACT TYPES Propagation Delay, S0, S1, to Y t PLH, t PHL (Note 10) ns Propagation Delay, ni to Y t PLH, t PHL ns Propagation Delay, ne to Y t PLH, t PHL ns Input Capacitance C I pf Power Dissipation Capacitance C PD (Note 11) pf 8. Limits tested at 100% V Min at 3.6V, Max at 3V. 10. V Min at.v, Max at 4.V. 11. C PD is used to determine the dynamic power consumption per multiplexer. AC: P D = V 2 CC f i (C PD + C L ) ACT: P D = V 2 CC f i (C PD + C L ) + V CC I CC where f i = input frequency, C L = output load capacitance, V CC = supply voltage.

6 t r = 3ns DISABLE t PLZ t f = 3ns t PZL INPUT LEVEL 90% 10% : LOW TO OFF TO LOW 0.2V CC VOL ( ) : HIGH TO OFF TO HIGH t PHZ t PZH V OH ( V CC ) 0.8 V CC OTHER INPUTS (TIED HIGH OR LOW) DISABLE S ENABLED DUT WITH THREE- STATE S DISABLED C L 0pF 00Ω R L S ENABLED (t PHZ, t PZH ) OPEN (t PHL, t PLH ) 2 V CC (t PLZ, t PZL ) (OPEN DRAIN) OUT 00Ω R L FOR AC SERIES ONLY: WHEN V CC = 1.V, R L = 1kΩ FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT t r = 3ns t f = 3ns E 90% I OR S 10% Y t PLH t PHL FIGURE 2. PROPAGATION DELAY TIMES AND TEST CIRCUIT R L (NOTE) 00Ω DUT LOAD C L 0pF NOTE: For AC Series Only: When V CC = 1.V, R L = 1kΩ. AC ACT Input Level V CC 3V Input Switching Voltage, 0. V CC 1.V Output Switching Voltage, 0. V CC 0. V CC FIGURE 3. PROPAGATION DELAY TIMES 6

7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated