CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573 High Speed CMOS Logic Octal Transparent Latch, Three-State Output

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ata sheet acquired from Harris Semiconductor SCHS182 November 1997 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 High Speed CMS Logic ctal Transparent Latch, Three-State utput Features

1 ata sheet acquired from Harris Semiconductor SCHS182 November 1997 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 High Speed CMS Logic ctal Transparent Latch, Three-State utput Features escription [ /Title (C74 HC373, C74 HCT37 3, C54 HC573, C74 HC573, C74 HCT57 3) /Sub- Common Latch Enable Control Common Three-State utput Enable Control Buffered Inputs Three-State utputs Bus Line riving Capacity Typical Propagation elay = 12ns at = 5V, C L = 15pF, T A = 25 o C (ata to utput for HC373) Fanout (ver Temperature Range) - Standard utputs LSTTL Loads - Bus river utputs LSTTL Loads Wide perating Temperature Range o C to 125 o C Balanced Propagation elay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V peration - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V peration - irect LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMS Input Compatibility, I l 1µA at V L, V H The Harris C74HC373, C74HCT373, C54HC573, C74HC573, and C74HCT573 are high speed ctal Transparent Latches manufactured with silicon gate CMS technology. They possess the low power consumption of standard CMS integrated circuits, as well as the ability to drive 15 LSTTL devices. The C74HCT373 and C74HCT573 are functionally as well as pin compatible with the standard 74LS373 and 74LS573. The outputs are transparent to the inputs when the latch enable (LE) is high. When the latch enable (LE) goes low the data is latched. The output enable (E) controls the threestate outputs. When the output enable (E) is high the outputs are in the high impedance state. The latch operation is independent to the state of the output enable. The 373 and 573 are identical in function and differ only in their pinout arrangements. rdering Information PART NUMBER TEMP. RANE ( o C) PACKAE PK. N. C54HC573F -55 to Ld CERIP F20.3 C74HC373E -55 to Ld PIP F20.3 C74HCT373E -55 to Ld PIP E20.3 C74HC573E -55 to Ld PIP E20.3 C74HCT573E -55 to Ld PIP E20.3 C74HC373M -55 to Ld SIC M20.3 C74HCT373M -55 to Ld SIC M20.3 C74HC573M -55 to Ld SIC M20.3 C74HCT573M -55 to Ld SIC M20.3 NTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number are available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. CAUTIN: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation File Number

2 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 Pinout C74HC373, C74HCT373 (PIP, SIC) TP VIEW C54HC573, C74HC573, C74HCT573 (PIP, SIC, CERIP) TP VIEW E 1 20 E 1 20 Q Q Q Q Q2 Q Q Q3 Q Q Q Q Q6 Q Q Q LE LE Functional Block iagrams C74HC373, C74HCT373, C74HC573, C74HCT LE E C74HCT LE E TRUTH TABLE UTPUT ENABLE LATCH ENABLE ATA UTPUT L H H H L H L L L L l L L L h H H X X Z NTE: H = High Level, L = Low Level, X = on t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition. 2

3 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 Absolute Maximum Ratings C Supply, V to 7V C Input iode, I IK For V I < -0.5V or V I > + 0.5V ±20mA C utput iode, I K For V < -0.5V or V > + 0.5V ±20mA C rain, per utput, I For -0.5V < V < + 0.5V ±35mA C utput Source or Sink per utput Pin, I For V > -0.5V or V < + 0.5V ±25mA C or round, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 3)....θ JA ( o C/W) θ JA ( o C/W) PIP Package N/A CERIP Package SIC Package N/A Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SIC - Lead Tips nly) perating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V C Input or utput, V I, V V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTIN: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. C Electrical Specifications HC TYPES High Level Input Low Level Input High Level utput CMS Loads High Level utput TTL Loads Low Level utput CMS Loads Low Level utput TTL Loads Input Leakage Quiescent evice SYMBL TEST CNITINS 25 o C -40 o C T 85 o C -55 o C T 125 o C V I (V) I (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V H V L I I I CC UNITS V IH or V V IL V V V V V IH or V V IL V V or or V V ±0.1 - ±1 - ±1 µa µa 3

4 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 C Electrical Specifications (Continued) Three-State Leakage HCT TYPES High Level Input Low Level Input High Level utput CMS Loads High Level utput TTL Loads Low Level utput CMS Loads Low Level utput TTL Loads Input Leakage Quiescent evice Three-State Leakage Additional Quiescent evice Per Input Pin: 1 Unit Load (Note 4) SYMBL - V IL or V IH V = or V IH to 5.5 V IL to 5.5 V H V L I I I CC ±0.5 - ±5 - ±10 µa V V V IH or V V IL V V V IH or V V IL to or - V IL or V IH V = or I CC TEST CNITINS 25 o C -40 o C T 85 o C -55 o C T 125 o C V I (V) I (ma) (V) MIN TYP MAX MIN MAX MIN MAX V V ±0.1 - ±1 - ±1 µa µa to ±0.5 - ±5 - ±10 µa NTE: 4. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LAS UNITS µa HCT373 HCT573 E n LE NTE: Unit Load is I CC limit specified in C Electrical Specifications table, e.g., 360µA max at 25 o C. 4

5 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 Prerequisite For Switching Specifications TEST 25 o C -40 o C T 85 o C -55 o C T 125 o C SYMBL CNITINS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES LE Pulse Width t W ns ns ns Set-up Time ata to LE t SU ns ns ns Hold Time, ata to LE t H ns (573) ns ns Hold Time, ata to LE t H ns (373) ns ns HCT TYPES LE Pulse Width t w ns Set-up Time ata to LE t w ns Hold Time, ata to LE t H ns Switching Specifications Input t r, t f = 6ns SYMBL TEST CNITINS (V) 25 o C -40 o C T 85 o C -55 o C T 125 o C TYP MAX MAX MAX UNITS HC TYPES Propagation elay, ata to Qn (HC/HCT373) t PLH, t PHL C L = 50pF ns ns ns C L = 15pF ns Propagation elay, ata to Qn (HC/HCT573) t PLH, t PHL C L = 50pF ns ns ns Propagation elay, LE to Qn t PLH, t PHL C L = 50pF ns ns ns 5

6 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 Switching Specifications Input t r, t f = 6ns (Continued) SYMBL TEST CNITINS (V) 25 o C -40 o C T 85 o C -55 o C T 125 o C TYP MAX MAX MAX UNITS utput Enabling Time t PZL, t PZH C L = 50pF ns ns ns C L = 15pF ns utput isabling Time t PLZ, t PHZ C L = 50pF ns ns ns C L = 15pF ns utput Transition Time t TLH, t THL C L = 50pF ns ns ns Input Capacitance C I pf Three-State utput Capacitance Power issipation Capacitance (Notes 5, 6) HCT TYPES Propagation elay, ata to Qn (HC/HCT373) Propagation elay, ata to Qn (HC/HCT573) Propagation elay, LE to Qn C pf C P pf t PLH, t PHL C L = 50pF ns C L = 15pF ns t PLH, t PHL C L = 50pF ns C L = 15pF ns t PLH, t PHL C L = 50pF ns utput Enabling Time t PZL, t PZH C L = 50pF ns utput isabling Time t PLZ, t PZH C L = 50pF ns utput Transition Time t TLH, t THL C L = 50pF ns Input Capacitance C I pf Three-State utput Capacitance Power issipation Capacitance (Notes 5, 6) C pf C P pf NTES: 5. C P is used to determine the no-load dynamic power consumption, per latch. 6. P (total power per latch) = V 2 CC f i (C P + C L ) where f i = Input Frequency, C L = utput Load Capacitance, = Supply. 6

7 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 Test Circuits and Waveforms t r C L CLCK t f C L I t WL + t WH = fcl t r C L = 6ns CLCK t f C L = 6ns I t WL + t WH = fcl 2.7V t WL t WH t WL t WH NTE: utputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIURE 1. HC CLCK PULSE RISE AN FALL TIMES AN PULSE WITH NTE: utputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIURE 2. HCT CLCK PULSE RISE AN FALL TIMES AN PULSE WITH t r = 6ns t f = 6ns t r = 6ns t f = 6ns 2.7V 0. t THL t TLH t THL t TLH INVERTIN UTPUT t PHL t PLH INVERTIN UTPUT t PHL t PLH FIURE 3. HC TRANSITIN TIMES AN PRPAATIN ELAY TIMES, CMBINATIN LIC FIURE 4. HCT TRANSITIN TIMES AN PRPAATIN ELAY TIMES, CMBINATIN LIC CLCK t r C L t f C L CLCK t r C L 2.7V 0. t f C L t H(H) t H(L) t H(H) t H(L) ATA t SU(H) t SU(L) ATA t SU(H) t SU(L) UTPUT t TLH t THL UTPUT t TLH t THL t PLH t PHL t PLH t PHL t REM SET, RESET R PRESET t REM SET, RESET R PRESET IC C L 50pF IC C L 50pF FIURE 5. HC SETUP TIMES, HL TIMES, REMVAL TIME, AN PRPAATIN ELAY TIMES FR EE TRIERE SEQUENTIAL LIC CIRCUITS FIURE 6. HCT SETUP TIMES, HL TIMES, REMVAL TIME, AN PRPAATIN ELAY TIMES FR EE TRIERE SEQUENTIAL LIC CIRCUITS 7

8 C74HC373, C74HCT373, C54HC573, C74HC573, C74HCT573 Test Circuits and Waveforms (Continued) 6ns UTPUT ISABLE 6ns t r UTPUT ISABLE 6ns t f ns tplz t PZL t PLZ t PZL UTPUT LW T FF UTPUT LW T FF UTPUT HIH T FF t PHZ t PZH UTPUT HIH T FF t PHZ t PZH UTPUTS ENABLE UTPUTS ISABLE UTPUTS ENABLE UTPUTS ENABLE UTPUTS ISABLE UTPUTS ENABLE FIURE 7. HC THREE-STATE PRPAATIN ELAY WAVEFRM FIURE 8. HCT THREE-STATE PRPAATIN ELAY WAVEFRM THER S TIE HIH R LW UTPUT ISABLE IC WITH THREE- STATE UTPUT UTPUT R L = 1kΩ C L 50pF FR t PLZ AN t PZL FR t PHZ AN t PZH NTE: pen drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is utput R L =1kΩ to, C L = 50pF. FIURE 9. HC AN HCT THREE-STATE PRPAATIN ELAY TEST CIRCUIT 8

9 IMPRTANT NTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATINS USIN SEMICNUCTR PRUCTS MAY INVLVE PTENTIAL RISKS F EATH, PERSNAL INJURY, R SEVERE PRPERTY R ENVIRNMENTAL AMAE ( CRITICAL APPLICATINS ). TI SEMICNUCTR PRUCTS ARE NT ESINE, AUTHRIZE, R WARRANTE T BE SUITABLE FR USE IN LIFE-SUPPRT EVICES R SYSTEMS R THER CRITICAL APPLICATINS. INCLUSIN F TI PRUCTS IN SUCH APPLICATINS IS UNERST T BE FULLY AT THE CUSTMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated

CD74HC109, CD74HCT109

Data sheet acquired from Harris Semiconductor SCHS140 March 1998 CD74HC109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject Dual J- Fliplop