CD74HC221, CD74HCT221

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1 November 997 SEMIONDUTO D74H22, D74HT22 High Speed MOS Logic Dual Monostable Multivibrator with eset Features Description Overriding ESET Terminates Output Pulse Triggering from the Leading or Trailing Edge and Buffered Outputs Separate esets Wide ange of Output-Pulse Widths Schmitt Trigger on B Inputs Fanout (Over Temperature ange) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature ange o to 25 o Balanced Propagation Delay and Transition Times Significant Power eduction ompared to LSTTL Logic Is H Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HT Types - 4.5V to V Operation - Direct LSTTL Input Logic ompatibility, V IL = 0.8V (Max), V IH = 2V (Min) - MOS Input ompatibility, I l µa at V OL, V OH The Harris D74H22, and H74HT22 are dual monostable multivibrators with reset. An external resistor ( X ) and an external capacitor ( X ) control the timing and the accuracy for the circuit. Adjustment of X and X provides a wide range of output pulse widths from the and terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A and B. The output pulse can be terminated by a LOW level on the eset () pin. Trailing Edge triggering (A) and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the I is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, X, is typically 500Ω. The minimum value of external capacitance, X, is 0pF. The calculation for the pulse width is t W = 0.7 X X at = 4.5V. Ordering Information PAT NUMBE TEMP. ANGE ( o ) PAKAGE PKG. NO. D74H22E -55 to 25 6 Ld PDIP E6.3 D74HT22E -55 to 25 6 Ld PDIP E6.3 D74H22M -55 to 25 6 Ld SOI M6.5 D74HT22M -55 to 25 6 Ld SOI M6.5 NOTES:. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die are available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout (PDIP, SOI) TOP VIEW A 6 B 2 5 X X 3 4 X X X X 7 0 2B 8 9 2A AUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I Handling Procedures. opyright Harris orporation 997 File Number 670.

2 Functional Diagram X X 4 5 A B 2 X X X MONO A B 0 MONO X 2 X X X 2 X TUTH TABLE INPUTS OUTPUTS A B H X H L H X L H L H L H H H X X L L H L H (Note 3) (Note 3) NOTE: H = High Level, L = Low Level, X = Irrelevant, = Transition from Low to High Level, = Transition from High to Low Level, = One High Level Pulse, = One Low Level Pulse 3. For this combination the reset input must be low and the following sequence must be used: pin (or 9) must be set high or pin 2 (or 0) set low; then pin (or 9) must be low and pin 2 (or 0) set high. Now the reset input goes from low-to-high and the device will be triggered. 2

3 Logic Diagram P 6 N X A (9) B 2 (0) 3 () P ESET FF D P OP AMP (7) S X X M M PP MIO VOLTAGE 3 X MASK FF S MAIN FF 4 N PULLDOWN FF D N 4 (6) X 8 4 (2) (3) OP AMP 3

4 Absolute Maximum atings D Supply, V to 7V D Input Diode urrent, I IK For V I < -0.5V or V I > + 0.5V ±20mA D Output Diode urrent, I OK For V O < -0.5V or V O > + 0.5V ±20mA D Drain urrent, per Output, I O For -0.5V < V O < + 0.5V ±25mA D Output Source or Sink urrent per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA D or Ground urrent, I ±50mA Thermal Information Thermal esistance (Typical, Note 4) θ JA ( o /W) θ J ( o /W) PDIP Package N/A SOI Package N/A Maximum Junction Temperature (Plastic Package) o Maximum Storage Temperature ange o to 50 o Maximum Lead Temperature (Soldering 0s) o (SOI - Lead Tips Only) Operating onditions Temperature ange, T A o to 25 o Supply ange, H Types V to 6V HT Types V to V D Input or Output, V I, V O V to Input ise and Fall Time, t r, t f on Inputs A and 2V ns (Max) 4.5V ns (Max) 6V ns (Max) Input ise and Fall Time, t r, t f on Input B 2V Unlimited ns (Max) 4.5V Unlimited ns (Max) 6V Unlimited ns (Max) AUTION: Stresses above those listed in Absolute Maximum atings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θ JA is measured with the component mounted on an evaluation P board in free air. D Electrical Specifications PAAMETE H TYPES High Level Input Low Level Input High Level Output MOS Loads High Level Output TTL Loads Low Level Output MOS Loads Low Level Output TTL Loads SYMBOL TEST ONDITIONS 25 o -40 o TO 85 o -55 o TO 25 o V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V V V V V OL V IH or V IL V V V V V V 4

5 D Electrical Specifications (ontinued) PAAMETE Input Leakage urrent uiescent Device urrent HT TYPES High Level Input Low Level Input High Level Output MOS Loads High Level Output TTL Loads Low Level Output MOS Loads Low Level Output TTL Loads Input Leakage urrent uiescent Device urrent Additional uiescent Device urrent Per Input Pin: Unit Load SYMBOL I I I or or V IH to V IL to ±0. - ± - ± µa µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I I TEST ONDITIONS 25 o -40 o TO 85 o -55 o TO 25 o V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or V 0 - ±0. - ± - ± µa µa to NOTE: For dual-supply systems theoretical worst case (V I = 2.4V, = V) specification is.8ma. HT Input Loading Table µa INPUT UNIT LOADS All Inputs 0.3 NOTE: Unit Load is I limit specified in D Electrical Table, e.g., 360µA max at 25 o. Prerequisite For Switching Function 25 o -40 o TO 85 o -55 o TO 25 o PAAMETE SYMBOL (V) MIN TYP MAX MIN MAX MIN MAX H TYPES t WL ns A ns ns t WH ns B ns ns 5

6 Prerequisite For Switching Function (ontinued) eset ecovery Time to A or B Output Pulse Width or X = 0.µF X = 0kΩ Output Pulse Width or X = 28pF, X = 2kΩ t WL ns ns ns t SU ns ns ns t W µs t W ns X = 000pF, X = 2kΩ t W µs X = 000pF, X = 0kΩ t W µs HT TYPES A t WL ns B eset ecovery Time to A or B PAAMETE SYMBOL (V) Output Pulse Width or X = 0.µF X = 0kΩ Output Pulse Width or X = 28pF, X = 2kΩ t WH ns t WL ns t SU ns t W µs t W ns X = 000pF, X = 2kΩ t W µs X = 000pF, X = 0kΩ t W µs Switching Specifications Input t r, t f = 6ns 25 o -40 o TO 85 o -55 o TO 25 o MIN TYP MAX MIN MAX MIN MAX PAAMETE SYMBOL TEST ONDITIONS (V) 25 o -40 o TO 85 o -55 o TO 25 o MIN TYP MAX MIN MAX MIN MAX H TYPES Trigger A, B, to t PLH L = 50pF ns L = 50pF ns L = 50pF ns L = 5pF ns Trigger A, B, to t PHL L = 50pF ns L = 50pF ns L = 50pF ns L = 5pF ns 6

7 Switching Specifications Input t r, t f = 6ns (ontinued) PAAMETE SYMBOL TEST ONDITIONS (V) 25 o -40 o TO 85 o -55 o TO 25 o MIN TYP MAX MIN MAX MIN MAX to t PLH L = 50pF ns ns ns to t PHL L = 50pF ns ns ns Output Transition Time t TLH, t THL L = 50pF ns ns ns Input apacitance IN pf Pulse Width Match Between ircuits in the Same Package X = 000pF, X = 0kΩ to - ± % Power Dissipation apacitance (Notes 5, 6) HT TYPES Trigger A, B, to Trigger A, B, to to to PD pf t PLH L = 50pF ns L = 5pF ns t PHL L = 50pF ns L = 5pF ns t PLH L = 50pF ns t PHL L = 50pF ns Output Transition Time t TLH, t THL L = 50pF ns ns ns Input apacitance IN pf Pulse Width Match Between ircuits in the Same Package X = 000pF, X = 0kΩ to - ± % Power Dissipation apacitance (Notes 5, 6) PD pf NOTES: 5. PD is used to determine the dynamic power consumption, per multivibrator. 6. P D = ( PD + L ) V 2 f i + Σ where f i = input frequency, f o = output frequency, L = output load capacitance, = supply voltage. 7

8 Test ircuits and Waveforms t r L LOK t f L I t WL + t WH = fl 90% 50% 50% 50% 0% 0% t r L = 6ns LOK t f L = 6ns I t WL + t WH = fl 3V 2.7V.3V.3V.3V 0.3V 0.3V t WL t WH t WL t WH NOTE: Outputs should be switching from 0% to 90% in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGUE. H LOK PULSE ISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from 0% to 90% in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGUE 2. HT LOK PULSE ISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 50% 0% INPUT 2.7V.3V 0.3V 3V t THL t TLH t THL t TLH INVETING OUTPUT t PHL t PLH 90% 50% 0% INVETING OUTPUT t PHL t PLH 90%.3V 0% FIGUE 3. H TANSITION TIMES AND POPAGATION DELAY TIMES, OMBINATION LOGI FIGUE 4. HT TANSITION TIMES AND POPAGATION DELAY TIMES, OMBINATION LOGI 8

9 Typical Performance urves 685 X = 0K X = 0K = 5V T A = 25 o t W, PULSE WIDTH (µs) X = µf K FATO HT T A, AMBIENT TEMPEATUE ( o ) , SUPPLY VOLTAGE (V) FIGUE 5. H/HT22 OUTPUT PULSE WIDTH vs TEMPEATUE FIGUE 6. H/HT22 K FATO vs SUPPLY VOLTAGE = 2V = 4.5V t W, PULSE WIDTH (µs) X = 00K X = 50K X = 0K X = 2K t W, PULSE WIDTH (µs) X = 00K X = 50K X = 0K X = 2K X, TIMING APAITANE (pf) X, TIMING APAITANE (pf) FIGUE 7. H22 OUTPUT PULSE WIDTH vs X FIGUE 8. H/HT22 OUTPUT PULSE WIDTH vs X = 6V t W, PULSE WIDTH (µs) X = 00K X = 50K X = 0K X = 2K X, TIMING APAITANE (pf) FIGUE 9. H22 OUTPUT PULSE WIDTH vs X 9

CD54/74HC32, CD54/74HCT32

CD54/74HC32, CD54/74HCT32 Data sheet acquired from Harris Semiconductor SCHS7A September 997 - Revised May 000 CD/7HC, CD/7HCT High Speed CMOS Logic Quad -Input OR Gate [ /Title (CD HCT, CD7 HC, CD7 HCT ) /Subject High Features