X9259. Quad Digitally-Controlled (XDCP TM ) Potentiometers. Single Supply / Low Power / 256-tap / 2-Wire bus

Transcription

1 PPLIION NOE ND DEVELOPMEN YEM V I L B L E N99 N115 N124 N133 N134 N135 ingle upply / Low Power / 256-tap / 2-ire bus X9259 Quad Digitally-ontrolled (XDP M ) Potentiometers FEUE Four separate potentiometers in one package 256 resistor taps 0.4% resolution 2-ire erial Interface for write, read, and transfer operations of the potentiometer iper esistance: 100Ω V = 5V 4 Non-volatile Data egisters for Each Potentiometer Non-volatile torage of Multiple iper Positions tandby urrent < 5µ Max V : 2.7V to 5.5V Operation 50Ω, 100Ω versions of otal esistance Endurance: 100,000 Data hanges per Bit per egister 100 yr. Data etention ingle upply Version of X Lead OI, 24-Lead OP, 24-Lead P (hip cale Package) Low Power MO DEIPION he X9259 integrates four digitally controlled potentiometers (XDP) on a monolithic MO integrated circuit. he digitally controlled potentiometers are implemented with a combination of resistor elements and MO switches. he position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile iper ounter egister () and four non-volatile Data egisters that can be directly written to and read by the user. he content of the controls the position of the wiper. t power-up, the device recalls the content of the default Data egisters of each DP (D00, D10, D20, and D30) to the corresponding. he XDP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNIONL DIGM V H0 H1 H2 H PI Interface POE UP, INEFE ONOL ND U 0 D00 D01 D02 D03 DP0 1 D10 D11 D12 D13 DP1 2 D20 D21 D22 D23 DP2 3 D30 D31 D32 D33 DP3 D L V P 0 L0 1 L1 2 L2 3 L3 EV /10/04 haracteristics subject to change without notice. 1 of 25

2 ODEING INFO Ordering Number Potentiomenter Organization Package Operating emperature ange V Limits X9259U24 50kΩ 24-lead OI 0 to 70 5V±10% X9259U kΩ 24-lead OI 0 to to 5.5V X9259U24I 50kΩ 24-lead OI -40 to +85 5V±10% X9259U24I kΩ 24-lead OI -40 to to 5.5V X9259UV24 50kΩ 24-lead OP 0 to 70 5V±10% X9259UV kΩ 24-lead OP 0 to to 5.5V X9259UV24I 50kΩ 24-lead OP -40 to +85 5V±10% X9259UV24I kΩ 24-lead OP -40 to to 5.5V X9259UB24 50kΩ 24-lead P 0 to 70 5V±10% X9259UB kΩ 24-lead P 0 to to 5.5V X9259UB24I 50kΩ 24-lead P -40 to +85 5V±10% X9259UB24I kΩ 24-lead P -40 to to 5.5V X kΩ 24-lead OI 0 to 70 5V±10% X kΩ 24-lead OI 0 to to 5.5V X925924I 100kΩ 24-lead OI -40 to +85 5V±10% X925924I kΩ 24-lead OI -40 to to 5.5V X9259V24 100kΩ 24-lead OP 0 to 70 5V±10% X9259V kΩ 24-lead OP 0 to to 5.5V X9259V24I 100kΩ 24-lead OP -40 to +85 5V±10% X9259V24I kΩ 24-lead OP -40 to to 5.5V X9259B24 100kΩ 24-lead P 0 to 70 5V±10% X9259B kΩ 24-lead P 0 to to 5.5V X9259B24I 100kΩ 24-lead P -40 to +85 5V±10% X9259B24I kΩ 24-lead P -40 to to 5.5V EV /10/04 haracteristics subject to change without notice. 2 of 25

3 IUI LEVEL PPLIION Vary the gain of a voltage amplifier Provide programmable dc reference voltages for comparators and detectors ontrol the volume in audio circuits rim out the offset voltage error in a voltage amplifier circuit et the output voltage of a voltage regulator rim the resistance in heatstone bridge circuits ontrol the gain, characteristic frequency and Q-factor in filter circuits et the scale factor and zero point in sensor signal conditioning circuits Vary the frequency and duty cycle of timer Is Vary the dc biasing of a pin diode attenuator in F circuits Provide a control variable (I, V, or ) in feedback circuits YEM LEVEL PPLIION djust the contrast in LD displays ontrol the power level of LED transmitters in communication systems et and regulate the D biasing point in an F power amplifier in wireless systems ontrol the gain in audio and home entertainment systems Provide the variable D bias for tuners in F wireless systems et the operating points in temperature control systems ontrol the operating point for sensors in industrial systems rim offset and gain errors in artificial intelligent systems EV /10/04 haracteristics subject to change without notice. 3 of 25

4 PIN ONFIGUION DN 0 3 OI/OP L L2 1 0 P L1 H3 L3 N V X H2 2 N V B L0 V P H0 D H1 1 V L0 H H1 D N H3 H2 N 0 2 P L1 1 D E F L3 3 DN 0 3 L 2 L2 op View Bumps Down PIN IGNMEN Pin (OI/OP) Pin (P) ymbol Function 2 F2 0 Device ddress for 2-ire bus. (ee Note 1) 3 F1 3 iper erminal of DP3 4 D2 H3 High erminal of DP3 5 E1 L3 Low erminal of DP3 6 E2 N1 Must be left unconnected 7 1 V ystem upply Voltage 8 B1 L0 Low erminal of DP0 9 2 H0 High erminal of DP iper erminal of DP Device ddress for 2-ire bus. (ee Note 1) 12 B2 P Hardware rite Protect ctive Low 13 B3 D erial Data Input/Output for 2-ire bus Device ddress for 2-ire bus. (ee Note 1) 15 4 L1 Low erminal of DP H1 High erminal of DP1 17 B4 1 iper erminal of DP V ystem Ground 20 E4 2 ipererminal of DP2 21 D3 H2 High erminal of DP2 22 F4 L2 Low erminal of DP2 23 F3 L erial lock for 2-ire bus. 24 E3 3 Device ddress for 2-ire bus. (ee Note 1) 6, 19 D1, D4 N No onnect 1 E2 DN Do Not onnect Note 1: 0-3 Device address pins must be tied to a logic level. EV /10/04 haracteristics subject to change without notice. 4 of 25

5 PIN DEIPION Bus Interface Pins EIL D INPU/OUPU (D) he D is a bidirectional serial data input/output pin for a 2-ire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-ire master at the rising edge of the serial clock L, and it shifts out data after each falling edge of the serial clock L. It is an open drain output and may be wire-oed with any number of open drain or open collector outputs. n open drain output requires the use of a pull-up resistor. EIL LO (L) his input is used by 2-ire master to supply 2-ire serial clock to the X9259. DEVIE DDE (3 0) he ddress inputs are used to set the least significant 4 bits of the 8-bit slave address. match in the slave address serial data stream must be made with the ddress input in order to initiate communication with the X9259. maximum of 16 devices may occupy the 2-ire serial bus. Device pins 3-0 must be tie to a logic level which specify the external address of the device, see Figures 3, 4, and 5. Potentiometer Pins H, L he H and L pins are equivalent to the terminal connections on a mechanical potentiometer. ince there are 4 potentiometers, there are 4 sets of H and L such that H0 and L0 are the terminals of DP0 and so on. he wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. ince there are 4 potentiometers, there are 4 sets of such that 0 is the terminal of DP0 and so on. Bias upply Pins YEM UPPLY VOLGE (V ) ND UPPLY GOUND (V ) he V pin is the system supply voltage. he V pin is the system ground. Other Pins NO ONNE No connect pins should be left open. his pins are used for Xicor manufacturing and testing purposes. HDE IE POE INPU (P) he P pin when LO prevents non-volatile writes to the Data egisters. EV /10/04 haracteristics subject to change without notice. 5 of 25

6 PINIPLE OF OPEION he X9259 is an integrated circuit incorporating four DPs and their associated registers and counters, and the serial interface providing direct communication between a host and the potentiometers. DP Description Each DP is implemented with a combination of resistor elements and MO switches. he physical ends of each DP are equivalent to the fixed terminals of a mechanical potentiometer ( H and L pins). he pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. he position of the wiper terminal within the DP is controlled by an 8-bit volatile iper ounter egister (). Power Up and Down ecommendations. here are no restrictions on the power-up or powerdown conditions of V and the voltages applied to the potentiometer pins provided that V is always more positive than or equal to V H, V L, and V, i.e., V V H, V L, V. he V ramp rate specification is always in effect. Figure 1. Detailed Potentiometer Block Diagram One of Four Potentiometers #: 0, 1, 2, or 3 H EIL D PH FOM INEFE IUIY EIL BU INPU D#0 D#1 D#2 8 8 D#3 PLLEL BU INPU IPE OUNE EGIE (#) OUNE DEODE DP OE IF = 00[H] then is closest to L IF = FF[H] then is closest to H UP/DN MODIFIED UP/DN L IN/DE LOGI L EV /10/04 haracteristics subject to change without notice. 6 of 25

7 iper ounter egister () he X9259 contains four iper ounter egisters, one for each potentiometer. he iper ounter egister can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. he contents of the can be altered in four ways: it may be written directly by the host via the rite iper ounter egister instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XF Data egister instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (see Instruction section for more details). Finally, it is loaded with the contents of its data register zero (D#0) upon power-up. (ee Figure 1.) Data egisters (D) Each of the four DPs has four 8-bit non-volatile Data egisters. hese can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated iper ounter egister. ll operations changing data in one of the data registers is a non-volatile operation and takes a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data egisters can be used as regular memory locations for system parameters or user preference data. Bit [7:0] are used to store one of the 256 wiper positions (0~255). he iper ounter egister is a volatile register; that is, its contents are lost when the X9259 is powereddown. lthough the register is automatically loaded with the value in D#0 upon power-up, this may be different from the value present at power-down. Powerup guidelines are recommended to ensure proper loadings of the D#0 value into the # (ee Design onsiderations ection). able 1. iper counter egister, (8-bit), [7:0]: Used to store the current wiper position (Volatile) (MB) (LB) able 2. Data egister, D (8-bit), Bit [7:0]: Used to store wiper positions or data (Non-volatile). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (MB) (LB) EV /10/04 haracteristics subject to change without notice. 7 of 25

8 EIL INEFE he X9259 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master always initiates data transfers and provide the clock for both transmit and receive operations. herefore, the X9259 operates as a slave device in all applications. ll 2-wire interface operations must begin with a, followed by an Identification Byte, that selects the X9259. ll communication over the 2-wire interface is conducted by sending the MB of each byte of data first. lock and Data onventions Data states on the D line can change only during L LO periods. D state changes during L HIGH are reserved for indicating and OP conditions. ee Figure 2. On power up of the X9259 the D pin is in the input mode. ondition ll commands to the X9259 are preceded by the start condition, which is a HIGH to LO transition of D while L is HIGH. he X9259 continuously monitors the D and L lines for the condition and does not respond to any command until this condition is met. ee Figure 2. OP ondition ll communications must be terminated by a OP condition, which is a LO to HIGH transition of D while L is HIGH. ee Figure 2. he OP condition is also used to place the device into the tandby Power mode after a ead sequence. OP condition can only be issued after the transmitting device has released the bus. cknowledge n, cknowledge, is a software convention used to indicate a successful data transfer. he transmitting device, either master or slave, releases the D bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the D line LO to acknowledge the reception of the eight bits of data. ee Figure 3. he X9259 responds with an after recognition of a condition followed by a valid Identification Byte, and once again after successful receipt of an Instruction Byte. he X9259 also responds with an after receiving a Data Byte after a rite Instruction. valid Identification Byte contains the Device ype Identifier 0101, as the four MBs, and the Device ddress bits matching the logic states of pins 3, 2, 1, and 0, as the four LBs. ee Figure 4. In the ead mode, the device transmits eight bits of data, releases the D line, and then monitors the line for an. he device continues transmitting data if an is detected. he device terminates further data transmissions if an is not detected. he master must then issue a OP condition to place the device into a known state. During the internal non-volatile rite operation, the X9259 ignores the inputs at D and L, and does not issue an after Identification bytes. EV /10/04 haracteristics subject to change without notice. 8 of 25

9 Figure 2. Valid Data hanges, tart, and top onditions L D D D D OP BLE HNGE BLE Figure 3. cknowledge esponse from eceiver L from Master D Output from ransmitter D Output from eceiver Identification Byte he first byte sent to the X9259 from the host is called the Identification Byte. he most significant four bits are a Device ype Identifier, ID[3:0] bits, which must be efer to able 3. Only the device which lave ddress matches the incoming device address sent by the master executes the instruction. he 3-0 inputs can be actively driven by MO input signals or tied to V or V. INUION BYE (I) he next byte sent to the X9259 contains the instruction and register pointer information. he four most significant bits are used provide the instruction opcode I [3:0]. he B and bits point to one of the four data registers of each associated XDP. he least two significant bits point to one of four iper ounter egisters or DPs. he format is shown in able 4. Data egister election #: 0, 1, 2, or 3 egister B D#0 0 0 D#1 0 1 D#2 1 0 D#3 1 1 he least significant four bits of the Identification Byte are the lave ddress bits, D[3:0]. o access the X9259, these four bits must match the logic values of pins 3, 2, 1, and 0. EV /10/04 haracteristics subject to change without notice. 9 of 25

10 able 3. Identification Byte Format Device ype Identifier lave ddress ID3 ID2 ID1 ID Logic value of pins 3, 2, 1, and 0 (MB) (LB) able 4. Instruction Byte Format Instruction egister DP election Opcode election ( election) I3 I2 I1 I0 B P1 P0 (MB) (LB) able 5. Instruction et Instruction ead iper ounter egister Note: 1/0 = data is one or zero Instruction et I3 I2 I1 I0 B P1 P0 Operation /0 1/0 ead the contents of the iper ounter egister pointed to by P1-P0 rite iper ounter egister /0 1/0 rite new value to the iper ounter egister pointed to by P1-P0 ead Data egister /0 1/0 1/0 1/0 ead the contents of the Data egister pointed to by P1-P0 and B- rite Data egister /0 1/0 1/0 1/0 rite new value to the Data egister pointed to by P1-P0 and B- XF Data egister to iper ounter egister XF iper ounter egister to Data egister Global XF Data egisters to iper ounter egisters Global XF iper ounter egisters to Data egister Increment/Decrement iper ounter egister /0 1/0 1/0 1/0 ransfer the contents of the Data egister pointed to by P1-P0 and B- to its associated iper ounter egister /0 1/0 1/0 1/0 ransfer the contents of the iper ounter egister pointed to by P1-P0 to the Data egister pointed to by B /0 1/0 0 0 ransfer the contents of the Data egisters pointed to by B- of all four pots to their respective iper ounter egisters /0 1/0 0 0 ransfer the contents of both iper ounter egisters to their respective data egisters pointed to by B- of all four DPs /0 1/0 Enable Increment/decrement of the ontrol Latch pointed to by P1-P0 EV /10/04 haracteristics subject to change without notice. 10 of 25

11 Instructions Four of the nine instructions are three bytes in length. hese instructions are: ead iper ounter egister read the current wiper position of the selected potentiometer, rite iper ounter egister change current wiper position of the selected potentiometer, ead Data egister read the contents of the selected Data egister; rite Data egister write a new value to the selected Data egister. he basic sequence of the three byte instructions is illustrated in Figure 5. hese three-byte instructions exchange data between the and one of the Data egisters. transfer from a Data egister to a is essentially a write to a static M, with the static M controlling the wiper position. he response of the wiper to this action is delayed by t L. transfer from the (current wiper position), to a Data egister is a write to non-volatile memory and takes a minimum of t to complete. he transfer can occur between one of the four potentiometer s, and one of its associated registers, Ds; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete. hese instructions transfer data between the host and the X9259; either between the host and one of the data registers or directly between the host and the iper ounter egister. hese instructions are: XF Data egister to iper ounter egister his transfers the contents of one specified Data egister to the associated iper ounter egister. XF iper ounter egister to Data egister his transfers the contents of the specified iper ounter egister to the specified associated Data egister. Global XF Data egister to iper ounter egister his transfers the contents of all specified Data egisters to the associated iper ounter egisters. Global XF iper ounter egister to Data egister his transfers the contents of all iper ounter egisters to the specified associated Data egisters. INEMEN/DEEMEN OMMND he final command is Increment/Decrement (Figure 6 and 7). he Increment/Decrement command is different from the other commands. Once the command is issued and the X9259 has responded with an cknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each L clock pulse (t HIGH ) while D is HIGH, the selected wiper moves one wiper position towards the H terminal. imilarly, for each L clock pulse while D is LO, the selected wiper moves one resistor wiper position towards the L terminal. ee Instruction format for more details. EV /10/04 haracteristics subject to change without notice. 11 of 25

12 Figure 4. wo-byte Instruction equence L D ID3 ID2 ID1 ID0 3 Device ID I3 I2 I1 I0 B P1 P0 External ddress Instruction Opcode egister ddress DP/ ddress O P Figure 5. hree-byte Instruction equence 2-ire Interface L D ID3 ID2 ID1ID I3 I2 I1 I0 B P1 P0 Device ID External Instruction ddress Opcode egister Pot/ ddress ddress D7 D6 D5 D4 D3 D2 D1 D0 Data for [7:0] or D[7:0] O P Figure 6. Increment/Decrement Instruction equence 2-ire Interface L D ID3 ID2 ID1 ID I3 I2 I1 I0 Device ID External Instruction ddress Opcode B P1 P0 egister ddress Pot/ ddress I N 1 I N2 I Nn D E1 D En O P Figure 7. Increment/Decrement iming pec IN/DE MD Issued t ID L D Voltage Out EV /10/04 haracteristics subject to change without notice. 12 of 25

13 INUION FOM ead iper ounter egister () Device ype Identifier Device ddresses Instruction Opcode D/ ddresses P1 P0 iper Position (ent by X9259 on D) M O P rite iper ounter egister () Device ype Identifier Device ddresses Instruction Opcode D/ ddresses P1 P0 iper Position (ent by Master on D) O P ead Data egister (D) Device ype Identifier Device ddresses Instruction Opcode D/ ddresses B P1 P0 iper Position (ent by X9259 on D) M O P rite Data egister (D) Device ype Identifier Device ddresses Instruction Opcode D/ ddresses B P1 P0 iper Position (ent by Master on D) O P HIGH-VOLGE IE YLE Global XF Data egister (D) to iper ounter egister () Device ype Identifier Device ddresses Instruction Opcode D/ ddresses B 0 0 O P Notes: (1) M / : stands for the acknowledge sent by the Master/lave. (2) 3 ~ 0 : stands for the device addresses sent by the master. (3) X : indicates that it is a 0 for testing purpose but physically it is a don t care condition. (4) I : stands for the increment operation, D held high during active L phase (high). (5) D : stands for the decrement operation, D held low during active L phase (high). EV /10/04 haracteristics subject to change without notice. 13 of 25

14 Global XF iper ounter egister () to Data egister (D) Device ype Identifier Device ddresses Instruction Opcode D/ ddresses B 0 0 O P HIGH-VOLGE IE YLE ransfer iper ounter egister () to Data egister (D) Device ype Identifier Device ddresses Instruction Opcode D/ ddresses B P1 P0 O P HIGH-VOLGE IE YLE ransfer Data egister (D) to iper ounter egister () Device ype Identifier Device ddresses Instruction Opcode D/ ddresses B P1 P0 O P Increment/Decrement iper ounter egister () Device ype Identifier Device ddresses Instruction Opcode D/ ddresses Increment/Decrement (ent by Master on D) P1 P0 I/D I/D.... I/D I/D O P Notes: (1) M / : stands for the acknowledge sent by the Master/lave. (2) 3 ~ 0 : stands for the device addresses sent by the master. (3) X : indicates that it is a 0 for testing purpose but physically it is a don t care condition. (4) I : stands for the increment operation, D held high during active L phase (high). (5) D : stands for the decrement operation, D held low during active L phase (high). EV /10/04 haracteristics subject to change without notice. 14 of 25

15 BOLUE MXIMUM ING emperature under bias to +135 torage temperature to +150 Voltage on L, D, any address input, V with respect to V... 1V to +7V V = (V H V L ) V Lead temperature (soldering, 10 seconds) I (10 seconds)... ±6m OMMEN tresses above those listed under bsolute Maximum atings may cause permanent damage to the device. his is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EOMMENDED OPEING ONDIION emp Min. Max. ommercial Industrial Device upply Voltage (V ) (4) Limits X9259 5V ±10% X V to 5.5V NLOG HEII (Over recommended industrial (2.7V) operating conditions unless otherwise stated.) ymbol Parameter Limits Min. yp. Max. Units est onditions OL End to End esistance 100 kω version OL End to End esistance 50 kω U version End to End esistance ±20 % olerance Power ating 50 m 25, each pot I iper urrent ±3 m iper esistance 300 Ω V(V I = V = 3V OL 150 Ω V(V I = V = 5V OL V EM Voltage on any H or L Pin V V V V = 0V Noise -120 db/ Hz ef: 1V esolution 0.4 % bsolute Linearity (1) MI (3) (5) w(n)(actual) w(n)(expected) elative Linearity (2) MI (3) w(n + 1) [ w(n) + MI ] (5) emperature oefficient of OL ±300 ppm/ atiometric emp. oefficient ppm/ H / L / Potentiometer apacitances 10/10/25 pf ee Macro model Notes: (1) bsolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) elative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = O / 255 or ( H L ) / 255, single pot (4) During power up V > V H, V L, and V. (5) n = 0, 1, 2,,255; m =0, 1, 2,, 254. EV /10/04 haracteristics subject to change without notice. 15 of 25

16 D.. OPEING HEII (Over the recommended operating conditions unless otherwise specified.) ymbol I 1 I 2 ENDUNE ND D EENION PINE POE-UP IMING Parameter V supply current (active) V supply current (non-volatile write).. E ONDIION Limits Min. yp. Max. Units est onditions 3 m f L = 400Hz; V = +6V; D = Open; (for 2-ire, ctive, ead and 5 m f L = 400Hz; V = +6V; D = Open; (for 2-ire, ctive, Non-volatile rite tate only) I B V current (standby) 5 µ V = +6V; V IN = V or V ; D = V ; (for 2-ire, tandby tate only) I LI Input leakage current 10 µ V IN = V to V I LO Output leakage current 10 µ V OU = V to V V IH Input HIGH voltage V x 0.7 V + 1 V V IL Input LO voltage 1 V x 0.3 V V OL Output LO voltage 0.4 V I OL = 3m V OH Output HIGH voltage V V I OH = -1m, V +3V V OH Output HIGH voltage V V I OH = -0.4m, V +3V Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years ymbol est Max. Units est onditions (6) IN/OU Input / Output capacitance (D) 8 pf V OU = 0V (6) IN Input capacitance (L, P, 2, 1 and 0) 6 pf V IN = 0V ymbol Parameter Min. Max. Units t r V (6) V Power-up rate V/ms t (7) PU Power-up to initiation of read operation 1 ms t (7) PU Power-up to initiation of write operation 50 ms Input Pulse Levels V x 0.1 to V x 0.9 Input rise and fall times 10ns Input and output timing level V x 0.5 Notes: (6) his parameter is not 100% tested (7) t PU and t PU are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued. hese parameters are periodically sampled and not 100% tested. EV /10/04 haracteristics subject to change without notice. 16 of 25

17 EQUIVLEN.. LOD IUI 5V PIE Macromodel 1533Ω OL D pin 100pF H L 10pF 25pF L 10pF L IMING ymbol Parameter Min. Max. Units f L lock Frequency 400 khz t Y lock ycle ime 2500 ns t HIGH lock High ime 600 ns t LO lock Low ime 1300 ns t U: tart etup ime 600 ns t HD: tart Hold ime 600 ns t U:O top etup ime 600 ns t U:D D Data Input etup ime 100 ns t HD:D D Data Input Hold ime 30 ns t L and D ise ime 300 ns t F L and D Fall ime 300 ns t L Low to D Data Output Valid ime 0.9 µs t DH D Data Output Hold ime 0 ns I Noise uppression ime onstant at L and D inputs 50 ns t BUF Bus Free ime (Prior to ny ransmission) 1200 ns t U:P 0, 1 etup ime 0 ns t HD:P 0, 1 Hold ime 0 ns EV /10/04 haracteristics subject to change without notice. 17 of 25

18 HIGH-VOLGE IE YLE IMING ymbol Parameter yp. Max. Units t High-voltage write cycle time (store instructions) 5 10 ms XDP IMING ymbol Parameter Min. Max. Units t PO iper response time after the third (last) power supply is stable 5 10 µs t L iper response time after instruction issued (all load instructions) 5 10 µs YMBOL BLE VEFOM INPU OUPU Must be steady May change from Low to High May change from High to Low Don t are: hanges llowed N/ ill be steady ill change from Low to High ill change from High to Low hanging: tate Not nown enter Line is High Impedance. EV /10/04 haracteristics subject to change without notice. 18 of 25

19 IMING DIGM tart and top iming () (OP) t t F L t U: t HD: t U:O t t F D Input iming t Y t HIGH L t LO D t U:D t HD:D t BUF Output iming L D t t DH EV /10/04 haracteristics subject to change without notice. 19 of 25

20 XDP iming (for ll Load Instructions) (OP) L D LB t L Vx rite Protect and Device ddress Pins iming () (OP) L D... (ny Instruction) t U:P t HD:P P 0, 1 EV /10/04 haracteristics subject to change without notice. 20 of 25

21 PPLIION INFOMION Basic onfigurations of Electronic Potentiometers V +V I hree terminal Potentiometer; Variable voltage divider wo terminal Variable esistor; Variable current pplication ircuits Noninverting mplifier Voltage egulator V + V O V IN 317 V O (EG) 1 2 I adj 1 2 V O = (1+ 2 / 1 )V V O (EG) = 1.25V (1+ 2 / 1 )+I adj 2 Offset Voltage djustment omparator with Hysterisis 1 V 100Ω 10Ω + 2 L072 V O V } 1 + } 2 V O 10Ω 10Ω V UL = { 1 /( )} V O (max) L L = { 1 /( )} V O (min) +12V -12V EV /10/04 haracteristics subject to change without notice. 21 of 25

22 pplication ircuits (continued) ttenuator Filter V + V V O V O = 2 = 3 = 4 = 10kΩ 1 2 V O = G V -1/2 G +1/2 G O = / 1 fc = 1/(2π) Inverting mplifier Equivalent L- ircuit V 1 } 2 } + V O V V O = G V G = - 2 / 1 Z IN 1 3 Z IN = 2 + s 2 ( ) 1 = 2 + s Leq ( ) >> 2 Function Generator + } } B frequency 1, 2, amplitude, B EV /10/04 haracteristics subject to change without notice. 22 of 25

23 PGING INFOMION 24-Bump hip cale Package (P B24) Package Outline Drawing a d Y I LO # k f b m l e j op View (Marking ide) Bottom View (Bumped ide) ide View e ide View e Ball Matrix L B 1 D P L0 V H1 H0 V D N H2 H3 N E 2 3 N1 L3 F L2 L 0 3 N - must be left unconnected Millimeters Inches ymbol Min Nom. Max Min Nom. Max Package idth Package Length B Package Height Body hickness D Ball Height E Ball Diameter F Ball Pitch idth J 0.5 Ball Pitch Length 0.5 Ball to Edge pacing idth L Ball to Edge pacing Length M EV /10/04 haracteristics subject to change without notice. 23 of 25

24 PGING INFOMION 24-Lead Plastic, OP, Package ode V (.65) B.169 (4.3).252 (6.4) B.177 (4.5).303 (7.70).311 (7.90).047 (1.20).0075 (.19).0118 (.30).002 (.06).005 (.15).010 (.25) (.50).030 (.75) Detail (20X) Gage Plane eating Plane (1.78) (4.16) (7.72) (0.42) (0.65).031 (.80).041 (1.05) LL MEUEMEN E YPIL ee Detail NOE: LL DIMENION IN INHE (IN PENHEE IN MILLIMEE) EV /10/04 haracteristics subject to change without notice. 24 of 25

25 PGING INFOMION 24-Lead Plastic, OI, Package ode (7.37) (7.60) (10.00) (10.65) Pin 1 Index Pin (0.35) (0.50) (15.20) (15.49) (4X) (2.35) (2.65) (1.27) (0.10) (0.30) 0.050" ypical (0.25) X (0.50) (0.40) (1.27) (0.22) (0.33) 0.420" 0.050" ypical FOOPIN 0.030" ypical 24 Places NOE: LL DIMENION IN INHE (IN PENHEE IN MILLIMEE) LIMIED NY Xicor, Inc Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its erms of ale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. DEM DILIME: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. utotore, Direct rite, Block Lock, erialflash, MP, and XDP are also trademarks of Xicor, Inc. ll others belong to their respective owners. U.. PEN Xicor products are covered by one or more of the following U.. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE ELED POLIY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. EV /10/04 haracteristics subject to change without notice. 25 of 25