DATASHEET X9408. Description. Features. Block Diagram. Low Noise/Low Power/2-Wire Bus Quad Digitally Controlled (XDCP ) Potentiometers

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1 DHEE X9408 Low Noise/Low ower/2-ire Bus Quad Digitally ontrolled (XD ) otentiometers FN8191 ev.4.00 Description he X9408 integrates four digitally controlled potentiometers (XD) on a monolithic M integrated circuit. he digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. he position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile iper ounter egister () and four non-volatile Data egisters that can be directly written to and read by the user. he contents of the controls the position of the wiper on the resistor array though the switches. ower-up recalls the contents of the default data register (D0) to the. he XD can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features Four otentiometers in ne ackage 64 esistor aps per otentiometer 2-wire erial Interface iper esistance, 40 ypical at 5V Four Nonvolatile Data egisters for Each ot Nonvolatile torage of iper osition tandby urrent < 1µ max (otal ackage) V = 2.7V to 5.5V peration V+ = 2.7V to 5.5V V- = -2.7V to -5.5V 10k, 2.5k End to End esistances High reliability Endurance 100,000 Data hanges er Bit er egister egister Data etention 100 years 24 Ld I, 24 Ld, 24 Ld DI ackages b-free (oh ompliant) Block Diagram V V+ V V IE UNE EGIE () V H0 / H0 V L0 / L IE UNE EGIE () EI Y 2 V H2 / H2 V L2 / L2 L D INEFE ND NL IUIY D 8 V 0 / 0 V 1 / 1 V 2 / 2 V 3 / IE UNE EGIE () EI Y 1 V H1 / H1 V L1 / L IE UNE EGIE () EI Y 3 V H3 / H3 V L3 / L3 FN8191 ev.4.00 age 1 of 20

2 rdering Information ENIMEE NUMBE MING V LIMI (V) GNIZIN (k ) EM NGE ( ) GE X9408Y24* X9408Y 5 ±10% to Ld I (300 mil) X9408Y24I* X9408Y I -40 to Ld I (300 mil) X9408YV24* X9408YV 0 to Ld (4.4mm) X9408YV24Z* (Note) X9408YV Z 0 to Ld (4.4mm) (b-free) X9408YV24I* X9408YV I -40 to Ld (4.4mm) X9408YV24IZ* (Note) X9408YV Z I -40 to Ld (4.4mm) (b-free) X940824* X to Ld I (300 mil) X940824I* X9408 I -40 to Ld I (300 mil) X9408V24* X9408V 0 to Ld (4.4mm) X9408V24Z* (Note) X9408V Z 0 to Ld (4.4mm) (b-free) X9408V24I* X9408V I -40 to Ld (4.4mm) X9408V24IZ* (Note) X9408V Z I -40 to Ld (4.4mm) (b-free) X9408Y24-2.7* X9408Y F 2.7 to to Ld I (300 mil) X9408Y24I-2.7* X9408Y G -40 to Ld I (300 mil) X9408YV24-2.7* X9408YV F 0 to Ld (4.4mm) X9408YV24Z-2.7* (Note) X9408YV Z F 0 to Ld (4.4mm) (b-free) X9408YV24I-2.7* X9408YV G -40 to Ld (4.4mm) X9408YV24IZ-2.71 (Note) X9408YV Z G -40 to Ld (4.4mm) ape and eel (b-free) X * X9408 F 10 0 to Ld I (300 mil) X940824I-2.7* X9408 G -40 to Ld I (300 mil) X940824IZ-2.7* (Note) X9408 Z G -40 to Ld I (300 mil) (b-free) X9408V24-2.7* X9408V F 0 to Ld (4.4mm) X9408V24Z-2.7* (Note) X9408V Z F 0 to Ld (4.4mm) (b-free) X9408V24I-2.7* X9408V G -40 to Ld (4.4mm) X9408V24IZ-2.7* (Note) X9408V Z G -40 to Ld (4.4mm) (b-free) *dd "1" suffix for tape and reel. **dd "1" suffix for tape and reel.lease refer to B347 for details on reel specifications. NE: hese Intersil b-free plastic packaged products employ special b-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is oh compliant and compatible with both nb and b-free soldering operations). Intersil b-free products are ML classified at b-free peak reflow temperatures that meet or exceed the b-free requirements of I/JEDE J D-020. FN8191 ev.4.00 age 2 of 20

3 in Descriptions Host Interface ins EIL L (L) he L input is used to clock data into and out of the X9408. EIL D (D) D is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ed with any number of open drain or open collector outputs. n open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVIE DDE ( 0-3 ) he address inputs are used to set the least significant 4 bits of the 8-bit slave address. match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9408. maximum of 16 devices may occupy the 2-wire serial bus. otentiometer ins V H / H (V H0 / H0 - V H3 / H3 ), V L / L (V L0 / L0 - V L3 / L3 ) he V H / H and V L / L inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. V / (V 0 / 0 V 3 / 3 ) he wiper outputs are equivalent to the wiper output of a mechanical potentiometer. HDE IE E INU () he pin when low prevents nonvolatile writes to the Data egisters. NLG ULIE V+, V- he nalog upplies V+, V- are the supply voltages for the XD analog section. in ssignments L D 0-3 YMBL erial lock erial Data Device ddress DEIIN V H0 / H0 - V H3 / H3, V L0 / L0 - V L3 / L3 otentiometer ins (terminal equivalent) V 0 / 0 - V 3 / 3 V+,V- V V N otentiometer ins (wiper equivalent) Hardware rite rotection nalog upplies ystem upply Voltage ystem Ground No onnection inouts X9408 (24 LD DI/I) VIE X9408 (24 LD ) VIE V V L0 / L V+ V L3 / L3 D V H0 / H V H3 / H3 V L1 / L V 0 / 0 V 0 / V 3 // H1 0 V H1 / H1 V 1 / V H0 / H0 V L0 / L N V 6 19 V D V V L V 2 / V L3 / L3 V L1 / L V L2 / L2 V H2 / H V H3 / H3 V H1 / H1 V 1 / V H2 / H2 V 2 / 2 V L2 / L2 L V 3 / 3 0 V V N FN8191 ev.4.00 age 3 of 20

4 rincipals of peration he X9408 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XD potentiometers. erial Interface he X9408 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master will always initiate data transfers and provide the clock for both transmit and receive operations. herefore, the X9408 will be considered a slave device in all applications. lock and Data onventions Data states on the D line can change only during L L periods (t L ). D state changes during L HIGH are reserved for indicating start and stop conditions. tart ondition ll commands to the X9408 are preceded by the start condition, which is a HIGH to L transition of D while L is HIGH (t HIGH ). he X9408 continuously monitors the D and L lines for the start condition and will not respond to any command until this condition is met. top ondition ll communications must be terminated by a stop condition, which is a L to HIGH transition of D while L is HIGH. cknowledge cknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. he transmitting device, either the master or the slave, will release the D bus after transmitting eight bits. he master generates a ninth clock cycle and during this period the receiver pulls the D line L to acknowledge that it successfully received the eight bits of data. he X9408 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9408 will respond with a final acknowledge. rray Description he X9408 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. he physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer ( H and L inputs). time. hese switches are controlled by the iper ounter egister (). he six bits of the are decoded to select, and enable, one of sixty-four switches. he may be written directly, or it can be changed by transferring the contents of one of four associated Data egisters into the. hese Data egisters and the can be read and written by the host system. Device ddressing Following a start condition the master must output the address of the slave it is accessing. he most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9408 this is fixed as 0101[B]. DEVIE YE IDENIFIE DEVIE DDE FIGUE 1. LVE DDE he next four bits of the slave address are the device address. he physical device address is defined by the state of the 0-3 inputs. he X9408 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9408 to respond with an acknowledge. he 0-3 inputs can be actively driven by M input signals or tied to V or V. cknowledge olling he disabling of the inputs, during the internal Nonvolatile write operation, can be used to take advantage of the typical 5ms EEM write cycle time. nce the stop condition is issued to indicate the end of the nonvolatile write command the X9408 initiates the internal write cycle. polling can be initiated immediately. his involves issuing the start condition followed by the device slave address. If the X9408 is still busy with the write operation no will be returned. If the X9408 has completed the write operation an will be returned and the master can then proceed with the next operation. t both ends of each array and between each resistor segment is a M switch connected to the wiper ( ) output. ithin each individual array only one switch may be turned on at a FN8191 ev.4.00 age 4 of 20

5 Flow 1. olling equence NN-VLILE IE MMND MLEED ENE LLING EGIE ELE I3 I2 I1 I IUE INUIN IE UNE EGIE ELE FIGUE 2. INUIN BYE FM IUE LVE DDE EUNED? YE FUHE EIN? YE IUE INUIN EED N N IUE IUE EED he four high order bits define the instruction. he next two bits (1 and 0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. he last bits (1, 0) select which one of the four potentiometers is to be affected by the instruction. Four of the nine instructions end with the transmission of the instruction byte. he basic sequence is illustrated in Figure 3. hese two-byte instructions exchange data between the iper ounter egister and one of the Data egisters. transfer from a Data egister to a iper ounter egister is essentially a write to a static M. he response of the wiper to this action will be delayed t L. transfer from the iper ounter egister (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t to complete. he transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. Instruction tructure he next byte sent to the X9408 contains the instruction and register pointer information. he four most significant bits are the instruction. he next four bits point to one of the two pots and when applicable they point to one of four associated registers. he format is shown in Figure 2. Four instructions require a three-byte sequence to complete. hese instructions transfer data between the host and the X9408; either between the host and one of the data registers or directly between the host and the iper ounter egister. hese instructions are: ead iper ounter egister (read the current wiper position of the selected pot), rite iper ounter egister (change current wiper position of the selected pot), ead Data egister (read the contents of the selected nonvolatile register) and rite Data egister (write a new value to the selected Data egister). he sequence of operations is shown in Figure 4. L D I3 I2 I1 I FIGUE 3. -BYE INUIN EQUENE FN8191 ev.4.00 age 5 of 20

6 he Increment/Decrement command is different from the other commands. nce the command is issued and the X9408 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each L clock pulse (t HIGH ) while D is HIGH, the selected wiper will move one resistor segment towards the H terminal. imilarly, for each L clock pulse while D is L, the selected wiper will move one resistor segment towards the L terminal. detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. INUIN INUIN E BLE 1. INUIN E I 3 I 2 I 1 I EIN ead iper ounteregister ead the contents of the iper ounter egister pointed to by 1-0 rite iper ounteregister rite new value to the iper ounter egister pointed to by 1-0 ead Data egister ead the contents of the Data egister pointed to by 1-0 and 1-0 rite Data egister rite new value to the Data egister pointed to by 1-0 and 1-0 XF Data egister to iper ounter egister XF iper ounter egister to Data egister Global XF Data egisters to iper ounter egisters Global XF iper ounter egisters to Data egister Increment/Decrement iper ounter egister ransfer the contents of the Data egister pointed to by 1-0 and 1-0 to its associated iper ounter egister ransfer the contents of the iper ounter egister pointed to by 1-0 to the Data egister pointed to by ransfer the contents of the Data egisters pointed to by 1-0 of all four pots to their respective iper ounter egisters ransfer the contents of both iper ounter egisters to their respective Data egisters pointed to by 1-0 of all four pots Enable Increment/decrement of the iper ounter egister pointed to by 1-0 NE: (7)1/0 = data is one or zero L D I3 I2 I1 I D5 D4 D3 D2 D1 D0 FIGUE 4. HEE-BYE INUIN EQUENE L D I3 I2 I1 I I N 1 I N 2 I N n D E 1 D E n FIGUE 5. INEMEN/DEEMEN INUIN EQUENE FN8191 ev.4.00 age 6 of 20

7 IN/DE MD IUED t ID L D V / VLGE U FIGUE 6. INEMEN/DEEMEN IMING LIMI L FM ME D UU FM NMIE D UU FM EEIVE FIGUE 7. NLEDGE ENE FM EEIVE NLEDGE FN8191 ev.4.00 age 7 of 20

8 EIL D H FM INEFE IUIY EGIE 0 EGIE EIL BU INU LLEL BU INU U N E V H / H EGIE 2 EGIE 3 IE UNE EGIE () D E D E IF = 00[H] HEN V / = V L / L IF = 3F[H] HEN V / = V H / H U/DN MDIFIED L IN/DE LGI U/DN L V L / L FIGUE 8. DEILED ENIMEE BL DIGM V / Detailed peration ll XD potentiometers share the serial interface and share a common architecture. Each potentiometer has a iper ounter egister and four Data egisters. detailed discussion of the register organization and array operation follows. iper ounter egister he X9408 contains four iper ounter egisters, one for each XD potentiometer. he iper ounter egister can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. he contents of the can be altered in four ways: it may be written directly by the host via the rite iper ounter egister instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XF Data egister instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its data register zero (D0) upon power-up. he is a volatile register; that is, its contents are lost when the X9408 is powered-down. lthough the register is automatically loaded with the value in 0 upon power-up, it should be noted this may be different from the value present at power-down. Data egisters Each potentiometer has four nonvolatile Data egisters. hese can be read or written directly by the host and data can be transferred between any of the four Data egisters and the. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. egister Descriptions BLE 2. DE EGIE, (6-BI), NNVLILE D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV (MB) (LB) Four 6-bit Data egisters for each XD. (sixteen 6-bit registers in total). {D5~D0}: hese bits are for general purpose not volatile data storage or for storage of up to four different wiper values. he contents of Data egister 0 are automatically moved to the wiper counter register on power-up. FN8191 ev.4.00 age 8 of 20

9 BLE 3. Instruction Format IE UNE EGIE, (6-BI), VLILE V V V V V V (MB) NE: 1. M / : stands for the acknowledge sent by the master/slave ~ 0 : stands for the device addresses sent by the master. 3. X : indicates that it is a 0 for testing purpose but physically it is a don t care condition. 4. I : stands for the increment operation, D held high during active L phase (high). 5. D : stands for the decrement operation, D held low during active L phase (high). ead iper ounter egister () (LB) ne 6-bit iper ounter egister for each XD. (Four 6-bit registers in total.) {D5~D0}: hese bits specify the wiper position of the respective XD. he iper ounter egister is loaded on power-up by the value in Data egister 0. he contents of the can be loaded from any of the other Data egister or directly. he contents of the can be saved in a D. DEVIE YE IDENIFIE DEVIE DDEE INUIN DE DDEE IE IIN (EN BY LVE N D) M rite iper ounter egister () DEVIE YE IDENIFIE DEVIE DDEE INUIN DE DDEE IE IIN (EN BY ME N D) ead Data egister (D) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND DDEE IE IIN/D (EN BY LVE N D) M rite Data egister (D) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND DDEE IE IIN/D (EN BY ME N D) HIGH-VLGE IE YLE XF Data egister (D) to iper ounter egister () DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND DDEE FN8191 ev.4.00 age 9 of 20

10 rite iper ounter egister () to Data egister (D) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND DDEE HIGH-VLGE IE YLE Increment/Decrement iper ounter egister () DEVIE YE IDENIFIE DEVIE DDEE INUIN DE DDEE INEMEN/DEEMEN (EN BY ME N D) I/D I/D.... I/D I/D Global XF Data egister (D) to iper ounter egister () DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D DDEE Global XF iper ounter egister () to Data egister (D) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D DDEE HIGH-VLGE IE YLE ymbol able Guidelines for alculating ypical Values of Bus ull-up esistors VEFM INU UU MU BE EDY MY HNGE FM L HIGH MY HNGE FM HIGH L DN E: HNGE LLED N/ ILL BE EDY ILL HNGE FM L HIGH ILL HNGE FM HIGH L HNGING: E N NN ENE LINE I HIGH IMEDNE EINE ( ) V MX MIN = =1.8k IL MIN t MX = BU MX. EINE 20 Min. esistance BU INE (pf) FN8191 ev.4.00 age 10 of 20

11 bsolute Maximum atings upply Voltage (V Limits) X V ±10% X V to 5.5V Voltage on D, L any address input with respect to V : V to +7V Voltage on V+ (eferenced to V ) V Voltage on V- (eferenced to V ) V (V+) - (V-) V I (10s) ±6m ny VH/H, VL/L, V/ V- to V+ hermal Information emperature Under Bias to +135 torage emperature to +150 b-free eflow rofile see link below perating onditions emperature ange ommercial to +70 Industrial to +85 UIN: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. nalog pecifications (ver recommended operating conditions unless otherwise stated.) LIMI YMBL MEE E NDIIN MIN (Note 6) Y (Note 4) MX (Note 6) UNI L End to end resistance tolerance % ower rating +25, each pot 50 m iper resistance I = (V H - V L )/ V+, V- = ±3V I = (V H - V L )/ V+, V- = ±5V V V + Voltage on V+ pin X V X V V - Voltage on V- pin X V X V EM Voltage on any V H / H, V L / L or V / pin V- V+ V Noise ef: 1kHz -120 dbv esolution (Note 4) 1.6 % bsolute linearity (Note 1) V(V wn / wn ) (actual) - V(V wn / wn ) (expected) (Note 4) elative linearity (Note 2) V(V w(n+1) / w(n+1) ) - [V(V w(n) / w(n) ) + MI] (Note 4) MI (Note 3) MI (Note 3) emperature coefficient of L (Note 4) 300 ppm/ atiometric emperature oefficient (Note 4) 20 ppm/ H / L / otentiometer apacitances ee Macro model 10/10/25 pf I L V H / H, V L / L, V / Leakage urrent V IN = V- to V+. Device is in tandby mode µ FN8191 ev.4.00 age 11 of 20

12 D Electrical pecifications (ver recommended operating conditions unless otherwise stated.) LIMI YMBL MEE E NDIIN MIN (Note 6) Y (Note 4) MX (Note 6) UNI I 1 V supply current (nonvolatile write) f L = 400kHz, D = pen, ther Inputs = V 5 m I 2 V supply current (move wiper, write, read) f L = 400kHz, D = pen, 250 µ ther Inputs = V I B V current (standby) L = D = V, ddr. = V 3 µ I LI Input leakage current 10 µ I L utput leakage current 10 µ V IH Input HIGH voltage V x 0.7 V +0.5 V V IL Input L voltage 0.5 V x 0.1 V V L utput L voltage I L = 3m 0.4 V NE: 1. bsolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 2. elative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = /63 or [V(V H / H ) - V(V L / L )]/63, single pot ENDUNE ND D EENIN MEE MIN UNI Minimum endurance 100,000 Data changes per bit per register Data retention 100 years INE YMBL E E NDIIN Y (Note 4) UNI I/ (Note 4) Input/output capacitance (D) V I/ = 0V 8 pf IN (Note 4) Input capacitance (0, 1, 2, 3, and L) V IN = 0V 6 pf E-U IMING YMBL MEE MIN (Note 6) MX (Note 6) UNI t U (Note 5) ower-up to initiation of read operation 1 ms t U (Note 5) ower-up to initiation of write operation 5 ms t V (Note 6) V ower-up amp V/msec NE: 4. Limits should be considered typical and are not production tested. 5. t U and t U are the delays required from the time the third (last) power supply (V, V+ or V-) is stable until the specific instruction can be issued 6. arameters with MIN and/or MX limits are 100% tested at +25, unless otherwise specified. emperature limits established by characterization and are not production tested. FN8191 ev.4.00 age 12 of 20

13 ower-up equirements (ower-up sequencing can affect correct recall of the wiper registers). he preferred power-on sequence is as follows: First V-, then V and V+, and then the potentiometer pins, V H / H, V L / L, and V /. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. he V ramp rate specification should be met, and any glitches or slope changes in the V line should be held to <100mV if possible. If V powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. lso, V should not reverse polarity by more than 0.5V. ecall of wiper position will not be complete until V, V+ and V- reach their final value... est onditions Input pulse levels V x 0.1 to V x 0.9 Input rise and fall times 10ns Input and output timing level V x 0.5 Equivalent.. Load ircuit 5V 1533 D UU 100F ircuit #3 IE Macro Model L V H / H H L 10pF V L / L 10pF 25pF V / FN8191 ev.4.00 age 13 of 20

14 iming (ver recommended operating condition) YMBL MEE MIN (Note 5) MX (Note 5) UNI f L lock frequency 400 khz t Y lock cycle time 2500 ns t HIGH lock high time 600 ns t L lock low time 1300 ns t U: tart setup time 600 ns t HD: tart hold time 600 ns t U: top setup time 600 ns t U:D D data input setup time 100 ns t HD:D D data input hold time 30 ns t (Note 7) L and D rise time 300 ns t F (Note 7) L and D fall time 300 ns t L low to D data output valid time 900 ns t DH D Data output hold time 50 ns I Noise suppression time constant at L and D inputs 50 ns t BUF Bus free time (prior to any transmission) 1300 ns t U:, 0, 1, 2 and 3 setup time 0 ns t HD:, 0, 1, 2 and 3 hold time 0 ns NE: 7. his parameter is not production tested. arameter established by characterization. HIGH-VLGE IE YLE IMING YMBL MEE Y. (Note 4) MX. (Note 6) UNI t High-voltage write cycle time (store instructions) 5 10 ms XD IMING YMBL MEE MIN. (Note 5) MX. (Note 6) UNI t iper response time after the third (last) power supply is stable 10 µs t L iper response time after instruction issued (all load instructions) 10 µs t ID iper response time from an active L/ edge (increment/decrement instruction) 10 µs FN8191 ev.4.00 age 14 of 20

15 iming Diagrams tart and top iming g () () t t F L t U: t HD: t U: t t F D Input iming t Y t HIGH L t L D t U:D t HD:D t BUF utput iming L D t t DH XD iming (for ll Load Instructions) () L D LB t L Vx FN8191 ev.4.00 age 15 of 20

16 XD iming (for Increment/Decrement Instruction) L D IE EGIE DDE IN/DE IN/DE t ID Vx rite rotect and Device ddress ins iming () () L D... (NY INUIN) t U: t HD: 0, 1 2, 3 pplications information Basic onfigurations of Electronic otentiometers V +V I HEE EMINL ENIMEE; VIBLE VLGE DIVIDE EMINL VIBLE EI; VIBLE UEN FN8191 ev.4.00 age 16 of 20

17 pplication ircuits NNINVEING MLIFIE VLGE EGUL V + V V IN 317 V (EG) 1 2 I adj 1 2 V (EG) = 1.25V (1+ 2 / 1 )+I adj 2 V = (1+ 2 / 1 )V FFE VLGE DJUMEN M IH HYEEI V 1 100k + 2 V V + V 10k L072 } 1 } 2 10k 10k V UL = { 1 /( )} V (max) V LL = { 1 /( )} V (min) +12V -12V FN8191 ev.4.00 age 17 of 20

18 pplication ircuits (continued) ENU FILE V + V V V 3 4 ll = 10k 1 2 V = G V -1/2 G +1/2 G = / 1 fc = 1/(2 ) INVEING MLIFIE EQUIVLEN L- IUI V 1 } 2 } + V V V = G V G = - 2 / 1 Z IN 1 3 Z IN = 2 + s 2 ( ) 1 = 2 + s Leq ( ) >> 2 FUNIN GENE + } } B FEQUENY µ 1, 2, MLIUDE µ, B FN8191 ev.4.00 age 18 of 20

19 hin hrink mall utline ackage Family () E 0.25 M B E1 B EING LNE 0.10 N LED e N 1 D VIE b IDE VIE EE DEIL X (N/2)+1 (N/2) IN #1 I.D B 2X N/2 LED I M B H MD0044 HIN HIN MLL ULINE GE FMILY MILLIMEE YMBL 14 LD 16 LD 20 LD 24 LD 28 LD LENE Max ± ±0.05 b /-0.06 c /-0.06 D ±0.10 E Basic E ±0.10 e Basic L ±0.15 L eference ev. F 2/07 NE: 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions D and E1 are measured at dtum lane H. 4. Dimensioning and tolerancing per ME Y14.5M c END VIE L1 2 1 DEIL X L 0-8 GUGE LNE 0.25 FN8191 ev.4.00 age 19 of 20

20 mall utline lastic ackages (I) N INDEX E e D B 0.25(0.010) M M E -B EING LNE B H 0.25(0.010) M B (0.004) NE: 1. ymbols are defined in the M eries ymbol List in ection 2.2 of ublication Number Dimensioning and tolerancing per NI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. he chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. erminal numbers are shown for reference only. 9. he lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. ontrolling dimension: MILLIMEE. onverted inch dimensions are not necessarily exact. L M h x 45 M24.3 (JEDE M-013-D IUE ) 24 LED IDE BDY MLL ULINE LI GE INHE MILLIMEE YMBL MIN MX MIN MX NE B D E e 0.05 B 1.27 B - H h L N ev. 1 4/06 opyright Intersil mericas LL ll ights eserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing I9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN8191 ev.4.00 age 20 of 20