User Manual. 1000BASE-T1 SFP Module

Transcription

1 User anual odule Version June 2017 echnica ngineering Gmb eopoldstraße ünchen Germany ax: mail:

2 ndex 1 eature ist arranty and afety nformation inning tartup and onfiguration tartup elf-onfiguration interface pecifications odule processor 2 register map Device addressing and operation urrent address read andom read equential read yte write equential write access to the 88Q2112_Z1 transceiver egister description Y register access examples ead peration rite peration.14 6 ontact age 2 of 17

3 1 eature ist he echnica ngineering 1000ase-1 odule fits into a standard mall orm-factor luggable slot. t uses the G and generates 1000 bit/s full-duplex. Note: D interface is not supported! fter power up, it self-configures to utomotive 1000ase-1. egisters of the integrated transceiver are accessible via 2 interface for diagnosis and reconfiguration. ne ink D shows link status. ower requirement: 3.3 Volt D +/ Volt ize: 68 x 14 x 14 mm eight: 0,1 kg nternational rotection: 2 0 perating emperature: 0 to +70 elsius age 3 of 17

4 2 arranty and afety nformation efore operating the device, read this manual thoroughly and retain it for your reference. Use the device only as described in this manual. Use only in dry conditions. Do not apply power to a damaged device. Do not open the device. therwise warranty will be lost. his device is designed for engineering purpose only. pecial care has to be taken for operation. Do not use this device in a series production car. s this device is likely to be used under rough conditions, warranty is limited to 1 year. anufacturer liability for damage caused by using the device is excluded. age 4 of 17

5 3 inning he 1000ase-1 line is connected by a olex connector. olex eader 2.0mm olex ousing olex rimp ontact in unction in unction ase-1 lus ase-1 inus ocket connector: in unction in unction 1 GND 20 GND 2 x_aul onnected to GND 19 G_XD_N 3 n.c. 18 G_XD_ 4 2_D 17 GND 5 2_ Volt 6 GND Volt 7 n.c. 14 GND 8 x_os onnected to GND 13 G_XD_ 9 n.c. 12 G_XD_N 10 GND 11 GND age 5 of 17

6 4 tartup and onfiguration 4.1 tartup fter 3.3 Volt power is applied, the module starts up and self-configures the 88Q2112_Z1 transceiver by D interface. his lasts 100ms. Do not apply any 2 activity on the bus during this time. 4.2 elf-onfiguration he odule configures itself to utomotive 1000ase-1 after power up. aster / lave onfiguration is done according to the D switch on the bottom of the device. he lock has to be opened if reconfiguration of the D switch is desired (see picture below). N = aster = lave age 6 of 17

7 5 2 nterface specifications 2 can be used 100ms after the power up of the module. he module operates with f up to 53z without requiring clock stretching. he module may clock stretch with f greater than 53z and up to 400 kz. he module processor listens as slave on the 7-bit address 0x50. Note: b X = 0x0 ead access beyond address 95 will return 0x00. he 88Q2112_Z1 transceiver can be accessed at 2 slave 7-bit address 0x40. Note: b X = 0x80 he 88Q2112_Z1 Y does not support 2 interfaces. owever, the microcontroller acts as a bridge between the host and the Y. ommands from the ost are processed by the microcontroller. he microcontroller accesses to the Y trough D interface and forwards the information to the ost. 5.2 odule processor 2 register map emory ap (ead only registers): Data ytes yte Number omment 0x03, 0 dentifier 0x04, 1 xt. dentifier 0x80, 2 onnector 0x00, 0x00, 0x00, 0x00, 3-6 ransceiver high 0x00, 0x00, 0x00, 0x00, 7-10 ransceiver low 0x00, 11 ncoding 0x01, 12 itrate Nominal in 100 it 0x00, 13 eserved 0x00, 14 ink ength iber 0x00, 15 ink ength iber 0x00, 16 ink ength iber 0x00, 17 ink ength iber 0x0, 18 ink ength opper in meter 0x00, 19 eserved '', 'e', 'c', 'h', 'n', 'i', 'c', 'a', ' ', '', 'n', 'g', '.', ' ', ' ', ' ', Vendor Name 0x00, 36 eserved 0x00, 0x00, 0x00, Vendor D '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', artnumber 0x00, 0x00, 0x00, 0x00, evision Number 0x00, 0x00, 0x00, eserved 0x, 63 heck ode for ield x00, 0x00, ptions 0x00, 66 itrate max 0x00, 67 itrate min '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '1', '2', '3', '4', '5', '6', erial Number tring 0x00, 0x00, 0x00, 0x00, Date ode high 0x00, 0x00, 0x00, 0x00, Date ode low 0x00, 0x00, 0x00, eserved 0x42 95 heck ode xtended for ield Device addressing and operation urrent ddress ead he current read operation only requires the 2 device read word to be sent. hen the acknowledge is received from the module, the current address data word is serially clocked out. age 7 of 17

8 age 8 of 17 xample: ead the current address of the module (b x) <-2_device -> D N X X X X X X X X 1 <-D D-> andom ead he random address read requires two operations to perform the read. xample: ead a random address of the module (2_device = b x) irst a write operation to specify the address desired to read: <-2_device -> <-2 emory address-> X X X X X X X X 0 hen a read operation to read the previous address specified: <-2_device -> D N X X X X X X X X 1 <-D D->

9 age 9 of equential read he sequential reads are started by either a current word address read or a random address read. o specify a sequential read, the host responds with an acknowledge instead of a stop after each data word. irst a write operation to specify the address desired to read: <-2_device -> <-2 emory address-> X X X X X X X X 0 hen the read operations: <-2_device -> D N X X X X X X X X 1 X X X X X X X X 1 <-D D n-> <-D D n+1-> yte rite he write operation requires 8-bits of data word address following the device address write word and acknowledgement. xample: yte write operation into the module (b x) <-2_device -> <-Y DD-> <-D D-> X X X X X X X X 0 X X X X X X X X 0

10 5.3.5 equential write he sequential write is started in the same way as a single byte write, but the host master does not send a stop condition after the first word is clocked in. <-2_device -> <-Y DD-> <-D D 1-> <-D D 2-> X X X X X X X X 0 X X X X X X X X 0 X X X X X X X X access to the 88Q2112_Z1 transceiver he 88Q2112_Z1Y listens as slave on the 7-bit address 0x40. very internal register of the Y (16 bits) is accessed by defining the Device Number (1 byte) and the egister ddress (2 bytes). he 2 emory address is mapped as: ddress 0x00 0x01 0x02 0x03 0x04 0x05 egister name Device number egister_address_ egister_address_ Y_egister_peration Y_register_data_ Y_register_data_ egister description Device number Defines the device number of the register to access egister_address_ Defines the ost significant byte of the register to access egister_address_ Defines the ess ignificant yte of the register to access Y_egister_peration_tatus it 0 ead tart ondition lag (ead/rite) his flag is set by the master after specifying the first 3 bytes of the register (Devices number, egister_address_ and egister_address_) when a read operation is trigged. age 10 of 17

11 it 1 ead n rogress lag (ead) his flag is set by the slave during the reading operation it 2 ead peration Done lag (ead) his flag is set by the slave when the reading operation is finished. his flag can be read after triggering the read to ensure that the data has finished reading. it 3 rite tart ondition lag (ead) his flag is set by the slave when a write operation is trigged. it 4 rite n rogress lag (ead) his flag is set by the slave during the writing operation it 5 rite peration Done lag (ead) his flag is set by the slave when the writing operation is finished. his flag can be read after writing the Y_register_data_ to ensure that the data has finished writing Y_register_data_ hen a reading operation, this register contains the of the Y register. hen a write operation, this register contains the to write in the Y register Y_register_data_ hen a reading operation, this register contains the of the Y register. hen a write operation, this register contains the to write in the Y register 5.5 Y register access examples ead peration he ead peration is performed by accessing the Y 2 device and loading the Y register address into the appropriate 2 registers. he register memory can be specified either with 2 andom ccess or 2 equential ccess xample: ead the Y s U using 2 andom ccess. egister (Device number 1, register 0x0002) <-2_device -> <-2 emory address-> <- Device_Number> x00 0x01 age 11 of 17

12 age 12 of 17 <-2_device-> <-2 emory address-> <egister_address_> x01 0x00 <-2_device-> <-2 emory address-> <egister_address_> x02 0x02 <-2_device-> <-2 emory address-> Y_egister_peration x03 0x01 <-2_device-> <-2 emory address-> <-2_device-> D N x04 Y_register_data_

13 age 13 of 17 <-2_device-> <-2 emory address-> <-2_device-> D N x05 Y_register_data_ xample: ead the Y s U using 2 equential ccess. egister (Device number 1, register 0x0002) <-2_device-> <-2 emory address-> < Device_Number> <egister_address_> x00 0x01 0x00 <egister_address_> <Y_egister_peration> <-2_device-> D x02 0x01 Y_register_data_ N Y_register_data_

14 age 14 of rite peration he rite peration requires the Y address word and the register memory. he register memory can be specified either with 2 yte rite or 2 equential rite xample: et the Y to lave configuration using 2 yte rite. Value: 0x8001.egister (Device number 1, register 0x0834) <-2_device -> <-2 emory address-> <- Device_Number> x00 0x01 <-2_device-> <-2 emory address-> <egister_address_> x01 0x80 <-2_device-> <-2 emory address-> <egister_address_> x02 0x01

15 age 15 of 17 <-2_device-> <-2 emory address-> Y_egister_peration x03 0x00 <-2_device-> <-2 emory address-> <-2_device-> Y_register_data_ x04 0x80 <-2_device-> <-2 emory address-> <-2_device-> Y_register_data_ x05 0x01

16 age 16 of 17 xample: et the Y to aster configuration using 2 equential rite. Value: 0x001.egister (Device number 1, register 0x0834) <-2_device-> <-2 emory address-> < Device_Number> <egister_address_> x00 0x01 0x08 <egister_address_> <Y_egister_peration> x34 0x00 Y_register_data_ Y_register_data_

17 6 ontact f you have any questions regarding this product please do not hesitate to contact us: echnica ngineering Gmb eopoldstraße ünchen Germany elefon: ax: nfo@technica-engineering.de age 17 of 17