1.7V (V CC = 1.7V to 5.5V) 2.5V (V CC = 2.5V to 5.5V) Partial Page Writes Allowed

Transcription

1 24M01 I 2 -ompatible (2-wire) erial POM 1-Mbit (131,072 x 8) DH Features Low Voltage and tandard Voltage Operation vailable 1.7V (V = 1.7V to 5.5V) 2.5V (V = 2.5V to 5.5V) Internally Organized 131,072 x 8 2-wire erial Interface chmitt riggers, Filtered Inputs for Noise uppression Bidirectional Data ransfer Protocol 400kHz (1.7V) and 1MHz (5V, 2.5V) ompatibility rite Protect Pin for Hardware Data Protection 256-byte Page rite Mode Partial Page rites llowed andom and equential ead Modes elf-timed rite ycle (5ms Max) High eliability ndurance: 1,000,000 rite ycles Data etention: 40 Years Green Package Options (Pb/Halide-free/oH ompliant) 8-lead JD OI, 8-lead IJ OI, 8-lead OP, and 8-ball LP Die ale Options: afer Form and ape and eel vailable Description he tmel 24M01 provides 1,048,576 bits of erial lectrically rasable and Programmable ead-only Memory (POM) organized as 131,072 words of 8 bits each. he device s cascadable feature allows up to four devices to share a common 2-wire bus. he device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. he devices are available in space-saving 8-lead JD OI, 8-lead IJ OI, 8-lead OP, and 8-ball LP. In addition, the entire family is available in 1.7V (1.7V to 5.5V) and 2.5V (2.5V to 5.5V) versions. tmel-8812f-pom-24m01-datasheet_012015

2 1. Pin onfigurations and Pinouts Pin Name Function 8-lead OI 8-lead OP N 1 2 No onnect ddress Input ddress Input N 1 2 GND op View V P L D N 1 2 GND op View V P L D GND D Ground erial Data 8-ball LP L erial lock Input V P N P rite Protect L 1 V Power upply D 2 GND op View Note: Drawings are not to scale. 2. bsolute Maximum atings* Operating emperature to +125 torage emperature to +150 Voltage on any pin with respect to ground V to +7.0V Maximum Operating Voltage V D Output urrent m *Notice: tresses beyond those listed under bsolute Maximum atings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. xposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

3 3. Block Diagram V GND P L D tart top Logic LOD erial ontrol Logic N H.V. Pump/iming Device ddress omparator OMP LOD IN Data ecovery 2 1 / Data ord ddr/counter X D POM Y D erial MUX D IN D OU / Logic D OU 4. Pin Description erial lock (L): he L input is used to positive edge clock data into each POM device and negative edge clock data out of each device. erial Data (D): he D pin is bidirectional for serial data transfer. his pin is open drain driven and may be wire-oed with any number of other open drain or open collector devices. Device ddresses ( 2 and 1 ): he 2 and 1 pins are device address inputs that can be hardwired or left not connected for hardware compatibility with other tmel 24xx devices. hen the 2 and 1 pins are hardwired, as many as four 1-Mbit devices may be addressed on a single bus system (ee Device ddressing on page 9. for more details). If the 2 and 1 pins are left floating, the 2 and 1 pin will be internally pulled down to GND if the capacitive coupling to the circuit board V plane is <3pF. If coupling is >3pF, tmel recommends connecting the 2 and 1 pin to GND. rite Protect (P): he rite Protect input, when connected to GND, allows normal write operations. hen P is connected high to V, all write operations to the memory are inhibited. If the pin is left floating, the P pin will be internally pulled down to GND if the capacitive coupling to the circuit board V plane is <3pF. If coupling is >3pF, tmel recommends connecting the pin to GND. witching P to V prior to a write operation creates a software write protect function. able 4-1. rite Protect P Pin tatus t V t GND Part of the rray Protected Full rray Normal ead/rite Operations 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

4 5. Memory Organization 24M01, 1-Mbit erial POM: he 1-Mbit is internally organized as 512 pages of 256 bytes each. andom word addressing requires a 17-bit data word address. 5.1 Pin apacitance able 5-1. Pin apacitance (1) pplicable over recommended operating range from = 25, f = 1.0MHz, V = 5.5V. ymbol est ondition Max Units onditions I/O Input/Output apacitance (D) 8 pf V I/O = 0V IN Input apacitance ( 2, 1, L) 6 pf V IN = 0V Note: 1. his parameter is characterized and is not 100% tested. 5.2 D haracteristics able 5-2. D haracteristics pplicable over recommended operating range from: I = -40 to +85, V = 1.7V to 5.5V (unless otherwise noted). ymbol Parameter est ondition Min yp Max Units V 1 V 2 upply Voltage, 1.7V Option upply Voltage, 2.5V Option V V I upply urrent V = 5.0V ead at 400kHz 2.0 m I upply urrent V = 5.0V rite at 400kHz 3.0 m I B tandby urrent 1.0 μ V = 1.7V V IN = V or V V = 2.5V 2.0 μ V = 3.6V 3.0 μ V IN = V or V V = 5.5V 6.0 μ I LI Input Leakage urrent V IN = V or V μ I LO Output Leakage urrent V OU = V or V μ V IL Input Low Level (1) -0.6 V x 0.3 V V IH Input High Level (1) V x 0.7 V V V OL1 Output Low Level V = 1.7V I OL = 0.15m 0.2 V V OL2 Output Low Level V = 3.0V I OL = 2.1m 0.4 V Note: 1. V IL min and V IH max are reference only and are not tested. 4 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

5 5.3 haracteristics able 5-3. haracteristics pplicable over recommended operating range from I = -40 to +85, V = 1.7V to 5.5V (where applicable), L = 100pF (unless otherwise noted). est conditions are listed in Note V 2.5V, 5.0V ymbol Parameter Min Max Min Max Units f L lock Frequency, L khz t LO lock Pulse idth Low ns t HIGH lock Pulse idth High ns t I Noise uppression ime (1) ns t lock Low to Data Out Valid ns t BUF ime the bus must be free before a new transmission can start (1) ns t HD. tart ondition Hold ime ns t U. tart ondition et-up ime ns t HD.D Data In Hold ime 0 0 ns t U.D Data In et-up ime ns t Inputs ise ime (1) ns t F Inputs Fall ime (1) ns t U.O top ondition et-up ime ns t DH Data Out Hold ime ns t rite ycle ime 5 5 ms ndurance (1) 25, Page Mode, 3.3V 1,000,000 rite ycles Notes: 1. his parameter is ensured by characterization only. 2. measurement conditions: L (connects to V ): 1.3 k (2.5V, 5V), 10 k (1.7V) Input pulse voltages: 0.3 V to 0.7 V Input rise and fall times: 50ns Input and output timing reference voltages: 0.5 V 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

6 6. Device Operation lock and Data ransitions: he D pin is normally pulled high with an external device. Data on the D pin may change only during L low time periods. Data changes during L high periods will indicate a tart or top condition as defined below. Figure 6-1. Data Validity D L Data table Data table Data hange tart ondition: high-to-low transition of D with L high is a tart condition which must precede any other command. top ondition: low-to-high transition of D with L high is a top condition. fter a read sequence, the top condition will place the POM in a standby power mode. Figure 6-2. tart and top Definition D L tart ondition top ondition 6 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

7 cknowledge: ll addresses and data words are serially transmitted to and from the POM in eight bit words. he POM sends a zero during the ninth clock cycle to acknowledge that it has received each word. Figure 6-3. Output cknowledge L Data In Data Out tart ondition cknowledge tandby Mode: he 24M01 features a low-power standby mode which is enabled: Upon power-up. fter the receipt of the top condition and the completion of any internal operation. oftware eset: fter an interruption in protocol, power loss, or system reset, any 2-wire part can be protocol reset by following these steps: 1. reate a tart condition (if possible). 2. lock nine cycles. 3. reate another tart condition followed by top condition as in Figure 6-4. he device should be ready for the next communication after the above steps have been completed. In the event that the device is still non-responsive or remains active on the D bus, a power cycle must be used to reset the device. Figure 6-4. oftware eset Dummy lock ycles L tart ondition tart ondition top ondition D 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

8 Figure 6-5. Bus iming L: erial lock, D: erial Data I/O t HIGH t F t L t LO t LO t U. t HD. t HD.D t U.D t U.O D IN t t DH t BUF D OU Figure 6-6. rite ycle iming L: erial lock, D: erial Data I/O L D 8 th Bit OD N t (1) top ondition tart ondition Note: 1. he write cycle time t is the time from a valid top condition of a write sequence to the end of the internal clear/write cycle. 8 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

9 7. Device ddressing he 1-Mbit POM requires an 8-bit device address word following a tart condition to enable the chip for a read or write operation (see Figure 7-1 below). he device address word consists of a mandatory 1010 sequence for the first four most significant bits. his is common to all 2-wire POM devices. he 1-Mbit uses the two device address bits, 2 and 1, to allow up to four devices on the same bus. hese 2 and 1 bits must compare to the corresponding hardwired input pins, 2 and 1. he 2 and 1 pins uses an internal proprietary circuit that biases it to a logic low condition if the pin is allowed to float. he seventh bit (P 0 ) of the device address is a memory page address bit. his memory page address bit is the most significant bit of the data word address that follows. he eighth bit of the device address is the read/write operation select bit. read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the POM will output a zero. If a valid compare is not made, the device will return to a standby state. Figure 7-1. Device ddress 1Mb P0 / MB LB 8. rite Operations Byte rite: o select a data word in the 1-Mbit memory requires a 17-bit word address. he word address field consists of the P 0 bit in the device address byte, then the most significant word address followed by the least significant word address (Figure 8-1). write operation requires the P 0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the POM will again respond with a zero and then the part is to receive the first 8-bit data word. Following receipt of the 8-bit data word, the POM will output a zero. he addressing device, such as a microcontroller, then must terminate the write sequence with a top condition. t this time the POM enters an internally timed write cycle, t, to the nonvolatile memory. ll inputs are disabled during this write cycle and the POM will not respond until the write is complete (Figure 8-1). Figure 8-1. Byte rite Device ddress I First ord ddress econd ord ddress Data O P D LIN M B P 0 / L B L B 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

10 Page rite: he 1-Mbit POM is capable of a 256-byte Page rite. Page rite is initiated the same way as a Byte rite, but the microcontroller does not send a top condition after the first data word is clocked in. Instead, after the POM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. he POM will respond with an acknowledge after each data word is received. he microcontroller must terminate the page write sequence with a top condition (Figure 8-2) and the internally timed write cycle will begin. he data word address lower 8 bits are internally incremented following the receipt of each data word. he higher data word address bits are not incremented, retaining the memory page row location. hen the internally generated word address, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the POM, the data word address will roll over and previous data will be overwritten. he address rollover during write is from the last byte of the current page to the first byte of the same page. Figure 8-2. Page rite Device ddress I First ord ddress econd ord ddress Data (n) Data (n + x) O P D LIN M B P 0 / L B L B cknowledge Polling: Once the internally timed write cycle has started and the POM inputs are disabled, cknowledge Polling can be initiated. his involves sending a tart condition followed by the device address word. he read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the POM respond with a zero, allowing a new read or write sequence to be initiated. Data ecurity: he 24M01 has a hardware data protection scheme that allows the user to write protect the entire memory when the P pin is at V M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

11 9. ead Operations ead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. here are three read operations: urrent ddress ead, andom ddress ead, and equential ead. urrent ddress ead: he internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. his address stays valid between operations as long as the V to the part is maintained. he address rollover during read is from the last byte of the last page, to the first byte of the first page of the memory. Once the device address with the read/write select bit set to one is input and acknowledged by the POM, the current address data word is serially clocked out on the D line. he microcontroller does not respond with a zero but does generate a following top condition. Figure 9-1. urrent ddress ead Device ddress D Data O P D LIN M B P 0 / N O andom ead: andom ead requires an initial byte write sequence to load in the data word address. his is known as a dummy write operation. Once the device address word and data word address are clocked in and acknowledged by the POM, the microcontroller must generate another tart condition. he microcontroller now initiates a current address read by sending a device address with the read/write select bit high. he POM acknowledges the device address and serially clocks out the data word on the D line. he microcontroller does not respond with a zero but does generate a following top condition. Figure 9-2. andom ead Device ddress I First ord ddress econd ord ddress Device ddress D Data (n) O P D LIN M B P 0 / Dummy rite L B P 0 / N O 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

12 equential ead: equential eads are initiated by either a urrent ddress ead or a andom ead. fter the microcontroller receives a data word, it responds with an acknowledge. s long as the POM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. hen the memory address limit is reached, the data word address will roll over and the sequential read will continue. he equential ead operation is terminated when the microcontroller does not respond with a zero, but does generate a following top condition. Figure 9-3. equential ead D LIN Device ddress I First ord ddress econd ord ddress... M B P 0 / L B... Device ddress Dummy rite D Data (n) Data (n + 1) Data (n + 2) Data (n + x) O P P 0 / N O 12 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

13 10. Ordering ode Detail 24M01-HM-B tmel Designator Product Family 24 = tandard I 2 erial POM Device Density M = Megabit Family 01 = 1 Megabit hipping arrier Option B or blank = Bulk (ubes) = ape and eel Operating Voltage M = 1.7V to 5.5V D = 2.5V to 5.5V Package Device Grade or afer/die hickness H = Green, NiPdu Lead Finish Industrial emperature ange (-40 to +85 ) U = Green, Matte n Lead Finish Industrial emperature ange (-40 to +85 ) 11 = 11mil afer hickness Package Option = JD OI = IJ OI X = OP U = 3x5 Grid rray, LP U = afer Unsawn 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

14 11. Part Markings 24M01: Package Marking Information 8-lead OI 8-lead IJ MLHY MLHY 8-lead OP 8-ball LP HY %U ### YXX Note 1: designates pin 1 Note 2: Package drawings are not to scale atalog Number runcation 24M01 runcation ode ###: 2G Date odes Voltages Y = Year M = Month = ork eek of ssembly % = Minimum Voltage 4: : 2018 : January 02: eek 2 D: 2.5V min 5: : 2019 B: February 04: eek 4 M: 1.7V min 6: : : : 2021 L: December 52: eek 52 ountry of ssembly Lot Number Grade/Lead Finish = ountry of ssembly... = tmel afer Lot Number H: Industrial/NiPdu U: Industrial/Matte in/ngu race ode XX = race ode (tmel Lot Numbers orrespond to ode) xample:, B... YZ, ZZ tmel runcation : tmel M: tmel ML: tmel 12/12/14 IL DING NO. V. Package Mark ontact: DL-O-ssy_eng@atmel.com 24M01M, 24M01 Package Marking Information 24M01M F 14 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

15 12. Ordering Information tmel Ordering ode Lead Finish Package Voltage Delivery Information Form Quantity Operation ange 24M01-HM-B Bulk (ubes) 100 per ube 1.7V to 5.5V 24M01-HM- ape and eel 4,000 per eel 81 24M01-HD-B Bulk (ubes) 100 per ube 2.5V to 5.5V 24M01-HD- ape and eel 4,000 per eel 24M01-HM-B Bulk (ubes) 95 per ube 1.7V to 5.5V 24M01-HM- ape and eel 2,000 per eel NiPdu 82 (Lead-free/Halogen-free) 24M01-HD-B Bulk (ubes) 95 per ube 2.5V to 5.5V 24M01-HD- ape and eel 2,000 per eel Industrial emperature (-40 to 85 ) 24M01-XHM-B Bulk (ubes) 100 per ube 1.7V to 5.5V 24M01-XHM- ape and eel 5,000 per eel 8X 24M01-XHD-B Bulk (ubes) 100 per ube 2.5V to 5.5V 24M01-XHD- ape and eel 5,000 per eel 24M01-UUM- (1) ngu (Lead-free/Halogen-free) 8U-6 1.7V to 5.5V ape and eel 24M01-U11M (2) N/ afer ale Note 2 5,000 per eel Notes: 1. LP Package UION: xposure to ultraviolet (UV) light can degrade the data stored in the POM cells. herefore, customers who use a LP product must ensure that exposure to ultraviolet light does not occur. 2. For wafer sales, please contact tmel ales. Package ype X 8-lead, wide, Plastic Gull ing mall Outline (JD OI) 8-lead, wide, Plastic Gull ing mall Outline (IJ OI) 8-lead, 4.4mm body, Plastic hin hrink mall Outline (OP) 8U-6 8-ball, 3x5 Grid rray, afer Level hip cale (LP) 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

16 13. Packaging Information lead JD OI 1 1 N L OP VI Ø ND VI e b OMMON DIMNION (Unit of Measure = mm) 1 YMBOL MIN NOM MX NO b D ID VI Notes: his drawing is for general information only. efer to JD Drawing M-012, Variation for proper dimensions, tolerances, datums, etc. D e 1.27 B L Ø 0 8 6/22/11 IL GP DING NO. V. Package Drawing ontact: packagedrawings@atmel.com 81, 8-lead (0.150 ide Body), Plastic Gull ing mall Outline (JD OI) B 81 G 16 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

17 lead IJ OI OP VI 1 ND VI 1 L e Notes: 1. his drawing is for general information only; refer to IJ Drawing D-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b, apply to plated terminal. he standard thickness of the plating layer shall measure between to.021 mm. 8 ID VI D b 1 q OMMON DIMNION (Unit of Measure = mm) YMBOL MIN NOM MX NO b D L q 0 8 e 1.27 B 3 11/10/14 Package Drawing ontact: packagedrawings@atmel.com IL 82, 8-lead, Body, Plastic mall Outline Package (IJ) GP N DING NO. 82 V. G 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

18 13.3 8X 8-lead OP 1 Pin 1 indicator this corner 1 L1 op View b N nd View L 1 Notes: D e ide View 1. his drawing is for general information only. efer to JD Drawing MO-153, Variation, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension 1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. llowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and 1 to be determined at Datum Plane H. 2 OMMON DIMNION (Unit of Measure = mm) YMBOL MIN NOM MX NO D , B , 5 b e 0.65 B L L F /27/14 IL GP DING NO. V. Package Drawing ontact: packagedrawings@atmel.com 8X, 8-lead 4.4mm Body, Plastic hin hrink mall Outline Package (OP) N 8X 18 24M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

19 13.4 8U-6 8-ball LP 4X d d Pin 1 B D D 1 j n0.015m j n 0.05m B Øb D B Pin e e2 d d2 OP VI ID VI BLL ID * Dimensions are NO to scale. OMMON DIMNION (Unit of Measure = mm) Pin ssignment Matrix B D V D P N L 1 2 GND YMBOL MIN YP MX NO ontact tmel for details e e d d D ontact tmel for details b /25/13 Package Drawing ontact: packagedrawings@atmel.com IL 8U-6, 8-ball (3x5 rray) afer Level hip cale Package (LP) GP GHZ DING NO. V. 8U-6 B 24M01 [DH] tmel-8812f-pom-24m01-datasheet_

20 14. evision History Doc. No. Date omments 8821F 01/ /2013 Update the ordering information section, part markings, and the 8X and 82 package outline drawings. Update document status from preliminary to complete. orrect LP pinout. Update footers and disclaimer page. 8812D 01/2013 orrect OP pin label 7 to P / B 07/2012 dd LP package. Update part markings. Update pinout diagram. Update part markings. orrect Byte rite figure from second typo error to first word address. Update equential ead figure. orrect ordering code: - 24M01-U-11, Die ale to 24M01-U11M, afer ale. Update tmel logos and disclaimer page /2012 Initial document release M01 [DH] tmel-8812f-pom-24m01-datasheet_012015

21 X X X X X X tmel orporation 1600 echnology Drive, an Jose, U : (+1)(408) F: (+1)(408) tmel orporation. / ev.: tmel-8812f-pom-24m01-datasheet_ tmel, tmel logo and combinations thereof, nabling Unlimited Possibilities, and others are registered trademarks or trademarks of tmel orporation in U.. and other countries. Other terms and product names may be trademarks of others. DILIM: he information in this document is provided in connection with tmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of tmel products. XP FOH IN H ML M ND ONDIION OF L LOD ON H ML BI, ML UM NO LIBILIY HOV ND DILIM NY XP, IMPLID O UOY NY LING O I PODU INLUDING, BU NO LIMID O, H IMPLID NY OF MHNBILIY, FIN FO PIUL PUPO, O NON-INFINGMN. IN NO VN HLL ML B LIBL FO NY DI, INDI, ONQUNIL, PUNIIV, PIL O INIDNL DMG (INLUDING, IHOU LIMIION, DMG FO LO ND POFI, BUIN INUPION, O LO OF INFOMION) IING OU OF H U O INBILIY O U HI DOUMN, VN IF ML H BN DVID OF H POIBILIY OF UH DMG. tmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. tmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, tmel products are not suitable for, and shall not be used in, automotive applications. tmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. FY-IIL, MILIY, ND UOMOIV PPLIION DILIM: tmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death ( afety-ritical pplications ) without an tmel officer's specific written consent. afety-ritical pplications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. tmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by tmel as military-grade. tmel products are not designed nor intended for use in automotive applications unless specifically designated by tmel as automotive-grade.