Two-wire Serial EEPROM K ( 1 6, X 8 ) / K ( 3 2, X 8 )

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Feature ajor Power echnology o.,ltd. wowire erial EEP 1 2 8 ( 1 6, 3 8 4 X 8 ) / 2 5 6 ( 3 2, 7 6 8 X 8 ) Lowvoltage peration 1.8 (V = 1.8V to 5.

1 Feature ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) Lowvoltage peration 1.8 (V = 1.8V to 5.5V) perating mbient emperature: 40 to +85 Internally rganized: 16,384 X 8 (128) 32,768 X 8 (256) wowire erial Interface chmitt rigger, Filtered Input for Noie uppreion idirectional Data ranfer Protocol 400 khz (1.8V, 2.7V, 5V) ompatibility Write Protect Pin for Hardware Data Protection 64byte Page (128/256) Write ode Partial Page Write llowed elftimed Write ycle (5 m max) Highreliability Endurance: 1 illion Write ycle Data etention: 100 Year 8lead PDIP, 8lead JEDE I and 8lead P Package General Decription he provide 131,072/262,144 bit of erial electrically eraable and programmable readonly memory (EEP) organized a 16,384/32,768 word of 8 bit each. he device i optimized for ue in many indutrial and commercial application where lowpower and lowvoltage operation are eential. he i available in paceaving 8 lead PDIP, 8lead JEDE I, and 8lead P package and i acceed via a wowire erial interface. In addition, the i available i n 1.8V (1.8V to 5.5V) verion. Pin onfiguration 8lead PDIP 8lead P 8lead I V V V WP WP WP N 3 6 L N 3 6 L N 3 6 L GND 4 5 D GND 4 5 D GND 4 5 D Pin Decription able 1: Pin onfiguration Pin Deignation ype Name and Function 0 1 I ddre Input D I/ & pendrain erial Data L I erial lock Input WP I Write Protect GND P Ground V P Power upply ajor Power ajor Power echnology o.,ltd. ev..2 Feb

2 lock Diagram ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) V GND WP L D P LGI EIL NL LGI EN H.V. PUP/IING LD DEVIE DDE P P D EVEY LD IN 0 1 /W D WD DDE UNE X DEDE EEP Y DE EIL UX DIN DU/ LGI DU ajor Power echnology o.,ltd. ev..2 Feb

3 Pin Decription ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) he 1 and 0 pin are device addre input that are hard wired for the. Four 128k/256k device may be addreed on a ingle bu ytem (device addreing i dicued in detail under the Device ddreing ection). he D pin i bidirectional for erial data tranfer. hi pin i opendrain driven and may be wireed with any number of other opendrain or open collector device. he L input i ued to poitive edge clock data into each EEP device and negative edge clock data out of each device. he ha a Write Protect pin that provide hardware data protection. he Write Protect pin allow normal read/write operation when connected to ground (GND). When the Write Protect pin i connected to V, the write protection feature i enabled and operate a hown in the following able 2. able 2: Write Protect WP Pin tatu t V t GND P24128 Full (128) rray Part of the rray Protected P24256 Full (256) rray Normal ead / Write peration emory rganization he 128 i internally organized a 256 page of 64 byte each. andom word addreing require a 14bit data word addre. he 256 i internally organized a 512 page of 64 byte each. andom word addreing require a 15bit data word addre. ajor Power echnology o.,ltd. ev..2 Feb

4 Device peration ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) he D pin i normally pulled high with an external device. Data on the D pin may change only during L low time period (ee to Figure 1 on page 4). Data change during L high period will indicate a tart or top condition a defined below. hightolow tranition of D with L high i a tart condition which mut precede any other command (ee to Figure 2 on page 4). lowtohigh tranition of D with L high i a top condition. fter a read equence, the top command will place the EEP in a tandby power mode (ee Figure 2 on page 4). ll addree and data word are erially tranmitted to and from the EEP in 8bit word. he EEP end a 0 to acknowledge that it ha received each word. hi happen during the ninth clock cycle. he feature a lowpower tandby mode which i enabled: (a) upon powerup and (b) after the receipt of the P bit and the completion of any internal operation fter an interruption in protocol, power lo or ytem reet, any twowire part can be reet by following thee tep: 1. lock up to 9 cycle. 2. Look for D high in each cycle while L i high. 3. reate a tart condition. Figure 1: Data Validity D L D LE D LE D HNGE Figure 2: tart and top Definition D L P ajor Power echnology o.,ltd. ev..2 Feb

5 Figure 3: utput cknowledge ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) L D IN D U NWLEDGE Device ddreing he 128/256 EEP device all require an 8bit device addre word following a tart condition to enable the chip for a read or write operation (ee to Figure 4 on page 7). he device addre word conit of a mandatory 1, 0 equence for the firt four mot ignificant bit a hown. hi i common to all the erial EEP device. he 128/256 ue the two device addre bit 1, 0 to allow a many a four device on the ame bu. hee bit mut compare to their correponding hardwired input pin. he 1 and 0 pin ue an internal proprietary circuit that biae them to a logic low condition if the pin are allowed to float. he eighth bit of the device addre i the read/write operation elect bit. read operation i initiated if thi bit i high and a write operation i initiated if thi bit i low. Upon a compare of the device addre, the EEP will output a 0. If a compare i not made, the chip will return to a tandby tate. he ha a hardware data prot ection cheme that allow the uer to write protect the entire memory when the WP pin i at V. ajor Power echnology o.,ltd. ev..2 Feb

6 Write peration ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) write operation require two 8bit data word addre following the device addre word and acknowledgment. Upon receipt of thi addre, the EEP will again repond with a 0 and then clock in the firt 8bit data word. Following receipt of the 8bit data word, the EEP will output a 0 and the addreing device, uch a a microcontroller, mut terminate the write equence with a top condition. t thi time the EEP enter an internally timed write cycle, tw, to the nonvolatile memory. ll input are diabled during thi write cycle and the EEP will not repond until the write i complete (ee Figure 5 on page 7). he 128/256 device are capable of 64byte page write. page write i initiated the ame a a byte write, but the microcontroller doe not end a top condition after the firt data word i clocked in. Intead, after the EEP acknowledge receipt of the firt data word, the microcontroller can tranmit up to 63 more data word. he EEP will repond with a 0 after each data word received. he microcontroller mut terminate the page write equence with a top condition (ee Figure 6 on page 7). he data word addre lower ix (128/256) bit are internally incremented following the receipt of each data word. he higher data word addre bit are not incremented, retaining the memory page row location. When the word addre, internally generated, reache the page boundary, the following byte i placed at the beginning of the ame page. If more than 64 data word are tranmitted to the EEP, the data word addre will roll over and previou data will be overwritten. nce the internally timed write cycle ha tarted and the EEP input are diabled, acknowledge polling can be initiated. hi involve ending a tart condition followed by the device addre word. he read/write bit i repreentative of the operation deired. nly if the internal write cycle ha completed will the EEP repond with a 0, allowing the read or write equence to continue. ead peration ead operation are initiated the ame way a write operation with the exception that the read/write elect bit in the device addre word i et to 1. here are three read operation: current addre read, random addre read and equential read. he internal data word addre counter maintain the lat addre acceed during the lat read or write operation, incremented by one. hi addre tay valid between operation a long a the chip power i maintained. he addre roll over during read i from the lat byte of the lat memory page to the firt byte of the firt page. he addre roll over during write i from the lat byte of the cur rent page to the firt byte of the ame page. nce the device addre with the read/write elect bit et to 1 i clocked in and acknowledged by the EEP, the current addre data word i erially clocked out. he microcontroller doe not repond with an input 0 but doe generate a following top condition (ee Figure 7 on page 8). ajor Power echnology o.,ltd. ev..2 Feb

7 ead peration ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) random read require a dummy byte write equence to load in the data word addre. nce the device addre word and data word addre are clocked in and acknowledged by the EEP, the microcontroller mut generate another tart condition. he microcontroller now initiate a current addre read by ending a device addre with the read/write elect bit high. he EEP acknowledge the device addre and erially clock out the data word. he microcontroller doe not repond with a 0 but doe generate a following top condition (ee Figure 8 on page 8). equential read are initiated by either a current addre read or a random addre read. fter the microcontroller receive a data word, it repond with an acknowledge. long a the EEP receive an acknowledge, it will continue to increment the data word addre and erially clock out equential data word. When the memory addre limit i reached, the data word addre will roll over and the equential read will continue. he equential read operation i terminated when the microcontroller doe not repond with a 0 but doe generate a following top condition (ee Figure 9 on page 8). Figure 4: Device ddre /W L Figure 5: yte Write DEVIE DDE W I E FI WD DDE END WD DDE D P D LINE 0 * L / W L Figure 6: Page Write DEVIE DDE W I E FI WD ( n ) DDE END WD ( n ) DDE D( n ) D( n+x ) P D LINE 0 * L / W L Note: * = DN E bit = DN E bit for the 128 ajor Power echnology o.,ltd. ev..2 Feb

8 Figure 7: urrent ddre ead ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) DEVIE DDE E D D P D LINE 0 L / W N Figure 8: andom ead DEVIE DDE W I E 1t, 2nd WD DDE ( n) DEVIE DDE E D D( n ) P D LINE 0 0 L / W DUY WIE L N Note: = DN E bit = DN E bit for the 128 Figure 9: equential ead DEVIE DDE E D D( n ) D( n+1 ) D( n+2 ) D( n+3 ) P D LINE / W N ajor Power echnology o.,ltd. ev..2 Feb

9 Electrical haracteritic ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) D upply Voltage V to +6.5V tree above thoe lited under "bolute aximum ating" may caue permanent damage to thi device. hee are tre Input / utput Voltage GND0.3V to V+0.3V rating only. Functional operation of thi device at thee or any other condition above thoe indicated in the operational ection perating mbient emperature to +85 of thi pecification i not implied or intended. Expoure to the abolute maximum rating condition for extended period may torage emperature to +150 affect device reliability. D Electrical haracteritic pplicable over recommended operating range from: = 40? to +85?, V = +1.8V to +5.5V (unle otherwie noted) Parameter ymbol in. yp. ax. Unit ondition upply Voltage V V upply Voltage V V upply Voltage V V upply Voltage V V upply urrent V = 5.0V I m ED at 400 khz upply urrent V = 5.0V I m WIE at 400 khz upply urrent V = 1.8V I VIN = V or V upply urrent V = 2.5V I VIN = V or V upply urrent V = 2.7V I VIN = V or V upply urrent V = 5.0V I VIN = V or V Input Leakage urrent ILI VIN = V or V utput Leakage urrent IL VU = V or V Input Low Level VIL 0.6 V X 0.3 V Input High Level VIH V X 0.7 V V utput Low Level V =5.0V VL3 0.4 V IL = 3.0 m utput Low Level V =3.0V VL2 0.4 V IL = 2.1 m utput Low Level V =1.8V VL1 0.2 V IL = 0.15 m Pin apacitance pplicable over recommended operating range from = 25, f = 1.0 Hz, V = +1.8V Parameter ymbol Input/utput apacitance (D) I/ Input apacitance (0, 1, L) IN in. yp. ax. 8 6 Unit pf pf VI/ = 0V VIN = 0V ondition ajor Power echnology o.,ltd. ev..2 Feb

10 Electrical haracteritic pplicable over recommended operating range from = 40 to +85, V = +1.8V to +5.5V, L = 1 L Gate and 100 pf (unle otherwie noted) Parameter lock Frequency, L lock Pule Width Low lock Pule Width High Noie uppreion ime lock Low to Data ut Valid ajor Power echnology o.,ltd. wowire erial EEP ymbol fl tlw thigh ti t ( 1 6, X 8 ) / ( 3 2, X 8 ) in. 1.8volt yp ax volt in. yp. ax Unit khz n ime the bu mut be free before a new tranmiion can tart tuf tart Hold ime thd tart etup ime tu Data In Hold ime thd.d 0 0 Data In etup ime tu.d n Input ie ime t Input Fall ime tf n top etup ime tu Data ut Hold ime tdh n Write ycle ime tw 5 5 m 5.0V, 25, yte ode Endurance 1 Write ycle Note 1. hi parameter i characterized and i not 100% teted. 2. meaurement condition: L (connect to V): 1.3 k (2.5V, 5V), 10 k (1.8V) Input pule voltage: 0.3 V to 0.7 V Input rie and fall time: 50 n Input and output timing reference voltage: 0.5 V he value of L hould be concerned according to the actual loading on the uer' ytem. ajor Power echnology o.,ltd. ev..2 Feb

11 u iming ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) Figure10:L:eriallock,D:erialDataI/ t F t HIGH t L t LW t LW t U. t HD. t HD.D t U.D t U. D_IN t t DH t UF D_U Write ycle iming Figure11:L:eriallock,D:erialDataI/ L D 8th I t W (1) P NDIIN NDIIN Note 1. he write cycle time tw i the time from a valid top condition of a write equence to the end of the internal clear/write cycle. ajor Power echnology o.,ltd. ev..2 Feb

12 rdering Information ajor Power echnology o.,ltd. wowire erial EEP ( 1 6, X 8 ) / ( 3 2, X 8 ) Part Number o= (lank) = om emp(0 70 ) lank = tandard npb plating 24: wowire (I2) Interface I = Ind emp(40 85 ) G = EP(oH compliant) D = DIP E = Exp emp( ) = P =2.7~ =128 bit = P = ube =1.8~ =256 bit W = Wafer/die = ape & eel Product Dataheet hange Notice Dataheet eviion Hitory Verion ontent Date 2.0 Dataheet Feb., 2008 ajor Power echnology o.,ltd. ev..2 Feb

16-Bit D-Type Flip-Flop with 3-State Outputs. Product Features. Product Description. Logic Block Diagram

16-Bit D-Type Flip-Flop with 3-State Outputs. Product Features. Product Description. Logic Block Diagram 123468901234689012346890121234689012346890123468901212346890123468901234689012123468901234689012346890121234689012 with 3-State Product Feature The PI4CX Family i deigned for low voltage operation, = 8