SRM2264L10/12 CMOS 64K-BIT STATIC RAM. Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous DESCRIPTION

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1 DESCRIPTION SRM2264L10/12 CMOS 64K-BIT STATIC RAM Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous The SRM2264L10/12 is an 8,192-word 8-bit asynchronous, static, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible, and the three-state output allows easy expansion of memory capacity. FEATURES Fast access time SRM2264L ns (Max) SRM2264L ns (Max) Low supply current Standby : 0.5µA (Typ) Operation : 47mA (Typ) ns 45mA (Typ) ns Completely static No clock required Single power supply V ± 10% TTL compatible inputs and outputs Three-state output with wired-or capability Non-volatile storage with back-up batteries Package SRM2264L10/ DIP-28 pin (plastic) SRM2264LM10/ SOP2-28 pin (plastic) SRM2264LTM10/ TSOP (I)-28 pin (plastic) BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Address Buffer 7 6 X Decoder Y Decoder Memory Cell Array 128 x 64 x 8 64 x 8 Column Gate, Chip Control 8 OE OE, Chip Control I/O Buffer I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O MEM- 33

2 PIN CONFIGURATION PIN DESCRIPTION A0 to A12 Address Input NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 V SS SRM2264L V DD A8 A9 A11 OE A10 I/O8 I/O7 I/O6 I/O5 I/O4 OE, I/O1 to 8 VDD VSS NC Write Enable Output Enable Chip Select Data Input/Output Power Supply (+5V) Power Supply (0V) No Connection ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Ratings Unit Supply voltage VDD 0.5 to 7.0 V Input voltage* VI 0.5 to 7.0 V Input/Output voltage* VI/O 0.5 to VDD V Power dissipation PD W Operating temperature TOPR 0 to 70 C Storage temperature TSTG 65 to 150 C Soldering temperature and time TSOL 260 C, 10s (at lead) *VI, VI/O (Min) = 3V (Pulse width is 50ns) RECOMMENDED DC OPERATING CONDITIONS (VSS = 0V, Ta = 0 to 70 C) Parameter Symbol Min Typ Max Unit Supply voltage Input voltage VDD V VSS V VIH VDD V VIL 0.3* V * If pulse width is less than 50ns, it is V MEM-

3 ELECTRICAL CHARACTERISTICS DC Electrical Characteristics (VDD = 5V ± 10%, VSS = 0V, Ta = 0 to 70 C) Parameter Symbol Conditions SRM2264L10 SRM2264L12 Min Typ* Max Min Typ* Max Unit Input leakage current Standby supply current ILI VI = 0 to VDD µa IDDS = VIH or = VIL ma IDDS1 = VDD 0.2V or 0.2V µa Average operating current IDDA VI = VIL, VIH II/O = 0mA, tcyc = Min ma Operating supply current IDDO VI = VIL, VIH II/O = 0mA ma Output leakage ILO = VIH or = VIL or = VIL or OE = VIH, µa VI/O = 0 to VDD High level output voltage VOH IOH = ma 2.4 VDD VDD 0.1 V Low level output voltage VOL IOL = 4.0mA V * Typical values are measured at Ta = 25 C and VDD = 5.0V Terminal Capacitance (f = 1MHz, Ta = 25 C) Parameter Symbol Conditions Min Typ Max Unit Address capacitance CADD VADD = 0V 3 5 pf Input capacitance CI VI = 0V 5 6 pf I/O capacitance CI/O VI/O = 0V 6 7 pf MEM- 35

4 AC Electrical Characteristics Read Cycle (VDD = 5V ± 10%, VSS = 0V, Ta = 0 to 70 C) Parameter Symbol Test Conditions SRM2264L10 SRM2264L12 Min Max Min Max Read cycle time trc ns Address access time tacc ns access time ta * ns access time ta ns OE access time toe ns output set time tclz ns output floating time tchz ns output set time tclz ns *2 output floating time tchz ns OE Output set time tolz 5 5 ns OE Output floating time tohz ns Output hold time toh * ns Unit Write Cycle (VDD = 5V ± 10%, VSS = 0V, Ta = 0 to 70 C) Parameter Symbol Test SRM2264L10 SRM2264L12 Conditions Min Max Min Max Unit Write cycle time twc ns Chip select time 1 tcw ns Chip select time 2 tcw ns Address enable time taw ns Address setup time tas *1 0 0 ns Write pulse width twp ns Address hold time twr 0 0 ns Input data setup time tdw ns Input data hold time tdh 0 0 ns Output floating twhz ns *3 Output setup time tow 5 5 ns * See next page for test condtions MEM-

5 *1 Read/Write Cycle Test Conditions 1. Input pulse level: 0.8V to 2.4V 2. tr = tf = 10ns 3. Input and output timing reference levels: 4. Output load ITTL + CL = 100pF *2 Read Cycle Test Conditions 1. Input pulse level: 0.8V to 2.4V 2. tr = tf = 10ns 3. Test Circuit V DD To scope SW1 Test: tchz1, tchz2, tohz Both SW1 and SW2 are closed. Test: tclz1, tclz2, tolz Hi-Z H SW1 is open, SW2 is closed. Test: tclz1, tclz2, tolz Hi-Z L SW1 is closed, SW2 is open. Output turn-on turn-off times To output terminal 5 pf 1 kω 300Ω OE tolz H H I/O Hi-Z L L 0.5V t OHZ Hi-Z tclz1 t CHZ1 Include scope, test, tool capacity V SS V SS SW2 I/O Hi-Z tclz2 H H L L 0.5V t CHZ2 Hi-Z *3 Write Cycle Test Conditions 1. Input pulse level: 0.8V to 2.2V 2. tr = tf = 10ns 3. Test Circuit V DD Test: tow, twhz Hi-Z H and H Hi-Z SW is VDD side Test: tow, twhz Hi-Z L and L Hi-Z SW is VSS side Output turn-on turn-off times To scope 300Ω To output terminal SW tow I/O Hi Z 0.1V 0.1V H L t WHZ 0.1V Hi Z 0.1V 5 pf 1 kω Include scope, test, tool capacity V SS V SS MEM- 37

6 Timing Charts Read Cycle*1 ADDRESS t RC OE t CLZ1 t ACC t A t A t CLZ2 t OH t CHZ1 t CHZ2 Dout t OLZ t OE t OHZ Note: *1. During the read cycle, must be H. Write Cycle (1) ( Control)*2 ADDRESS t WC t AW t CW1 t WR t AS Dout t DW t DH Din Note: *2. During write cycle (1) and (2), the Output Buffer is in high impedance regardless of the OE level MEM-

7 Write Cycle (2) ( Control)*2 ADDRESS t WC t AW t WR t AS t CW2 Dout Din t DW t DH Note: *2. During write cycle (1) and (2), the Output Buffer is in high impedance regardless of the OE level. Write Cycle (3) ( Control)*3 ADDRESS t WC t AW t WR t AS t WP Dout t WHZ t OW Din t DW t DH Note: *3. During write cycle (3), the Output Buffer is in high impedance if the OE level is H MEM- 39

8 DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POR SUPPLY (Ta = 0 to 70 C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDR V Data retention current IDDR VDD = 3V = VDD 0.2V or 0.2V 10 µa Chip select data hold time tcdr 0 ns Operation recovery time tr trc* ns * trc = Read Cycle time Data Retention Timing ( Control) Data hold mode V DD t CDR 2.2V 4.5V V DDR 2.0V 4.5V V DD 0.2V t R 2.2V Data Retention Timing ( Control) V DD Data hold mode t CDR t R 0.4V 0.4V 4.5V V DDR 2.0V 4.5V 0.2V MEM-

9 FUNCTIONS Truth Table OE A0 to A12 Data I/O Mode IDD H X Hi-Z Unselected IDDS, IDDS1 L Hi-Z Unselected IDDS, IDDS1 L H X L Stable Input data Write IDDO L H L H Stable Output data Read IDDO L H H H Stable Hi-Z Output disable IDDO X: H or L : H, L, or Hi-Z Read Data Data is able to be read when the address is set while holding = L, = H, OE= L and = H. Since Data I/O terminals are high impedance state when OE= H, the data bus line can be used for any other objective, then access time apparently is able to be cut down. Write Data There are four ways of writing data into memory (see Timing Charts, above): 1. Hold = H, = L set addresses and give L pulse to. 2. Hold = L, = L set addresses and give H pulse to. 3. Hold = L, = H set addresses and give L pulse to. 4. After setting addresses, give L pulse to, and give H pulse to. Anyway, data on the Data I/O terminals are latched up into the SRM2264L10/12 at the end of the period that, are L level, and is H level. As Data I/O terminals are in high impedance state when any of, OE= H, or = L, the contention on the data bus can be avoided. Standby Mode When is H or is L level, the SRM2264L10/12 is in the standby mode which has data retaining operation. In this case Data I/O terminals are Hi Z, and all inputs of addresses,. When and level are in the range over VDD 0.2V, or level is in the range under 0.2V, in the SRM2264L10/12 there is almost no current flow except through the high resistance parts of the memory MEM- 41

10 PACKAGE DIMENSIONS Plastic DIP-28pin Unit: Inches (mm) Max (37.4Max) ± (36.7 ± 0.1 ) ± (13.4 ± 0.1 ) ± (2.54 ± 0.25 ) (1.5 ) ± (0.46 ± 0.1 ) ± (0.6 ± 0.1 ) ± (4.6 ± 0.1 ) Min (3.0 Min) (15.24) 0.600~0.655 (15.24~16.64) ± (0.25 ± 0.03 ) 0.01 Plastic SOP2-28pin* Unit: Inches (mm) Max (18.1 Max) ± (17.8 ± 0.1 ) ± (8.4 ± 0.1 ) ± (11.8 ± 0.3 ) ± (2.5 ± 0.15 ) ± (0.15 ± 0.05 ) (9.4) (2.7) (1.27) ± (0.4 ± 0.1 ) (0.2) () * SRM2264LM10/12 has the same electrical characteristics as SRM2264L10/ MEM-

11 CHARACTERISTIC CURVES 1.1 Normalized I DDA T a V DD = 5.5V T cyc = Min 0.9 Normalized I DDA t cycle V DD = 5.5V Ta = 25 C 1.2 Normalized I DDA V DD ( C) ,000 (ns) Ta = 25 C T cyc = Min (V) 10 5 Normalized I DDS1 Ta V DD = 5.5V CS = V DD 0.2V Normalized I DDS1 V DD Ta = 25 C CS = V DD 0.2V (ma) I OH V OH V DD = 4.5V Ta = 25 C ( C) (V) (V) 1.1 Normalized t ACC t ACS Ta V DD = 4.5V C L = 100pF 1.2 Normalized t ACC t ACS V DD Ta = 25 C C L = 100pF (ma) V DD = 4.5V Ta = 25 C I OL V OL ( C) (V) (V) MEM- 43

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HM6264A Series. Features. Ordering Information word 8-bit High Speed CMOS Static RAM

HM6264A Series. Features. Ordering Information word 8-bit High Speed CMOS Static RAM 8192-word 8-bit High Speed CMOS Static RAM Features Low-power standby 0.1 mw (typ) 10 µw (typ) L-/LL-version Low power operation 15 mw/mhz (typ) Fast access time l00/120/ (max) Single +5 V supply Completely