2.5V/3V, 3.0GHz CML AnyGate ANY LOGIC
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1 .5V/3V, 3.0GHz CML nygate NY LOGIC w/ or OUTPUT uperlite FINL FETURE Guaranteed C parameters over temperature: f MX > 3.0GHz () t r /t f < 00ps Propagation delay < 80ps Guaranteed operation over 40 C to +85 C temperature range Wide supply voltage range:.3v to 3.6V ingle IC provides 8 logic functions : MUX capability Fully differential I/O ource terminated CML outputs for fast edge rates: for load for load Guaranteed matched propagation delays: elect ()-to-out: < 80ps Input ( and )-to-out: < 80ps ccepts PECL, LVPECL, CML input signals Functions as a PECL/LVPECL-to-CML translator vailable in a 0-pin (3mm 3mm) MOP package DECRIPTION The and are highly flexible, universal logic gates capable of up to 3.0GHz operation (). These nygate differential logic devices will produce all possible logic functions of two oolean variables. They can be configured as any of the following gates: ND, NND, OR, NOR, XOR, XNOR, DELY, NEGTION (NOT). The and can also function as a -input multiplexer. The has an output stage optimized for loads, and the is optimized for loads. The differential inputs for both devices are normally terminated with a single resistor () between the true and complement pins. PPLICTION Port bypass Data communication systems Wireless communication systems Telecom systems PIN CONFIGURTION FUTIONL LOCK DIGRM / 0 VCC 9 / / GND MOP / 0 and PIN NME Pin Function, / CML, PECL, LVPECL Input, / CML, PECL, LVPECL Input, / Differential CML Output, / CML, PECL, LVPECL Input elector GND Ground nygate and uperlite are trademarks of Micrel, Inc. Rev.: mendment: / Issue Date: October 00
2 uperlite PIN DECRIPTION, / CML Input (Differential) This is one of the differential inputs to the logic block. For a -variable logic function, it is either a constant value or a oolean input. For a -input mux, this signal represents the output when is set to logic zero., / CML Input (Differential) This is one of the differential inputs to the logic block. For a -variable logic function, it is either a constant value or a oolean input. For a -input mux, this signal represents the output when is set to logic one., / CML Output (Differential) This is the differential CML output for the logic block. For termination guidelines, see Figure 3., / CML Input (Differential) This differential CML input is one of the inputs to the logic block. It represents either one oolean input for a -variable logic function, or the select input for a -input mux. FUTIONL DECRIPTION Establishing tatic Logic Inputs The true pin of an input pair is internally biased to ground through a 75kΩ resistor. The complement pin of an input pair is internally biased to / through an internal voltage divider consisting of two 75kΩ resistors. ince some logic functions necessitate an output to be connected to two inputs, / inputs have no internal terminations. Typically, one resistor between the true and complement input is all that is required, as per Figure 3. To keep an input at static logic zero at 3.0V, leave both inputs unconnected or tie the complement input to. For < 3.0V applications, connect the complement input to and leave the true input unconnected. To make an input static logic one, connect the true input to, and leave the complement input unconnected. These are the only safe ways to cause inputs to be at a static value. In particular, no input pin should be directly connected to ground. ll (no connect) pins should be unconnected. Input Input /Input /Input Figure. Hard Wiring Logic () NOTE:. Input is either,, input, and /Input is either /, /, / input. For > 3.0V pplications Input VCC /Input For < 3.0V pplications Figure. Hard Wiring Logic 0 ()
3 uperlite TRUTH TLE / / / / ( ) ND/NND ( ) / L L L L H L H L L H L L H L H L H H H L / / / / + ( + ) OR/NOR + (+ ) / L H L L H H H L H L L H H H L H H H H L / / / / ( ) XOR/XNOR ( ) / L H L L H L H H H L H L L H L H L H L H / / / / DELY/NEGTION / L X L L H H X L H L / / / / / X L H L H X H H H L : MUX 0 H L 3
4 uperlite CML TERMINTION ND TTL INTERFCE ll inputs accept the output from any other member of this family. ll outputs are source terminated or CML differential drivers as shown in Figure 3. ll inputs to the / must be externally terminated. / inputs are designed to accept a termination resistor between the true and complement inputs of a differential pair. 040 form factor chip resistors will fit with some trace fanout. 00Ω / / 8m 6m Figure 3a. Load CML Output Figure 3b. Differentially Terminated ( Load CML Output) (TTL Driver) 8m / TTL Driver k k 549Ω /.47k Figure 3c. Differentially Terminated ( Load CML Output) Figure 4. Interfacing TTL-to-CML elect Inputs 4
5 uperlite OLUTE MXIMUM RTING () ymbol Rating Value Unit Power upply Voltage 0.5 to +6.0 V V IN Input Voltage 0.5 to +0.5 V V OUT CML Output Voltage.0 to +0.5 V T Operating Temperature Range 40 to +85 C T store torage Temperature Range 65 to +50 C θ J Package Thermal Resistance till-ir (multi-layer PC) 3 C/W (Junction-to-mbient) 500lfpm (multi-layer PC) 96 C/W θ JC Package Thermal Resistance 4 C/W (Junction-to-Case) NOTE:. Permanent device damage may occur if OLUTE MXIMUM RTING are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to OLUTE MXIMUM RTlNG conditions for extended periods may affect device reliability. DC ELECTRICL CHRCTERITIC T = 40 C to +85 C () ymbol Parameter Min. Typ. Max. Unit Condition Power upply Voltage V I CC Power upply Current 40 m No Load m No Load CML DC ELECTRICL CHRCTERITIC =.3V to 3.6V; GND = 0V; T = 40 C to +85 C () ymbol Parameter Min. Typ. Max. Unit Condition V ID Differential Input Voltage 00 mv V IH Input HIGH Voltage.6 V V IL Input LOW Voltage.5 0. V V OH Output HIGH Voltage V No Load V OL Output LOW Voltage V No Load V OUT Output Voltage wing () V No Load V Load (3) 0.00 V Load (4) () R OUT V Load (5) () Output ource Impedance Ω Ω NOTE:. The DC parameters are guaranteed after thermal equilibrium has been established.. ctual voltage levels and differential swing will depend on customer termination scheme. Refer to the CML Termination diagram for more details. 3. pplies to : 00Ω termination resistor across and /. ee Figure 3a. 4. pplies to the. ee Figure 3c. 5. pplies to the : termination resistor across and /. ee Figure 3b. 5
6 uperlite C ELECTRICL CHRCTERITIC () =.3V to 3.6V; GND = 0V; T = 40 C to +85 C ymbol Parameter Min. Typ. Max. Unit Condition f () MX Max. Operating Frequency.5 GHz 3.0 GHz t PD(-) Propagation Delay ( to ) 350 ps ps t PD Propagation Delay (- and -) (- and -) 350 ps ps t r CML Output Rise/Fall Times t f (0% to 80%) 0 ps ps NOTE:. : outputs terminated to equivalent load. ee Figure 3c. : outputs terminated to load. ee Figure 3b. f MX represents a maximum toggle rate in which the output still meets CML logic swing. PRODUCT ORDERING CODE Ordering Package Operating Package Code Type Range Marking Description UKI K0- Industrial 85U Load UKITR* K0- Industrial 85U Load UKI K0- Industrial 85 Load UKITR* K0- Industrial 85 Load *Tape and Reel. 6
7 uperlite 0 LED MOP (K0-) Rev. 00 MICREL-YNERGY 350 COTT OULEVRD NT CLR C U TEL + (408) FX + (408) WE This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 00 Micrel Incorporated 7
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UNISONIC TECHNOLOGIES CO., LTD U74LVC1G125 BUS BUFFER/LINE DRIVER 3-STATE DESCRIPTION The U74LVC1G125 is a single bus buffer/line driver with 3-state output. When the output enable ( ΟΕ ) is high the output
CD74HC165, CD74HCT165
Data sheet acquired from Harris Semiconductor SCHS156 February 1998 CD74HC165, CD74HCT165 High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register Features [ /Title (CD74H C165, CD74H CT165) /Subject
Standard Products UT54ACS109/UT54ACTS109 Dual J-K Flip-Flops. Datasheet November 2010
Standard Products UT54ACS109/UT54ACTS109 Dual J-K Flip-Flops Datasheet November 2010 www.aeroflex.com/logic FEATURES 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available
SGM7SZ00 Small Logic Two-Input NAND Gate
GENERAL DESCRIPTION The SGM7SZ00 is a single two-input NAND gate from SGMICRO s Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive
74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
74HC1G125; 74HCT1G125
Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
AOZ6135 High Performance, Low R ON, 1Ω SPDT Analog Switch
OZ6135 High Performance, Low R ON, 1Ω PDT nalog witch General Description The OZ6135 is a high performance single-pole double-throw (PDT), low power, TTL-compatible bus switch. The OZ6135 can handle analog
CD74HC151, CD74HCT151
Data sheet acquired from Harris Semiconductor SCHS150 September 1997 CD74HC151, CD74HCT151 High Speed CMOS Logic 8-Input Multiplexer [ /Title (CD74H C151, CD74H CT151) /Subject High peed MOS ogic 8- nput
NL27WZ126. Dual Buffer with 3 State Outputs. The NL27WZ126 is a high performance dual noninverting buffer operating from a 1.65 V to 5.5 V supply.
Dual Buffer with 3 State Outputs The NL27WZ126 is a high performance dual noninverting buffer operating from a 1.65 to 5.5 supply. Features Extremely igh Speed: t PD 2.6 ns (typical) at = 5.0 Designed
Low Voltage 400 MHz Quad 2:1 Mux with 3 ns Switching Time ADG774A
a FEATURE Bandwidth >4 MHz Low Insertion Loss and On Resistance: 2.2 Typical On-Resistance Flatness.3 Typical ingle 3 V/5 upply Operation Very Low istortion:
Standard Products UT54ACS139/UT54ACTS139 Dual 2-Line to 4-Line Decoders/Demultiplexers. Datasheet November 2010
Standard Products UT54ACS9/UT54ACTS9 Dual -Line to 4-Line Decoders/Demultiplexers Datasheet November 00 www.aeroflex.com/logic FEATURES Incorporates two enable inputs to simplify cascading and/or data
MC10EP131, MC100EP V / 5VНECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V / 5VНECL Quad D Flip Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master slaved D flip flop with common set and separate resets. The device is an expansion
CD54/74HC147, CD74HCT147. High Speed CMOS Logic 10-to-4 Line Priority Encoder. Features. [ /Title (CD74 HC147, CD74 HCT14 7) /Subject
CD/7HC7, CD7HCT7 Data sheet acquired from Harris Semiconductor SCHS9B September 997 - Revised March 00 High 0-to- Encoder [ /Title (CD7 HC7, CD7 HCT 7) /Subject (High 0-to- Encode r) /Autho r () /Keywords
Octal bus transceiver; 3-state
Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257
CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 Data sheet acquired from Harris Semiconductor SCHS171D November 1997 - Revised October 2003 High-Speed CMOS Logic Quad 2-Input Multiplexer with Three-State
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368
CD/HC, CD/HCT, CD/HC, CDHCT Data sheet acquired from Harris Semiconductor SCHSD November - Revised October 00 High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting [ /Title
UNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD BUS BUFFER/LINE DRIVER 3-STATE DESCRIPTION The U74LVC1G125 is a single bus buffer/line driver with 3-state output. When the output enable ( ΟΕ ) is high the output will be
74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
CD54/74HC30, CD54/74HCT30
CD/7HC0, CD/7HCT0 Data sheet acquired from Harris Semiconductor SCHSA August 997 - Revised May 000 High Speed CMOS Logic 8-Input NAND Gate [ /Title (CDH C0, CD7H C0, CD7H CT0) /Subject High peed MOS ogic
Dual 3-channel analog multiplexer/demultiplexer with supplementary switches
with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7SG02FU IN A GND
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7SG02FU 2 Input NOR Gate Features High-level output current: I OH /I OL = ±8 ma (min) at = 3.0 High-speed operation: t pd = 2.4 ns (typ.) at
Package Type. IXDD614PI 8-Pin DIP Tube 50 OUT 8-Lead Power SOIC with Exposed Metal Back Tube 100
IXD_64 4-Ampere Low-Side Ultrafast MOSFET Drivers Features 4A Peak Source/Sink Drive Current Wide Operating Voltage Range: 4.V to V - C to +2 C Extended Operating Temperature Range Logic Input Withstands
74AHC125; 74AHCT125. Quad buffer/line driver; 3-state
Rev. 04 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They
MM74HC251 8-Channel 3-STATE Multiplexer
8-Channel 3-STATE Multiplexer General Description The MM74HC251 8-channel digital multiplexer with 3- STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and
PI5A3158. SOTINY TM Low Voltage Dual SPDT An a log Switch 2:1 Mux/DeMux Bus Switch. Features. Description. Connection Diagram.
PI53158 OINY M Low Voltage Dual PD n a log witch Features CMO echnology for Bus and nalog pplications Low On-Resistance: 8Ω at 3.0V Wide Range: 1.65V to 5.5V Rail-to-Rail ignal Range Control Input Overvoltage
UNISONIC TECHNOLOGIES CO., LTD
U74LC1G04 UNISONIC TECHNOLOGIES CO., LTD SINGLE INERTER GATE DESCRIPTION The UTC U74LC1G04 is a single inverter gate, it provides the function Y = A. This device has power-down protective circuit, preventing
54AC258 54ACT258 Quad 2-Input Multiplexer with TRI-STATE Outputs
54AC258 54ACT258 Quad 2-Input Multiplexer with TRI-STATE Outputs General Description The AC/ ACT258 is a quad 2-input multiplexer with TRI-STATE outputs. Four bits of data from two sources can be selected
74LV General description. 2. Features. 8-bit addressable latch
Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed