DG3157. High-Speed, Low R ON, SPDT Analog Switch. Vishay Siliconix. (2:1 Multiplexer/Demultiplexer Bus Switch) DESCRIPTION FEATURES

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1 High-peed, Low R ON, PDT nalog witch (2:1 Multiplexer/Demultiplexer Bus witch) DG3157 DECRIPTION The DG3157 is a high-speed single-pole double-throw, low power, TTL-Compatible bus switch. Using sub-micro CMO technology, the DG3157 achieves low on-resistance and negligible propagation delay. The DG3157 can handle both analog and digital signals and permits signals with amplitudes of up to V CC to be transmitted in either direction. When the elect pin is low, B 0 is connected to the output pin. When the elect pin is high, B 1 is connected to the output pin. The path that is open will have a highimpedance state with respect to the output. Make-beforebreak is guaranteed. n eptiaxial layer prevents latch-up. FETURE Halogen-free ccording to IEC Direct cross to industry standard N74LVC1G3157, NC7B3157, NLB3175, Pl53157, and TG3157 C-70 6-lead package 1.65 V to 5.5 V V CC operation 5 Ω connection between ports Minimal propagation delay Break-before-make switching Zero bounce in flow-through mode FUNCTIONL BLOCK DIGRM ND PIN CONFIGURTION C-70 6-Pin B B Top View Device Marking: G1 TRUTH TBLE Logic Input () Function 0 B 0 Connected to 1 B 1 Connected to ORDERING INFORMTION Temp. Range Package Part Number - 40 C to 85 C C-70-6 DG3157DL-T1-E3 DG3157DL-T1-GE3 (Halogen-free) 1

2 BOLUTE MXIMUM RTING Parameter Limit Unit Reference to to + 6,, B a to ( + 0.3) V Continuous Current (ny terminal) ± 50 Peak Current (Pulsed at 1 ms, 10 % duty cycle) ± 200 m torage Temperature D uffix - 65 to 150 C Power Dissipation (Packages) b 6-Pin C-70 c 250 mw Notes: a. ignals on, or B or exceeding will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. ll leads welded or soldered to PC board. c. Derate 3.1 mw/ C above 70 C. PECIFICTION Parameter DC Characteristics ymbol Test Conditions Unless Otherwise pecified = 3.0 V, V = 0.25 V to 0.7 e Temp. a Limits - 40 C to 85 C Min. b Typ. c Max. b = 1.65 to 1.95 V 0.75 High Level Input Voltage V H = 2.3 to 5.5 V 0.7 = 1.65 to 1.95 V 0.25 Low Level Input Voltage V L = 2.3 to 5.5 V 0.3 V BN = 0 V, I = 30 m 6 7 On Resistance R ON = 4.5 V = 3.0 V = 2.3 V = 1.65 V On Resistance Flatness R FLT 0 < V BN < On Resistance Matching Between Channels ΔR ON Input Leakage Current I = 5.5 V, V = 5.5 V Off tage witch Leakage I BN(off) = 5.5 V, V /V B = 0 V/5.5 V On tate witch Leakage I BN(on) = 5.5 V, V /V B = 0 V/5.5 V V BN = 2.3 V, I = - 30 m 6 12 V BN = 4.5 V, I = - 30 m 9 15 V BN = 0 V, I = 24 m 8 9 V BN = 3.0 V, I = - 24 m V BN = 0 V, I = 8 m 9 12 V BN = 2.3 V, I = - 8 m V BN = 0 V, I = 4 m V BN = 1.8 V, I = - 4 m = 4.5 V, I = - 30 m 6 = 3.0 V, I = - 24 m 12 = 2.3 V, I = - 8 m 22 = 1.65 V, I = - 4 m 90 = 4.5 V, V BN = 3.15 V, I = - 30 m 0.32 = 3.0 V, V BN = 2.1 V, I = - 24 m 0.31 = 2.3 V, V BN = 1.6 V, I = - 8 m 0.30 = 1.65 V, V BN = 1.15 V, I = - 4 m Unit V Ω µ 2

3 PECIFICTION Parameter ymbol Test Conditions Unless Otherwise pecified = 3.0 V, V = 0.25 V to 0.7 e Temp. a Limits - 40 C to 85 C Min. b Typ. c Max. b Power upply Power upply Range V Quiescent upply Current I+ = 5.5 V, V = V B = or 1 10 µ C Electrical Characteristice Prop Delay Time f t PHL /t PLH V = 0 V Output Enable Time f t PZL /t PZH V LOD = 2 x for t PZL V LOD = 0 V for t PZH Output Disable Time f t PLZ /t PHZ V LOD = 2 x for t PLZ V LOD = 0 V for t PHZ = 1.65 to 1.95 V = 2.3 to 2.7 V 1.2 = 3.0 to 3.6 V 0.8 = 4.5 to 5.5 V 0.3 = 1.65 to 1.95 V = 2.3 to 2.7 V = 3.0 to 3.6 V = 4.5 to 5.5 V = 1.65 to 1.95 V = 2.3 to 2.7 V = 3.0 to 3.6 V = 4.5 to 5.5 V = 1.65 to 1.95 V 0.5 Break-Before-Make Time d t BBM = 2.3 to 2.7 V 0.5 = 3.0 to = 4.5 to 5.5 V 0.5 Charge Injection d Q C L = 0.1 nf, V GEN = 0 V = 5 V 7 R GEN = 0 Ω = 3.3 V 3 pc nalog witch Characteristics Off Isolation d OIRR R L = 50 Ω, f = 10 MHz Crosstalk d X TLK db - 3 db Bandwidth d BW R L = 50 Ω > 250 MHz Capacitance Control Pin Capacitance d C IN = 0 V 4.9 B Port Off Capacitance d C IO-B < 6.5 pf Port Capacitance When = 5 V witch Enable d C IO-(on) < 18.5 Notes: a. = 25 C, = as determined by the operating suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for design aid only, not guaranteed nor subject to production testing. d. Guarantee by design, nor subjected to production test. e. V IN = input voltage to perform proper function. f. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch. Unit ns tresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3

4 LOGIC DIGRM Positive Logic B 1 B 0 Figure 1. TYPICL CHRCTERITIC 25 C, unless otherwise noted R ON On Resistance (Ω) = 1.65 V, I = 4 m = 2.3 V, I = 8 m = 3.0 V, I = 24 m = 4.5 V, I = 30 m V (V) R ON vs. V vs. 4

5 C LODING ND WVEFORM V LD From Output Under Test C L 50 pf R L 500 Ω R L 500 Ω W Open TET t PLH /t PHL t PLZ /t PZL t PHZ /t PZH W Open V LD Load Circuit Figure 2. C Test Circuit t r = 2.5 ns witch Input 1.5 V 1.5 V 10 % 10 % t w t PL H 90 % 90 % t PH L t f = 2.5 ns 3.0 V t f = 2.5 ns Logic Input 90 % 90 % 1.5 V 1.5 V t PZ L 10 % 10 % t r = 2.5 ns t PL Z 3.0 V V LD 2 Output 1.5 V 1.5 V V OH Output W aveform 1 W at V LD t PZ H 1.5 V t PH Z V OL V V OL V OH V OL Output W aveform 2 W at 1.5 V V OH 0.3 V 0 V Propagation Delay T imes Enable and Disable T ime-low- and High-Level Enabling Figure 3. C Waveforms Notes: C L includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. ll input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 Ω. The outputs are measured one at a time with one transition per measurement. t PLZ and t PHZ are the same as t dis. t PZL and t PZH are the same as t dis. t PLH and t PHL are the same as t dis. V LD = 2. 5

6 TET CIRCUIT Logic Input V H t r < 5 ns t f < 5 ns B 1 B 1 V O V L B 0 B 0 R L 50 Ω C L 35 pf VB 0 = V B 1 V O 90 % witch Output 0 V t D t D C L (includes fixture and stray capacitance) Figure 4. Break-Before-Make Interval V gen + R gen V IN = 0 B X V OUT C L = 1 nf V V On OUT Off Q = OUT x C L On Figure 5. Charge Injection IN depends on switch configuration: input polarity determined by sense of switch. 10 nf 10 nf B X 0 V, 2.4 V R L COM 0 V, 2.4 V B X Meter HP4192 Impedance nalyzer or Equivalent nalyzer Off I sol a ti on = 20 l o g V V Bx f = 1 MHz Figure 6. Off-Isolation Figure 7. Channel Off/On Capacitance maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for ilicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?

7 Package Information e b e 1 D E 1 E -B c L Dim Min Nom Max Min Nom Max b c D E E e 0.65BC 0.026BC e L Nom 7 Nom 1 ECN: Rev. B, 09-Jul-01 DWG: 5550 Document Number: Jul-01 1

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