NLAS3158. Low Voltage Dual SPDT Analog Switch Dual 2:1 Multiplexer

Transcription

1 Low Voltage Dual PDT nalog witch Dual 2:1 Multiplexer The NL3158 is an advanced CMO analog switch fabricated with silicon gate CMO technology. It achieves very low propagation delay and RD ON resistances while maintaining CMO low power dissipation. nalog and digital voltages that may vary across the full power supply range (from to ). This device is a drop in replacement for the PI The select pin has overvoltage protection that allows voltages above, up to V to be present on the pin without damage or disruption of operation of the part, regardless of the operating voltage. Features High peed: t PD = 1. ns (Typ) at = V Low Power Dissipation: I CC = 1. (Max) at T = 25 C tandard CMO Logic Levels High Bandwidth, Improved Linearity Low RD ON : 8 Max at 3 V Break Before Make Circuitry, Prevents Inadvertent horts This is a Pb Free Device Typical pplications witches tandard NTC/PL Video, udio, PDIF and HDTV May be used for Clock witching, Data MUX ing, etc. Can witch Balanced ignal Pairs, e.g. LVD 2 Mb/s WDFN MN UFFIX CE 485G MRKING DIGRM M 1 = pecific Device Code M = Date Code = Pb Free Package (Note: Microdot may be in either location) elect Input L H 1 1 FUNCTION TBLE Function B Connected to B1 Connected to Important Information Latchup Performance Exceeds 3 m Pin for Pin Drop in for PI53158 WDFN Package, 3x1 mm ED Performance: Human Body Model; 2 V; Machine Model; 2 V Extended utomotive Temperature Range 55 C to +5 C (ee ppendix ) B B 1 1B 5 8 1B Figure 1. Pinout (Top View) ORDERING INFORMTION ee detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. emiconductor Components Industries, LLC, 215 November, 215 Rev. 2 1 Publication Order Number: NL3158/D

2 MXIMUM RTING Rating ymbol Value Unit upply Voltage to + V DC witch Input Voltage (Note 1) V I to + V DC Input Voltage (Note 1) V IN to + V DC Input Diode V IN V I IK 5 m DC Output Current I OUT 8 m DC or Ground Current I CC /I + m torage Temperature Range T stg 65 to +15 C Junction Temperature Under Bias T J 15 C Junction Lead Temperature (oldering, econds) T L 26 C Power +85 C P D 18 mw tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. RECOMMENDED OPERTING CONDITION (Note 2) Characteristic ymbol Min Max Unit upply Voltage Operating V elect Input Voltage V IN V witch Input Voltage V I V Output Voltage V OUT V Operating Temperature T C Input Rise and Fall Time Control Input = 2.3 V 3.6 V Control Input = 4.5 V 5.5 V t r, t f Thermal Resistance J 35 C/W Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 2. elect input must be held HIGH or LOW, it must not float. ns/v 2

3 DC ELECTRICL CHRCTERITIC (T = 4 C to +85 C) ymbol Parameter Test Conditions V IH HIGH Level Input Voltage (V) T = +25C T = 4C to +85C Min Typ Max Min Max Unit.75.7 V V IL LOW Level Input Voltage I IN Input Leakage Current V IN 5.5 V I OFF R ON I CC R RNGE R ON R flat OFF tate Leakage Current witch On Resistance (Note 3) Quiescent upply Current ll Channels ON or OFF, B V IN = V, I O = 3 m V IN = 2.4 V, I O = 3 m V IN = 4.5 V, I O = 3 m V IN = V, I O = 24 m V IN = 3 V, I O = 24 m V IN = V, I O = 8 m V IN = 2.3 V, I O = 8 m V IN = V, I O = 4 m V IN = 1.65 V, I O = 4 m V IN = or I OUT = V nalog ignal Range V On Resistance Over ignal Range (Note 3) (Note 7) On Resistance Match Between Channels (Note 3) (Note 4) (Note 5) On Resistance Flatness (Note 3) (Note 4) (Note 6) I = 3 m, V Bn I = 24 m, V Bn I = 8 m, V Bn I = 4 m, V Bn I = 3 m, V Bn = 3.15 I = 24 m, V Bn = 2.1 I = 8 m, V Bn = 1.6 I = 4 m, V Bn = 1.15 I = 3 m, V Bn I = 24 m, V Bn I = 8 m, V Bn I = 4 m, V Bn Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Measured by the voltage drop between and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two ( or B Ports). 4. Parameter is characterized but not tested in production. 5. R ON = R ON max R ON min measured at identical, temperature and voltage levels. 6. Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions. 7. Guaranteed by Design

4 C ELECTRICL CHRCTERITIC (T = 4 C to +85 C) ymbol Parameter Test Conditions (V) T = +25C T = 4C to +85C Min Typ Max Min Max Unit Figure Number t PHL t PLH Propagation Delay Bus to Bus (Note 9) V I = OPEN ns Figures 2, 3 t PZL t PZH t PLZ t PHZ t BBM Q Output Enable Time Turn On Time ( to B n ) Output Disable Time Turn Off Time ( Port to B Port) Break Before Make Time (Note 8) Charge Injection (Note 8) OIRR Off Isolation (Note ) NO OIRR Off Isolation (Note ) NC V I = 2 for t PZL V I = V for t PZH V I = 2 for t PLZ V I = V for t PHZ R L = 5 C L = 35 pf C L =.1 nf, V GEN = V R GEN = R L = 5 f = MHz R L = 5 f = MHz Xtalk Crosstalk R L = 5 f = MHz ns ns Figures 2, 3 Figures 2, 3 ns Figure 4 pc Figure db Figures 6, db Figures 6, db Figure 7 BW 3 db Bandwidth R L = MHz Figures, 15 THD Total Harmonic Distortion (Note 8) R L = 6 V P P f = 6 Hz to 2 khz % Figure 11 CPCITNCE (Note 11) ymbol Parameter Test Conditions Typ Max Unit C IN elect Pin Input Capacitance = V 2.3 pf Figure Number C IO B B Port Off Capacitance = V 6.5 pf Figure 8 C IO ON Port Capacitance when witch is Enabled = V 18.5 pf Figure 9 8. Guaranteed by Design. 9. This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and the 35 pf load capacitance, when driven by an ideal voltage source (zero output impedance)..off Isolation = 2 log [V /V Bn ]. 11. T = +25 C, f = 1 MHz, Capacitance is characterized but not tested in production. 4

5 PPENDIX DC ELECTRICL EXTENDED UTOMOTIVE TEMPERTURE RNGE CHRCTERITIC (Note 14) ymbol Parameter Test Conditions V IH V IL HIGH Level Input Voltage LOW Level Input Voltage (V) T = +25C T = 55C to +5C Min Typ Max Min Max Unit.75.7 V.25.3 V I IN Input Leakage Current V IN 5.5 V I OFF R ON I CC OFF tate Leakage Current witch On Resistance (Note ) Quiescent upply Current ll Channels ON or OFF, B V IN = V, I O = 3 m V IN = 2.4 V, I O = 3 m V IN = 4.5 V, I O = 3 m V IN = V, I O = 24 m V IN = 3 V, I O = 24 m V IN = V, I O = 8 m V IN = 2.3 V, I O = 8 m V IN = V, I O = 4 m V IN = 1.65 V, I O = 4 m V IN = or I OUT = nalog ignal Range V R RNGE On Resistance Over ignal Range (Note ) (Note ) I = 3 m, V Bn I = 24 m, V Bn I = 8 m, V Bn I = 4 m, V Bn Measured by the voltage drop between and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two ( or B Ports)..Guaranteed by Design. 14.For R ON, R FLT see 4 C to +85 C section. 5

6 PPENDIX C ELECTRICL EXTENDED UTOMOTIVE TEMPERTURE RNGE CHRCTERITIC ymbol Parameter Test Conditions t PHL t PLH Propagation Delay Bus to Bus (Note 16) V I = OPEN (V) T = +25C T = 55C to +5C Min Typ Max Min Max Unit ns Figure Number Figures 2, 3 t PZL t PZH t PLZ t PHZ t B M Output Enable Time Turn On Time ( to B n ) Output Disable Time Turn Off Time ( Port to B Port) Break Before Make Time (Note 15) V I = 2 for t PZL V I = V for t PZH V I = 2 for t PLZ V I = V for t PHZ ns ns Figures 2, 3 Figures 2, 3 ns Figure 4 15.Guaranteed by Design. 16.This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and the 5 pf load capacitance, when driven by an ideal voltage source (zero output impedance). 6

7 C LODING ND WVEFORM V I RU NOTE: Input driven by 5 source terminated in 5 NOTE: C L includes load and stray capacitance NOTE: Input PRR = 1. MHz; t W = 5 ns FROM OUTPUT UNDER TET C L RD Figure 2. C Test Circuit t r = 2.5 ns WITCH INPUT 9% 9% 5% 5% t f = 2.5 ns t f = 2.5 ns ELECT INPUT % 9% 9% 5% 5% t r = 2.5 ns % % t W % t PZL t PLZ V TRI t PLH t PHL V OH OUTPUT 5% V OL +.3 V OUTPUT 5% 5% V OL OUTPUT t PZH t PHZ 5% V OL V OH V OH.3 V V TRI Figure 3. C Waveforms V IN B V OUT LOGIC INPUT B 1 R L C L V OUT.9 V OUT LOGIC INPUT t D Figure 4. Break Before Make Interval Timing 7

8 C LODING ND WVEFORM R GEN B N V OUT LOGIC INPUT OFF ON OFF V GE R L 1 M C L pf V OUT V OUT LOGIC INPUT Q = (V OUT )(C L ) Figure 5. Charge Injection Test nf nf 5 LOGIC INPUT V or V IH ignal Generator dbm B B 1 5 nalyzer 5 B N nalyzer 5 Figure 6. Off Isolation Figure 7. Crosstalk nf nf Capacitance Meter LOGIC INPUT V or Capacitance Meter f = 1 MHz LOGIC INPUT V or f = 1 MHz B N B N Figure 8. Channel Off Capacitance Figure 9. Channel On Capacitance nf ignal Generator dbm B N 5 LOGIC INPUT V or Figure. Bandwidth 8

9 V 3. V THD (%) 4.5 V.1 FREQUENCY (Hz) Figure 11. Total Harmonic Distortion vs. Frequency 9

10 R ON () C 8 25 C 85 C 6 5 C C 4 R ON () 4 C 5 C 85 C 25 C 55 C V IN (V) V IN (V) Figure. R ON vs. V IN vs. = 3. V Figure. R ON vs. V IN vs. = 4.5 V V V 3. V 4.5 V R ON () V P OUT (db) V V IN (V) FREQUENCY (MHz) Figure 14. On Resistance vs. Input Voltage Figure 15. Bandwidth vs. Frequency V 3. V P OUT (db) V PHE (deg) V 4.5 V V 1 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Off Isolation vs. Frequency Figure 17. Phase ngle vs. Frequency

11 DEVICE ORDERING INFORMTION NL3158MNR2G Device Order Number Package Type Tape & Reel ize WDFN (Pb Free) 3 Unit / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging pecifications Brochure, BRD811/D. 11

12 PCKGE DIMENION WDFN 3.x1., P CE 485G IUE 2 X PIN ONE REFERENCE.15 C X 2 X.15 C. C.8 C D TOP VIEW IDE VIEW 1 B E (3) C ETING PLNE NOTE: 1. DIMENIONING ND TOLERNCING PER ME Y14.5M, CONTROLLING DIMENION: MILLIMETER. 3. DIMENION b PPLIE TO TERMINL ND I MEURED BETWEEN.25 ND.3 MM FROM TERMINL. 4. COPLNRITY PPLIE TO THE EXPOED PD WELL THE TERMINL. MILLIMETER DIM MIN MX REF b.18.3 D 3. BC E 1. BC e BC L.2.4 X L e X 1 6 BOTTOM VIEW 7 X b. C B.5 C NOTE 3 ON emiconductor and the are registered trademarks of emiconductor Components Industries, LLC (CILLC) or its subsidiaries in the United tates and/or other countries. CILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of CILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. CILLC reserves the right to make changes without further notice to any products herein. CILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does CILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in CILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. CILLC does not convey any license under its patent rights nor the rights of others. CILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the CILLC product could create a situation where personal injury or death may occur. hould Buyer purchase or use CILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold CILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that CILLC was negligent regarding the design or manufacture of the part. CILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON emiconductor E. 32nd Pkwy, urora, Colorado 811 U Phone: or Toll Free U/Canada Fax: or Toll Free U/Canada orderlit@onsemi.com N. merican Technical upport: Toll Free U/Canada Europe, Middle East and frica Technical upport: Phone: Japan Customer Focus Center Phone: ON emiconductor Website: Order Literature: For additional information, please contact your loca ales Representative NL3158/D