ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Fall Notes - Unit 7 DATAPATH CIRCUIT

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1 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 Note - Unit 7 INTRODUCTION TO DIGITL SYSTM DSIGN DIGITL SYSTM MODL FSM + Datapath Circuit: DTPTH CIRCUIT Input reetn clock FINIT STT MCHIN CONTROL CIRCUIT Output XMPL: CR LOT COUNTR photo receptor If = No light received (car obtructing LD ) If B = No light received (car obtructing LD B) B If car enter the lot, the following equence ( B) mut be followed: If car leave the lot, the following equence ( B) mut be followed: car might tay in a tate for many cycle ince the car peed i very large compared to that of the clock frequency. DIGITL SYSTM (FSM + Datapath circuit) Uually, when reetn (aynchronou clear) and clock are not drawn, they are implied. reetn B FINIT STT MCHIN ud ud Q clock CONTROL CIRCUIT -bit counter DTPTH CIRCUIT Intructor: Daniel Llamocca

2 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 Finite State Machine (FSM): B/ ud reetn = / / / / / / / / /,,/ S S3 S S5 / / / / / / / / / / / / / / / S6 / / S7 S / / / lgorithmic State Machine (SM) chart: S reetn= = no ye S3 S6 S S7 S S, ud Intructor: Daniel Llamocca

3 clr LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 XMPL: CCUMULTOR DIGITL SYSTM (FSM + Datapath circuit) clr: Synchronou clear. If = and clr =, then the output bit of the regiter are et to ero. reetn Din D Q ign extenion + D Q Dout retart i FINIT STT MCHIN clr Finite State Machine (FSM): retart/i clr reetn = / / X/ S / / X/ lgorithmic State Machine (SM): S reetn= retart i, clr i i, clr retart i 3 Intructor: Daniel Llamocca

4 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 XMPL: 7-SGMNT SRILIZR DIGITL SYSTM (FSM + Datapath circuit) Mot FPG Development board have a number of 7-egment diplay (e.g.,, ). However, only one can be ued at a time. If we want to diplay four digit (input, B, C, D), we can deign a erialier that will only how one digit at a time on the 7-egment diplay. Since only one 7-egment diplay can be ued at a time, we need to erialie the four BCD output. In order for each digit to appear bright and continuouly illuminated, each digit i illuminated for m every m (i.e. a digit i un-illuminated for 3 m and illuminated for m). Thi i taken care of by feeding the output '' of the counter to. to the enable input of the FSM. Thi way, tate tranition only occur each.. In the figure, the enable ignal for the four 7-egment diplay are active low (thi i uually the cae). B C D 3 BCD to 7 egment decoder 7 Counter (.) reetn -to- decoder buf buf(3) buf() buf() buf() FINIT STT MCHIN lgorithmic State Machine (SM) chart: Thi i a Moore-type FSM. reetn= S S3 S Intructor: Daniel Llamocca

5 L B LB P clrp LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 XMPL: SRIL MULTIPLIR UNSIGND MULTIPLICTION: SQUNTIL LGORITHM P, Load,B while B if b = then P P + end if left hift right hift B end while xample: x P + P P + = P + = P,, B b= P P + =., B b= P P =., B b= P P + = + =., B b= P P + = + =., B DIGITL SYSTM (FSM + Datapath circuit) Iterative Multiplier rchitecture: clr: ynchronou clear. In thi cae, if clr = and =, the regiter content are initialied to. The olution i computed in at mot N + cycle. N N DataB Data.. reetn b FSM L done din _l N N ".."&Data Shift-left N + LB B din _l N N B b Shift-right Parallel cce _l = Load _l = Shift P clrp clr P N lgorithmic State Machine (SM) chart: P S reetn= clrp P L, LB,, B, B S3 done b P 5 Intructor: Daniel Llamocca

6 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 xample (timing diagram): clock reetn D DB B F 3C 7 F F 3C 7 F tate S S S3 S S S3 S P F D 69 F F B C3 C3 C3 done L=LB =B clrp P 6 Intructor: Daniel Llamocca

7 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 XMPL: SRIL DT TRNSMISSION WITH URT URT Interface Thi interface tranfer data aynchronouly (clock i not tranmitted, tranmitter and receiver ue their own clock). Data communication: RXD (receive pin), TXD tranmit pin). The FT3 chip inide the Nexy- board i in charge of handling the USB communication with a computer. Format of a Frame: Start bit ( ), to 9 data bit (LSB tranmitted firt), optional parity bit, and a top bit ( ). Tranmitter: Simple deign that tranmit the data frame at the Baud rate (or bit rate in bp). Receiver: It ue a clock ignal whoe frequency i a multiple (uually 6) of the incoming data rate. Baud rate clock Micro USB FT3 TXD RXD rtix-7 - Nexy C (RXD) D (TXD) TXD tart DO D D D3 D D5 D6 D7 top DIGITL SYSTM (FSM + Datapath circuit) For a baud rate of 96 bp, the Baud rate clock i 96 H. N = 96 = 6. Thi number change according to the n deired baud rate. reetn= S TXD TXD SW TXD C Q FSM LR R o dout _L RIGHT SHIFT RGISTR din C Q LR, R reetn clock Q clr counter to 7 Q 3 Q C clr Q counter to N- n C S3 TXD C C (C C+) STRT bit C (C ) If max count i reached, C= make C= S TXD o C C (C C+) DT bit C (C ), R Q Q (Q Q+) Q (Q ) If max count i reached, Q= make Q= S5 TXD STOP bit C (C ) C C (C C+) 7 Intructor: Daniel Llamocca

8 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 XMPL: BIT-COUNTING CIRCUIT SQUNTIL LGORITHM C while if a = then C C + end if right hift end while DIGITL SYSTM (FSM + Datapath circuit) clr: Synchronou clear. In thi cae, if clr =, the count i initialied to ero (here, we do not need C to be ). Data reetn _l _r din _l Parallel cce Right Shift (MSB to LSB) _l = Load _l = Shift n n C Q m clr_c C clr counter: m bit m = ceil(log(n)) + a FINIT STT MCHIN done lgorithmic State Machine (SM) chart: S reetn= clr_c _r, _l _r S3 done a C Intructor: Daniel Llamocca

9 _G O_G _ext _R O_R _R O_R _R O_R _R3 O_R3 op _ LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 XMPL: SIMPL PROCSSOR DIGITL SYSTM (FSM + Datapath circuit) Data_in n D Q n Data BUS R R R R3 B LU G w fun 7 CONTROL CIRCUIT done Operation: very time w = '', we grab the intruction from fun and execute it: funq = f f f Ry Ry Rx Rx f Operation Function Load Rx, Data Rx Data Move Rx, Ry Rx Ry dd Rx, Ry Rx Rx + Ry Sub Rx, Ry Rx Rx - Ry Not Rx Rx NOT (Rx) nd Rx, Ry Rx Rx ND Ry Or Rx, Ry Rx Rx OR Ry Xor Rx, Ry Rx Rx XOR Ry 9 Intructor: Daniel Llamocca

10 _fun G op O_G _ext LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 Control Circuit: fun _fun 7 D Q 7 funq Rx Rx x DCODR with enable 3 _R _R _R _R3 Ry Rx o o DCODR with enable 3 O_R O_R O_R O_R3 funq = f f f Ry Ry Rx Rx x o o w f 3 FSM done rithmetic-logic Unit (LU): op Operation Function Unit y <= y <= + y <= - Tranfer Increment Decrement y <= B Tranfer B y <= B + Increment B rithmetic y <= B y <= + B y <= B Decrement B dd and B Subtract B from '' y <= not y <= not B y <= ND B y <= OR B y <= NND B y <= NOR B y <= XOR B y <= XNOR B Complement Complement B ND OR NND NOR XOR XNOR Logic Intructor: Daniel Llamocca

11 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 lgorithmic State Machine (SM): S reetn= w _fun _ext, x done f o, x done o, o _ o, o _ o, o _ o, o _ o, o _ o, o _ S3a Sa S5a S6a S7a Sa o, _G op o, _G op _G op o, _G op o, _G op o, _G op S3b Sb S5b S6b S7b Sb O_G, x done O_G, x done O_G, x done O_G, x done O_G, x done O_G, x done Intructor: Daniel Llamocca

12 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 XMPL: DISPLYING PTTRNS ON 7-SGMNT DISPLYS Different pattern are hown baed on the elector el ignal. Two 7-egment diplay are ued. top input: If it i aerted (top = ), the light pattern freee. The input x elect the rate of change (every.5,.,.5, or.5 econd). eg[7..] : el 7 6 eg x 5 top? reetn 3 el[..] clock DIGITL SYSTM (FSM + Datapath circuit) x top reetn clock Q?? counter (.5) Q?? el FINIT STT MCHIN deg g D Q 7 7 On the NXYS, only one 7-egment diplay can be ued at a time 7 counter (.) 3 Counter (.) Q?? FINIT STT MCHIN -to- decoder buf buf() buf() counter (.5) Q?? x = Light change every.5 x = Light change every. x = Light change every.5 x = Light change every.5 counter (.5) Intructor: Daniel Llamocca

13 LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 lgorithmic State Machine (SM) chart: S reetn= el deg, g deg, g deg, g deg, g S5 S S deg, g deg, g deg, g deg, g S3 S6 S9 deg, g deg, g deg, g deg, g S S7 S S3 deg, g deg, g deg, g deg, g lgorithmic State Machine (SM) chart: Thi i the FSM that control the output MUX S reetn= 3 Intructor: Daniel Llamocca