Unit 1 - Digital System Design

Size: px

Start display at page:

Download "Unit 1 - Digital System Design"

Lora Matthews
5 years ago
Views:

LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 IGITAL SYSTM MOL FSM (CONTROL) + ATAPATH CIRCUIT Unit - igital System esign ATAPATH CIRCUIT Inputs clock

1 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 IGITAL SYSTM MOL FSM (CONTROL) + ATAPATH CIRCUIT Unit - igital System esign ATAPATH CIRCUIT Inputs clock FINIT STAT MACHIN CONTROL CIRCUIT Outputs XAMPLS CAR LOT COUNTR photo receptors If A = No light received (car obstructing L A) If B = No light received (car obstructing L B) B A If car enters the lot, the folloing sequence (A B) must be folloed: If car leaves the lot, the folloing sequence (A B) must be folloed: A car might stay in a state for many cycles since the car speed is very large compared to that of the clock frequency. IGITAL SYSTM (FSM + atapath circuit) Usually, hen (asynchronous clear) and clock are not dran, they are implied. A B FINIT STAT MACHIN ud ud clock CONTROL CIRCUIT -bit counter ATAPATH CIRCUIT Instructor: aniel Llamocca

2 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 Finite State Machine (FSM): A B/ ud = / / / / / / / / /,,/ S S S3 S S5 / / / / / / / / / / / / / / / S6 / / S7 S8 / / / Algorithmic State Machine (ASM) chart: S = = no S yes S3 S6 S S7 S S8, ud Instructor: aniel Llamocca

3 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 BOUNCING CIRCUIT Mechanical bouncing lasts approximately ms. The, e have to make sure that the input signal is stable ( ) for at least ms before e assert _db. Then, to deassert _db, e have to make that the is stable ( ) for at least ms. IGITAL SYSTM (FSM + atapath circuit) Counter to N-: = = +. sclr: Synchronous clear. The ay it is designed, if sclr = and =, then =. If T is the period of the clock signal, then N = ms. T For example, for MHz input clock, T = ns. Then N = ms = ns 6 ms ms clock FSM sclr z _db _db < ms < ms sclr counter to N- n n comparator =N-? z Algorithmic State Machine: S = S, sclr aits for the first '' S sclr for _db=, must be for at least ms z S3 _db S _db, aits for the first '' z sclr for _db=, must be for at least ms 3 Instructor: aniel Llamocca

4 _G O_G _ext _R O_R _R O_R _R O_R _R3 O_R3 op _A LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 SIMPL PROCSSOR IGITAL SYSTM (FSM + atapath circuit) This system is a basic Central Processing Unit (CPU). For completeness, a memory ould need to be included. Here, the Control Circuit could be implemented as a State Machine. Hoever, in order to simplify the State Machine design, the Control Circuit is partitioned into a datapath circuit and a FSM. ata_in n n ata BUS R R R R3 A B ALU G fun 7 CONTROL CIRCUIT done OPRATION very time = '', e grab the instruction from fun and execute it. Instruction = f f f Ry Ry Rx Rx. This is called machine language instruction or Assembly instruction: f f f : Opcode (operation code). This is the portion that specifies the operation to be performed. Rx: Register here the result of the operation is stored (e also read data from Rx). Rx can be R, R, R3, R. Ry: Register here e only read data from. Ry can be R, R, R3, R. f = f f f Operation Function Load Rx, ata Rx ata Move Rx, Ry Rx Ry Add Rx, Ry Rx Rx + Ry Sub Rx, Ry Rx Rx - Ry Not Rx Rx NOT (Rx) And Rx, Ry Rx Rx AN Ry Or Rx, Ry Rx Rx OR Ry Xor Rx, Ry Rx Rx XOR Ry Instructor: aniel Llamocca

_fun _A _G op O_G _ext LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 Control Circuit: This is made out of some combinational units, a register, and a

5 _fun _A _G op O_G _ext LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 Control Circuit: This is made out of some combinational units, a register, and a FSM: x: very time e ant to enable register Rx, the FSM only asserts x (instead of controlling _R, _R, _R, _R3 directly). The decoder takes care of generating the enable signal for the corresponding register Rx. o, so: very time e ant to read from register Ry (or Rx), the FSM only asserts o (instead of controlling O_R, O_R, O_R, O_R3 directly) and so (hich signals hether to read from Rx or Ry). The decoder takes care of generating the enable signal for the corresponding register Rx or Ry. fun _fun 7 7 funq Rx Rx x COR ith enable 3 _R _R _R _R3 Ry Rx o so COR ith enable 3 O_R O_R O_R O_R3 funq = f f f Ry Ry Rx Rx x o so f 3 FSM done Arithmetic-Logic Unit (ALU): op Operation Function Unit y <= A y <= A + y <= A - Transfer A Increment A ecrement A y <= B Transfer B y <= B + Increment B Arithmetic y <= B y <= A + B y <= A B ecrement B Add A and B Subtract B from 'A' y <= not A y <= not B y <= A AN B y <= A OR B y <= A NAN B y <= A NOR B y <= A XOR B y <= A XNOR B Complement A Complement B AN OR NAN NOR XOR XNOR Logic 5 Instructor: aniel Llamocca

6 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 Algorithmic State Machine (ASM): very branch of the FSM implements an Assembly instruction. S = S _fun _ext, x done f o, x done o, so _A o, so _A o, so _A o, so _A o, so _A o, so _A S3a Sa S5a S6a S7a S8a o, _G op o, _G op _G op o, _G op o, _G op o, _G op S3b Sb S5b S6b S7b S8b O_G, x done O_G, x done O_G, x done O_G, x done O_G, x done O_G, x done 6 Instructor: aniel Llamocca

7 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 BINARY TO BC CONVRSION OUBL BL ALGORITM Given an N-bit unsigned binary number, e left shift every one of the N bits into a ne register (that holds the BC digits). We thus have N iterations. If after shifting, any of the BC digits (one or more) is greater than, e increment it by 3. The exception is on the last iteration, here after shifting, e do not increment any nibble. For N bits, e need N 3 BC digits. So the BC register is N 3 bits ide. Number of bits Binary range Number of BC digits [-5] 7 [-7] 3 [-3] [-6383] 5 N [, N ] N 3 Why does it ork? Think of BC shifting: e ant to shift the bits of a BC number, but preserving the BC representation. If a number loer or equal than is shifted, e get at most 8, still representable in BC. If a number greater than is shifted, the minimum number e get is =, hich is not in BC. If e add 3 to the number and then shift, e ill get the proper BC result ith BC digits. xample: 5=. If e shift, e get. ould be in BC. To get this, e can add 3 to, resulting in. After shifting, e get. The same happens for numbers 6, 7, 8, and 9. xample: 55 = (N=8). We need N 3 = 3 BC digits. Note that there are N = 8 iterations. The table shos the state after an operation has been applied. In the example, only a nibble gets incremented at a time. BC number Binary number Procedure just applied Procedure to apply Initialization Left shift Left shift Left shift Left shift Left shift Left shift. >. Then e add 3 to Add 3 to Left shift Left shift. >. Then e add 3 to Add 3 to Left shift Left shift Left shift Left shift. >. Then e add 3 to Add 3 to Left shift Left shift >. Then e add 3 to Add 3 to Left shift Left shift. None. We do not add 3 in the last iteration xample: 7 = (N=8). We need N 3 = 3 BC digits. Note that there are N = 8 iterations. The table shos the state after an operation has been applied. In general, more than a nibble can be incremented at a time. BC number Binary number Procedure just applied Procedure to apply Initialization Left shift Left shift Left shift Left shift Left shift Left shift >. Then e add 3 to Add 3 to Left shift Left shift Left shift Left shift Left shift Left shift Left shift Left shift >, >. Then e add 3 to and Add 3 to and Left shift Left shift Note. We do not add 3 in the last iteration 7 Instructor: aniel Llamocca

LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 IGITAL SYSTM (FSM + atapath circuit) start done i_bin clock sclrb B FSM K _A L_A _LB sclr_b _C sclr_c _CB

8 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 IGITAL SYSTM (FSM + atapath circuit) start done i_bin clock sclrb B FSM K _A L_A _LB sclr_b _C sclr_c _CB sclr_cb B z_c z_cb CB F _C sclr_c sclr counter to N- z_c _CB sclr_cb sclr counter to K- z_cb CB _LB COR... K- LB() LB() LB() LB(K-) N pb(k) so so LFT SHIFT sclr pb(k-) pb() LFT SHIFT sclr pb() LFT SHIFT sclr pb() s_l s_l s_l RGISTR B(K-) RGISTR B() RGISTR B() LB(K-) LB() LB() so B(K-) B() B() so LFT SHIFT RGISTR s_l A LA F... K- + B o_bcd(k-)... o_bcd() CB o_bcd() Algorithmic State Machine (ASM) Chart: S = sclrb, B ".." _C, sclr_c, _CB, sclr_cb start LA, A S B "..", A S3 F > & z_c= no yes _LB B(CB) z_cb _CB _CB, sclr_cb z_c _C _C, sclr_c S done start 8 Instructor: aniel Llamocca

9 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 XTRA TOPICS LINAR FBACK SHIFT RGISTRS (LFSRS) LFSRs have a simple and fairly regular structure. Typical components: -type flip flops, and logic gates. Advantages: very little hardare and high speed operation. Inputs to flip flops are linear functions of the previous state. espite the simple appearance, LFSRs are based on rather complex mathematical theory and have interesting applications in the area of digital system testing, cryptography, and fault-tolerant computing. Typical applications: rror correction/detection, pseudo random number generators, fast counters. A generic -bit LFSR is depicted belo: 3 x LINAR FUNCTION APPLICATION: CYCLIC RUNANCY CHCK (CRC) This error-detection code is used in digital communications (e.g.: thernet, CAN), and storage devices (e.g.: RAMs). Communication system k-bit message: M = m k m k m m. CRC code: R = r n r n r r. Stream sent: m k m k m m r n r n r r CRC Generator Transmitted bits CRC Checker error Associated polynomials: M(x) = m k x k + m k x k + + m x + m x. Order: k R(x) = r n x n + r n x n + + r x + r x. Order: n The CRC code is calculated as a remainder: R(x) = remainder ( xn M(x) G(x) ) G(x) = g n x n + g n x n + + g x + g x. This is the generating polynomial of order n. G = g n g n g g Here, hen dealing ith polynomial operations, e use modulo- polynomial arithmetic (Galois field of to elements: GF()). The coefficients of the polynomials can only be or. The multiplication operation can be implemented as a simple AN gate, and the addition (or subtraction) operation can be implemented by a XOR gate: a ± b = a b, a {,}. xample: x n + x n = x n x n =. CRC generator: It computes R(x). Its input is x n M(x) m k m k m m. CRC checker: On the receiver side, both the message and CRC code might be corrupted by the channel: M (x) and R (x). So, e must check if remainder ( xn M (x) ) = R (x). If so, e say that the system passed the CRC check. G(x) Note that this implies: x n M (x) = (x)g(x) + R (x) x n M (x) R (x) = x n M (x) + R (x) = (x)g(x). In modulo- arithmetic, R (x) = R (x). It follos that x n M (x) + R (x) should be divisible by G(x). The CRC checker tests if remainder ( xn M (x)+r (x) ) =. If the remainder is zero, e say that it passed the CRC check. It G(x) is still possible for R (x) and M (x) to make the remainder equal to zero but this is far less likely. The input to the CRC checker is x n M (x) + R (x) m k m k m r n r n r. 9 Instructor: aniel Llamocca

10 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 xample: CRC- (n = ): M =, G = M(x) = x 7 + x 6 + x 5 + x + x x n M(x) = x (x 7 + x 6 + x 5 + x + x) = x + x + x 9 + x 6 + x 5 G(x) = x + x 3 + R(x) = x + x CRC circuit The folloing LFSR implements -bit CRC. Components: flip flops, AN, XOR gates. Note that g = is not used. This is because it is common in CRC to have g n =. This is already considered in the design of the circuit. xample ith M =, G = : When integrated into the CRC generator, the input is given by: x n M(x). The output result is R =. When integrated into the CRC checker, the input is given by: x n M (x) + R (x). The result of the circuit is remainder =, indicating a valid transmission. R R R R 3 x G G G G 3 x R x R Applications: The circuit above can be implemented for any number of bits n. For example: CRC-3 (thernet), CRC-5 (CAN), and CRC- (trivial even parity generator ith G(x) = x + ). This is a serial implementation, i.e., each bit is fed to the circuit at a time. Other implementations process some bits in parallel (for CRC-, the parity generator in C7: Notes Unit processes all the bits at once). The design of the generating polynomial G(x) is outside the scope of this class. These circuits are better implemented in hardare for high speed and lo resource utilization. x G R Instructor: aniel Llamocca

11 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 MOULO-N COUNTR SIGN A modulo-n counter could be designed by the State Machine method, but this can be very cumbersome if N is a large number. For example, if N=, e need states. The figure shos a counter modulo- that uses a register, and adder, a comparator, and logic gates. : count. z: output signal asserted only hen the maximum count (99) is reached. This can be easily described in VHL using the structural description. You can also use the behavioral description, here the count is increased by every clock cycle and z is asserted hen the count reaches N a 7 b 7 + a 6 b 6 a 5 b 5 sclr clock sclr 8 B a b a 3 b 3 A=B sclr: synchronous clear If =sclr=, then = 8 A = 99? A=B a b a z b a b MMORY COING Physical implementation of memory is not homogeneous: ifferent portions of memory are used for different purposes: RAM, ROM, I/O devices. A processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. ven if all the memory as of one type, e still have to implement it using multiple ICs. For a given valid address, one and only one memory-mapped component must be accessed. Address ecoding: Process of generating chip select (CS, C) signals from the address bus for each device in the system. The Address bus line (N+M bits) is split into to sections: The N most significant bits are used to generate the CS signals for the different devices. The M least significant bits are passed to the devices as addresses. XAMPL A -bit address line in a processor handles up to = MB of addresses, each address containing one-byte of information. We ant to connect four 56KB memory chips to the processor. The MSBs of the address line are used to generate the CS signals. The 8 LSBs are passed to the devices as addresses. The pink-shaded circuit: i) addresses the memory chips, and ii) enables only one memory chip (via C: chip enable) hen the address falls in the corresponding range. xample: if address = x5ffff, only memory chip is enabled (C=). If address = x3, only memory chip is enabled. 3 56KB 56KB 56KB 56KB FFFF 7FFFF 8 BFFFF C FFFFF Memory space Memory devices address 56 KB 56 KB 56 KB 3 C C C address(7..) address(8) address(9) y y y y 3 56 KB C Instructor: aniel Llamocca

12 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 FLIP FLOPS: PRACTICAL ASPCTS Reducing rate of change of a synchronous circuit: Here, e use FSM as an example of a synchronous circuit. But e can apply this technique to any synchronous circuit. We usually ould like to reduce the rate at hich FSM transitions occur. A straightforard option is to reduce the frequency of the input clock. But this is a very complicated problem hen a high precision clock is required. Alternatively, e can reduce the rate at hich FSM transitions occur by including an enable signal in our FSM: this means including an enable to every flip flop in the FSM. For any FSM transition to occur, the enable signal has to be. Then e assert the enable signal only hen e need it. The effect is the same as reducing the frequency of the input clock. The figure belo depicts a counter modulo-n (from to N-) connected to a comparator that generates a pulse (output signal z) of one clock period every time e hit the count N-. The number of bits the counter is given by n = log N. The effect is the same as reducing the frequency of the FSM to f N, here f is the frequency of the clock. n Inputs FSM Outputs comparator z clock counter to N- =N-? xample: Timing diagram of a modulo- counter. Notice that z is only asserted hen the count reaches. This z signal controls the enable of a FSM, so that the FSM transitions only occur every clock cycles, thereby having the same effect as reducing the frequency by. z We can apply the same technique not only to FSMs, but also to any sequential circuit. This ay, e can reduce the rate of any sequential circuit (e.g. another counter) by including an enable signal of every flip flop in the circuit. Flip flop timing parameters: Propagation elay. Setup Time: Interval of time before the clock edge here the data must be held stable. Hold Time: Interval of time after the clock here the data must be held stable. If setup time or hold time are violated, the output may become unpredictable, or even orse it might enter into metastability. restricted region Instructor: aniel Llamocca

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Digital Logic and Microprocessor Design Winter 2015.

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Digital Logic and Microprocessor Design Winter 2015. LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Note - Unit 7 INTRODUCTION TO DIGITAL SYSTM DSIGN DIGITAL SYSTM MODL FSM + Datapath Circuit: