Fault Tolerance & Reliability CDA Chapter 2 Cyclic Polynomial Codes
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1 Fault Tolerance & Reliability CDA 5140 Chapter 2 Cyclic Polynomial Codes - cylic code: special type of parity check code such that every cyclic shift of codeword is a codeword - for example, if (c n-1, c n-2,... c 0 ) is a codeword so is (c n-2, c n-3,... c 0, c n-1 ) - cyclic property best captured using polynomial algebra over a finite field, in particular binary finite field - for code word c(x) = (c n-1, c n-2,... c 0 ) represent it as polynomial c n-1 X n-1 + c n-2 X n c 1 X 1 + c 0 - two most important concepts are use of polynomial division and the operation of modulo a polynomial - for f(x) and g(x) two polynomials with the latter of at least degree 1, then the Euclid division algorithm states that there are two polynomials q(x), the quotient, and r(x), the remainder such that f(x) = q(x)g(x) + r(x) and degree of r(x) is less than degree of g(x) and further state that r(x) is congruent to f(x) modulo g(x), i.e. r(x) = f(x) [mod g(x)] - for cyclic codes most important modulus is X n 1 which implies that 1 = X n [mod X n 1] - thus Xc(x) [mod X n 1] is a code word since Xc(X) = c n-1 X n + c n-2 X n c 1 X 2 + c 0 X and reducing mod X n 1, then X n = 1 giving Xc(X) = c n-2 X n-1 + c n-3 X n c 1 X 2 + c 0 X + c n-1
2 - consequently for c(x) a codeword, so is X i c(x) - thus α i X i c(x) = f(x) c(x) where f(x) has binary coefficients - just as can generate any (n,m) parity-check code using the generator matrix G, can also generate the code words for (n,m) cyclic code by the generator polynomial g(x) with the following properties: - g(x) is unique lowest-degree nonzero code polynomial with coefficient 1 in highest-degree term - degree of g(x) is n m - each of the 2 m code words of binary cyclic code is multiple of g(x) of form α i X i g(x), 0 < i < m-1 - set of code polynomials g(x), Xg(X),... X m-1 g(x) is a linearly independent set and all 2 m code words can be generated from these m code words - g(x) must be a factor of X n 1 Example: - consider the (7,4) cyclic code with generating polynomial g(x) = X 3 + X + 1 has 3 check digits and the four linearly independent code words are: polynomials 7-tuples X 3 + X X 4 + X 2 + X X 5 + X 3 + X X 6 + X 4 + X and all 16 codewords are linear combinations of these
3 - for a data polynomial, of degree m-1, d(x) = d m-1 X m-1 + d m-2 X m d 1 X 1 + d 0 the data digits are d m-1, d m-2,... d 0 - the code words can be generated by c(x) = d(x) g(x) which can be done by means of the following shift register circuit where the register cells are initialized to all zeroes: d(x) g n-m g 2 g 1 g 0 + c(x) Nonsystematic Encoding using Shift Register - digit d m-1 is fed in first, then d m-2 and so on until d 0 followed by (n-m) zeroes
4 - the circled g i represent multiplication by g i (either 0 or 1) and the + is modulo 2 addition (XOR), and the g i are coefficients of g(x) - code digits come out in the order of c n-1 until finally c 0 - as an example, consider for n = 7, m = 4 g(x) = X 3 + X + 1 and d(x) = X use the above circuit to generate c(x) and verify using polynomial multiplication that the resulting c(x) is g(x) times d(x) - note that above circuit generates a non-systematic code word - can generate a systematic code by applying the following and creating the corresponding circuit - multiplying d(x) by X n-m we have X n-m d(x) = d m-1 X n-1 + d m-2 X n d 0 X n-m = q(x)g(x) + r(x) for g(x) the degree n-m generator polynomial, and r(x) the unique remainder polynomial of degree less than n-m then, adding r(x) to each side gives d m-1 X n-1 + d m-2 X n d 0 X n-m + r(x) = q(x)g(x) thus the LHS must be a multiple of g(x) and hence a code polynomial and if we write r(x) as r(x) = p n-m-1 X n-m-1 + p n-m-2 X n-m p 1 X + p 0 the coefficients of the code polynomial are: d m-1, d m-2,... d 0, p n-m-1, p n-m--2,... p 0 which is systematic
5 - then need to design a feedback shift register to divide X n-m d(x) by g(x) to determine r(x) - the following circuit does so, where the register is initialized to all zeroes, and with d m-1 fed in first, and then d m-2,... d 0 sequentially in that order until d m-1 reaches the furthest right position - then perform m right shifts which then leaves the digits of r(x) in the register with p n-m-1 in the furthest right position - note in the following figure, since the coefficient of X n-m must be 1 there is no corresponding multiplication needed as for the other positions; and, the first cell simply holds the bit before the clock pulse, while the remaining cells hold the results g 0 g 1 g 2 g n-m-2 g n-m-1 d(x) Feedback Shift Register for Systematic Encoding for the original d(x) = X and g(x) = X 3 + X + 1, draw the FSR and perform the division, give the resulting r(x) and c(x), and show, using polynomial division that c(x) is a multiple of g(x) - of interest is that this same feedback shift register can be used for encoding and error detection - if the received polynomial is y(x) and the error polynomial is e(x), then
6 y(x) = c(x) + e(x) - if y(x) is a code word and it is divided by g(x), the remainder is 0 - if y(x) is not a code word, then dividing by g(x) will give a remainder which is referred to as a syndrome (polynomial) s(x) and indicates an error - is y(x) = X 5 + X 2 + X + 1 a codeword for the above circuit? - is y(x) = X 6 + X 4 + X 2 a codeword for the above circuit?
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