Number Systems 1(Solutions for Vol 1_Classroom Practice Questions)

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(OR) s per the given number x must be greater than 5. Let consider x = 6 (5) 6 = (59) (44) 6 = (64) () 6 = () (59) + (64) = () So that x = 6. ns: (a) 8-bit representation of.

2 Chapter Number Systems (Solutions for Vol _Classroom Practice Questions). ns: (d) 5 x + 44 x = x ( x + x + 5 x )+( x +4 x + 4 x ) = x + x + x x +x+5+x +4x+4 = x + x + x 5x 6 = (x6) (x+ ) = (ase cannot be negative) Hence x = 6. (OR) s per the given number x must be greater than 5. Let consider x = 6 (5) 6 = (59) (44) 6 = (64) () 6 = () (59) + (64) = () So that x = 6. ns: (a) 8-bit representation of. ns: (c) In s complement representation the sign bit can be extended towards left any number of times without changing the value. In given number the sign bit is X, hence it can be extended left any number of times. 4. ns: (c) inary representation of +(59) : (+59) =( ) = ( ) S complement Hexadecimal equivalent (DE5) H +7 = () s complement representation of 7 =. s complement representation of 7 =. No. of s in s complement of 7 = m = No. of s in s complement of 7 = n = m: n = : CE Engg. Publications 5. ns: 5 Symbols used in this equation are,,, Hence base or radix can be 4 or higher () x = () x (.) x x + x +x = (x+) (x+x +x - ) x +x+ = (x) x x x + x + = x + 6x + x 5x = x(x 5) = x = (or) x = 5 x must be x >, So x = 5 Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

3 : : Number Systems 6. ns: 5 = x8 y = x.y + 8 y = xy+8 xy = Possible solutions: i. x =, y = ii. x =, y = 5 iii. x =, y = possible solutions exists. 7. ns: The range (or) distinct values For s complement ( n )to +( n ) For sign magnitude ( n ) to +( n ) Let n = in s complement ( ) to + ( ) to +,,, + X = 4 n = in sign magnitude to + Y = X Y = CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

4 Chapter Logic Gates & oolean lgebra. ns: (c) Given s complement numbers of sign bits are x & y. z is the sign bit obtained by adding above two numbers. Overflow is indicated by = x y z x y z Examples. = +7 = +7 4 x y z. = +7 = +5 x y z. = 7 = 7 4 x y z 4. = 7 = 5 x y z. ns: (b) Truth table of XOR o/p Stage : X X o/p For second XOR gate o/p =. Similarly for third XOR gate o/p = X & for fourth o/p = For Even number of XOR gates o/p = For XOR gates cascaded o/p =.. ns: (b) w,x y,z 4. ns: (c) f f y z v = v = x x w,x y,z f 4 Stage : Given one i/p = lways. X o/p = X = X CE Engg. Publications For First XOR gate o/p = X x f f f 4 = f. f + f 5. ns: (d) Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata f P Q R

5 t t P t Q t R t : 5 : Logic Gates and oolean lgebra = m (,, 4,7) M (x, y, z) = a b c Where x = M (a, b,c), y = M(a,b, c ), z = c 8. ns: 4 () (C) (without delay) t = t = t = 4 t = 6 t = 8 t(ns) 6. ns: (c) x x x x x x x x 4 x x 4 x x 4 x x x x 4 y z, when y = z option (c) is true For all cases option,, D not satisfy. 7. ns: (b) M(a,b,c) = ab + bc + ca M (a, b,c) = bc a b a c M(a, b, c ) = ab + b c + c a M( M (a, b,c), M(a,b, c ), c) = bc ab a c (ab bc ac) ab bc ca)c ( bc ab bc ab a c (ab bc ac) = abc abc abc abc = c[ab ab] c[ab ab] y z a cc bc ab a c(c) abc (with delay) (with delay) Z(without delay) Z (with delay) 4 n sec Z is for 4 nsec 9. ns: (c) Logic gates X Y XY XY Where Y Y It is a NND gate and thus the gate is Universal gate. CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

6 Chapter K Maps. ns: (b) yz wx f xz xz SOP SOP: x y + y w POS: y(x + w) wz xy wy = xy+yw xy. ns: (b). POS ab cd b d f b d b c x + w wz xy = y(x+w) b c y 4. ns: (a) For n-variable oolean expression, Maximum number of minterms = n Maximum number of implicants = n Maximum number of prime implicants = n 5. ns: (c) C F(,, C) = C C 6. ns: fter minimization = C D = CD only one minterm. = n CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

7 : 7 : K-Maps 7. ns: w z w xy x yz wx yz CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

8 4 Chapter Combinational Circuits. ns: (d) Let the output of first MUX is F F = I +I Where is selection line, I, I = MUX Inputs F S.W S.W S Output of second MUX is F.I F S. I.F S. F F S F ut F S F S S W W i.e., F W S S W. ns: 5 X Y Y X Y X Y X Z 4 F Z F Z F Z F Z S S S S Initially all the output values are, at t =, the inputs to the 4-bit adder are changed to X X X X =, Y Y Y Y = indicates critical path delay to get the output CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

9 : 9 : ECE - Postal Coaching Solutions X Y S = [t= ns] is updated as after ns 5 5 C Z = [t= ns] is updated again to (or) is not changed, i.e. Z is t= ns Z = X Y S = [t= ns] is updated again to (or) is not changed 5 5 C C Z = [t= ns] is updated again to (or) is not changed, i.e. Z is t= ns Z = X Y S = [t= ns] is updated again to (or) is not changed Z = 5 5 C Z = [t=5ns, t =5ns] is updated to after 5 ns X Y S = [t=ns] is updated again to (or) is not changed 5 5 C Z 4 = [t=5ns, t =5ns] is updated as after 5ns when Z is arrived Z = Total time taken = t + t = 5 ns i.e. critical time (or) maximum time is taken for Z 4 to get final output as CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

10 : : Digital. ns: (a) The given circuit is binary parallel adder/subtractor circuit. It performs +, but not + operations. K C Operation + (addition) ++(addition with carry) + ( s complement addition) + +( s complement subtraction) 4. ns: (d) It is expansion of :4 decoders to :8 demultiplexer, must be connected to S, S i.e.., R = S, S = S Q must be connected to S i.e., Q = S P is serial input must be connected to D in 5. ns: 6 T = NOR MUX MUX ns.5ns.5ns Delay = ns +.5ns +.5ns = 5ns T = NOT MUX NOR MUX ns.5ns ns.5ns Delay = ns +.5ns + ns +.5ns = 6ns Hence, the maximum delay of the circuit is 6ns 6. ns: When all bits in register is, then only it gives highest delay. in 8 bit notation of s complement is CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

11 5 Chapter Sequential Circuits. ns: (c) Given Clk, X, X Output of First D-FF is Q Output of Second D-FF is Q 4 clk X X Q Q s the clear input is given to be synchronous so it waits upto the next clock pulse to clear the counter & hence the counter get s cleared during the 7 th clock pulse. mod of counter = 7 4. ns: (b) The given circuit is a mod 4 ripple down counter. Q is coming to after the delay of t. CLK Q Q 4 Y=Q Q. ns: 4 In the given first loop of states, zero has repeated times. So, minimum 4 number of Flip-flops are needed.. ns: 7 The counter is cleared when Q D Q C Q Q = Clk Q D Q C Q Q ns: (c) ssume n = clk -bit counter Q Q 4 decoder Outputs of counter is connected to inputs of decoder Counter outputs Decoder inputs Decoder outputs Q Q a b d d d d The overall circuit acts as 4-bit ring counter n = k = = 4, k-bit ring counter CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

12 : : Digital & Microprocessors 6. ns: (b) CLK Serial in= C D C D fter 7 clock pulses content of shift register become again 7. ns: (b) J K Q n Q T J Q K Q n. =. =. =. =. =. =. =. = Q n+ J KQ n n Q n Q n T = J Q +KQ n = (J+Q n ) (K + Q ) n n 8. ns:.5 Clk Q Q Q Q 4 Q 5 Y= Q + Q The waveform at OR gate output, Y is [ = +5V] verage power V T o Lt T 5T P T y (t) dt o R R T dt T dt RT T.T 5. (T T) (5T T).5mw RT R(5T) 5 CE Engg. Publications T T T 4T 5T T = 5T Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

13 : : Postal Coaching Solutions 9. ns: (b) Present Next State Output (Y) State X = X = X = X = E C C D E C Step (): Step (): y replacing state as state C then state, C are equal. Reducing state table Present state D E Next state X = X = Reducing state table Present state D E E Next state X = X = E State D, E are equal, remove state E and replace E with D in next state. Reducing state table Present state D D Next state X = X = D Finally reduced state table is Reduced state table Present state D Next state X = X = D states are present in the reduced state table. ns: (c) State table for the given state diagram State Input Output S S S S Output is s complement of input.. ns: (c) In state (C), when XYZ =, then mbiguity occurs ecause, from state (C) When X =, Z = N.S is () When Y =, Z = N.S is () CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

14 Chapter 6 Logic Gate Families. ns: (b) V OH (min):- (High level output voltage) The minimum voltage level at a Logic circuit output in the logic state under defined load conditions. V OL (max):- (Low level output voltage) The maximum voltage level at a logic circuit output in the Logical state under defined load conditions. V IL (max):- (Low level input voltage) The maximum voltage level required for a logic at an input. ny voltage above this level will not be accepted as a Low by the logic circuit. V IH (min) :- (High level Input voltage) The minimum voltage level required for logic at an input. ny voltage below this level will not be accepted as a HIGH by the Logic circuit. I OH + + I IH. ns: (b) Fan out is minimum in DTL (High Fan-out = CMOS) Power consumption is minimum in CMOS. Propagation delay is minimum in ECL (fastest = ECL). ns: (b) When V i =.5V, Q is in reverse active region Q is in saturation region Q is in saturation region Q 4 is in cut-off region 4. ns: (d) The given circuit can be redrawn as below: P P Q Q NOT gate V dd OUT CE Engg. Publications V OH V - - IH I OL + V OL - High Low Fig: currents and voltages in the two logic states. I IL + V IL - OUT PQ PQ = P ND Q 5. ns: (b) s per the description of the question, when the transistor Q and diode both are OFF then only output z =. X Y Z Remarks Q is OFF, Diode is ON Q is OFF, Diode is OFF Q is ON, Diode is OFF Q is ON, Diode is OFF Hence Z = X Y Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

15 7 Chapter Semiconductor Memories. ns: (b) Square of a 4 - bit number can be at most 8 - bit number. { i.e () = (5) [(5) ] = (5) }. Therefore ROM requires 8 data lines. Data is with size of 4 bits ROM must require 4 address lines and 8 data lines ROM = n m n = inputs (address lines), m = output lines n = 4, m = 8.. ns: (a) ROM is used to design a combinational circuit. The number of address lines of the ROM is equal to the number of input variables in the truth table. ROM is represented as n m where n inputs and m output lines. [Where n = address bits]. ns: (b) i/p s o/p s X X X X Y Y Y Y 4 Outputs ns: (c) C C E ROM t the rising edge of the First clock pulse the content of location () = 6 appears on the data bus, at the rising of the second clock pulse the content of location () = appears on the data bus. 5. ns: (b) bit SRM memory cell is WL t t time L CMOS Inverters L In Inverters, output of the st Inverter is connected to Gate Input of nd Inverter and vice versa. The outputs are in 4 CD number CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

16 8 Chapter /D & D/ Converters. ns: (b) CLK Counter Decoder Q Q Q D D D D V R ns: (b) R R R R I/ R R R I/4 I/8 I/6 R 8 9 R equ = (((((R R)+R) R)+R) R)+R) R) R equ = R = k. V I = R V = = m. R k Current division at 6 I = 6 = 6.5. ns: (c) Net current at inverting terminal, I I 5I I i = + = I V = I i R = k 6 5 = =.5V 6 4. ns: (d) Given that V DC = n n b n Volts V DC = b b b b V DC =.5b + b + b + 4b Initially counter is in state Up counter o/p b b b b V DC (V) o/p of comparator When V DC = 6.5 V, the o/p of comparator is. t this instant, the clock pulses to the counter are stopped and the counter remains in state. The stable reading of the LED display is. CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

17 : 7 : Digital & Microprocessors 5. ns: (b) The magnitude of error between V DC & V in at steady state is 6. ns: (a) In Dual slope V V = DC DC Vin T VR.T VR T Vin T in =. V mv 7. ms ms DVMindicates.4 7. ns: (d) Ex: f in = khz f s = khz f in = 5 khz f s = 5 khz. Max conversion time = N+ T =. s = 48 s. Sampling period = T s maximum conversion time T s 48 s. Sampling rate f s = 6 Ts 48 f s 488 f s 5 Hz f 4. f in = s 5Hz CE Engineering cademy Hyderabad Delhi hopal Pune hubaneswar Lucknow Patna engaluru Chennai Vijayawada Vizag Tirupati Kukatpally

18 Chapter 9 rchitecture, Pin Details of 885 & Interfacing with 885. ns: (a) chip select is an active low signal for chipselect ; the inputs for NND gate must be let us see all possible cases for chipselect condition =EH X X X X X X X X X X X X X X X X X X X X X X X X The only option that suits hare is option(a) & are used for line selection to 7 are used for chip selection ddress space is 6H to 6H o to are used for line selection to 5 are used for chip selection 6H ( =) 6H( =) Chipselect =EFFFH. ns: (d) oth the chips have active high chip select inputs. Chip is selected when 8 =, 9 = Chip is selected when 8 =, 9 = Chips are not selected for combination of & of 8 & 9 Upon observing 8 & 9 of given address Ranges, F8 to F9FF is not represented. ns: (d) The I/O device is interfaced using Memory Mapped I/O technique. The address of the Input device is =F8F8 H The Instruction for correct data transfer is = LD F8F8H 4. ns: (b) Out put of 8 Decoder is used for selecting the output port. Select code is H This mapping is memory mapped I/O CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

19 : 9 : Digital & Microprocessors 5. ns: (d) =8H =FFH =8H =FFH =8H =FFH =8H =FFH 6. ns: (a) ddress Range given is cs 8 k ROM H FFFH To provide cs as low, The condition is 5 = 4 = and = (or) () i.e 5 = 4 = and shouldn t be,. Thus it is [ +, ] CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

20 : : Digital & Microprocessors 7. ns: (a) 5 :8 Decoder 4 5, 4 are used for chip selection,, are used for input of decoder Enable of Input of decoder ddress of decoder chip Size of each memory block = = K CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

21 Chapter Instruction set of 885 & Programming with 885. ns: (c) 6H : LXI H,879H ; (HL) = 879H 6H : MOV, L ; ()(L) = 79 64H : DD H ; () = + ; (H) = ; () = CY =, C = 65H : D ; 66 dded to () since CY= & C = ; () = 69H 66H : MOV H, ; (H)() =69H 67H : PCHL ; (PC)(HL) = 6979H. ns: (c) H : LXI SP, FFH ; (SP) = FFH H : LXI H, 7 H ; (HL) = 7H 6H : MVI, H ; () = H 8H : SU M ; ()()-(7) ; (7) = H ; () = H The contents of ccumulator is H. ns: (c) SU : MVI, H H CLL SU program will shifted to SU address location SU : INR H RET returned to the main program The contents of ccumulator after execution of the above SU is H 4. ns: (c) The loop will be executed until the value in register equals to zero, then, Execution time =9(7T+4T+4T+T)+( 7T+4T+4T+7T)+7T = 54T 5. ns: (d) H=55 : L = 55, 54, 5, ---- H=54 : L =, 55, 54, H= : L =,55,54,5,--- H= : In first iteration (with H=55), the value in L is decremented from 55 to i.e., 55 times In further remaining 54 iterations, the value in L is decremented from to i.e., 56 times DCRL instruction gets executed for [ 55 (54 56)] 6579 times 6. ns: (a) ST 4H is a -yte Instruction and it requires 4 Machine cycles (Opcode fetch, Operand Read, Operand Read, Memory write). The Higher order ddress ( 5 8 ) sent in 4 machine cycles is as follows Given ST 4 is stored at FFEH CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

22 : : Digital & Microprocessors i.e., ddress Instruction FFE, FFF, : ST 4H Machine cycle. Opcode fetch. Operand Read. Operand Read 4. Memory Write ddress ( 5 - ) FFEH FFFH H 4H Higher order address ( 5-8 ) FH FH H H i.e. Higher order ddress sent on 5-8 for 4 Machine Cycles are FH, FH, H, H. 7. ns: (d) The operation SI E H indicates -E where indicates accumulator Thus the result of the subtraction operation is stored in the accumulator and the contents of accumulator are changed. 8. ns: (c) If the content in register is to be multiplied with the content in register C, the contents of register is added to the accumulator (initial value of accumulator is ) for C times. CE Engg. Publications Hyderabad Delhi hopal Pune hubaneswar engaluru Lucknow Patna Chennai Vijayawada Vizag Tirupati Kukatpally Kolkata

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph: Serial : 5SP_CS_W_Digital Logic_598 Delhi Noida hopal Hyderabad Jaipur Lucknow Indore Pune hubaneswar Kolkata Patna Web: Email: info@madeeasy.in Ph: 452462 CLSS TEST 289 COMPUTER SCIENCE & IT Subject :