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1 Serial : S_CS_C_Digital Logic_588 Delhi Noida hopal Hyderabad Jaipur Lucknow Indore Pune hubaneswar Kolkata Patna Web: info@madeeasy.in Ph: -56 CLASS TEST 8-9 COMPUTER SCIENCE & IT Subject : Digital Logic Date of test : 5/8/8 Answer Key. (b) 7. (c). (a) 9. (a) 5. (a). (b) 8. (b). (d). (c) 6. (b). (d) 9. (c) 5. (a). (b) 7. (b). (c). (d) 6. (a). (a) 8. (b) 5. (b). (a) 7. (d). (a) 9. (b) 6. (b). (c) 8. (c). (c). (b)

2 CT-8 CS Digital Logic 7. (b) to get X =, Detailed Explanations X = (A ) ( C ) C A = C = C = for (AC) = () A =, C =, C = X = for (AC) = () A =, C =, C = X = for (AC) = () A =, C =, C = X = for (AC) = () A =, C =, C = X =. (b) Y = c F = Y = dy + dc = dc + dc = c d. (d) Given, f = A + A + A = A + + A + A = A + + A f = A A = A A =. (c) Output of the : MUX circuit in Figure A is Output of the circuit in Figure is Y = I A + I A + I A + I A On comparison Y = A C = AC + AC + AC + AC I I I I 5. (b) Simplifying boolean expression: F ( + C) (A + + C) = (C + CC) (A + + C) = (C + C) (A + + C) ( + ) (A + + C) (A + + C) = AC + C + C ( + A + )

3 8 Computer Science & IT 6. (b) Let the base be x, then 9 = x = x + x + x + x 7. (c) A J K Q Qn n+ = 9 = x + x + = 6 (y substitution) Q n + = A + A + AQn Q n + = + AQ n = + AQn 8. (b) Y = I SS + I SS + I SS + I SS Y = A + () = + A = A + 9. (c) Number of flip-flops for mod-6 ripple counter = Maximum clock frequency = 9 Hz = 5 MHz p p = = = 5. (d) Number of unused states in Johnson counter = k k k k = k = 5. (a) Minimum time taken for all flip-flops to stabilize is (75 ns 8) + 5 = 65 ns Frequency of operation must be less than, 65ns =.5 MHz. (c) Decimal input = 9 CD = Output of Gray code converter = Y corresponds to I m with (S n...s ) is = () m = 9

4 CT-8 CS Digital Logic 9. (a) (6) 7 = (7) (67) 8 = (55) (98) = (98) (Z) 5 = (Z) 5 () 9 = (99) (Z) 5 = (99) (7) (55) (98) (Z) 5 = (9) Converting (9) = () 5 Z =. (d) F = ( X + Y)( Z + W) F = XY Z + XY W = XY Z + XY W = ( XY Z ) ( XY W ) Z XY Z X Y W XY W F So, minimum two input NAND gates are required. 5. (a) In the given digital circuit each multiplexer is working as a NOT gate thus it is a ring oscillator with five NOT gates. The frequency of oscillation will be f = Nt pd. N = number of NOT gates in cascade = propagation delay of each NOT gate. t pd f = = 5 5ns 6 Hz = MHz. 6. (a) For the given MUX, A and are select lines and C be the input I I I I C C So, I = = a

5 Computer Science & IT 7. (d) I I I = = b = = c = = d So, a d = b c = So, output of NAND gate is i.e. MUX E connected to. The MUX is in disable state. MUX is having active high enable, but E =, so that MUX is in disable state. Hence MUX output Z is equal to. FFD FFT Q D Q T D = Q T T = Q T Q D Clock pulse So, output will either be or and never. 8. (c) Initially Clock pulse SIPO PISO So, after 8 pulses, the output from PISO will be same as input in SIPO. 9. (a) State table can be drawn from state diagram Present state Input Next state Q n X Q n + Q n + = Qn + X (Q n + represent output of NOR gate)

6 CT-8 CS Digital Logic. (c) For st MUX, I I I I So, f (A,, C) = AC + AC + AC + AC = Σ m (,,, 7) For nd MUX, I I = I = I So, f (A,, C) = AC + A + A + A C = Σ m (,,, 7) So, f (A,, C) represents the difference of full substractor while f (A,, C) represents the borrow of full substractor.. (b) The k-map has to rearranged as AC CD A D AC F = AC + D + AC. (a) In the circuit, we have D = QQ = Q+ Q D = Q D = Q The truth table for the circuit is obtained below: CLK number initial Present State Q Q Q Inputs D D D Q + Next State Q + Q After clock pulses, output is Q Q Q =

7 Computer Science & IT. (a) A A+ y A + = ( A+ )( A+ ) = A + A = A HIGH A LOW HIGH LOW HIGH Y LOW t t 7 t t 8 t t 9 t t t 5 t t 6. (c) An Ex-OR gate can be represented as A Z A Z nsec nsec nsec So, for EX-OR gate, it will take nsec to get the output. c n X b n a n nsec 6 nsec nsec 5 Y 5 nsec So, to get the output Y, it will take 5 nsec. nsec 5. (a) The total delay for synchronous series counter = t pd (of FF) + (n ) t pd (of AND gate) where n = no. of Flip Flops. As M n (Where M = modulus) So, 56 n n = 8 Total delay = 5 + (8 ) 5 = 5 + = 55 nsec So, the maximum frequency of MOD-56 counter will be = 55 sec n = 8.8 MHz

8 CT-8 CS Digital Logic 6. (b) FFO FFI CLK Q Q J = Q K = J = Q K = Q N = 7. (b) Given, input frequency = 6 khz Output frequency after -bit ring counter = 6 6kHz = Output frequency after -bit Jhonson counter = 6 khz 8 = Output frequency after decade counter = khz = 8. (b) The output z is connected from inverted outputs of the FFs through AND gate, i.e. z = QAQQC = QA + Q + QC Hence, the output z will be high only when all FF s output are zero, i.e. Q A = Q = Q C = Let initially z =, then we obtain the truth table for the circuit as CLK number initial 5 6 Present State Inputs Next State Q A Q Q C J A = K A = J = Q C K = J C = Q K C = Q A Q Q C z It is MOD-6 counter. So, output z will be after 6 clock pulses.

9 Computer Science & IT 9. (b) f (A,, C) = Σ(,, ) f (A,, C) = ΠM(,,, 6, 7) = Σ(,, 5) f f = Σm(, ) For function f to be zero f = ΠM(, ). (b) f (A,, C) = [ f (A,, C) f (A,, C)] = Σ(,,, 5, 6, 7) Maximum minterms possible are 6. T A = Q A + Q T = QA + Q Present State FF Input Next State + + Q A Q T A T Q A Q counter counts the sequence of Thus, MOD counter.

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph: Serial : 5SP_CS_W_Digital Logic_598 Delhi Noida hopal Hyderabad Jaipur Lucknow Indore Pune hubaneswar Kolkata Patna Web: Email: info@madeeasy.in Ph: 452462 CLSS TEST 289 COMPUTER SCIENCE & IT Subject :