Layout of 7400-series Chips Commonly Used in. CDA 3101: Introduction to Computer Hardware and Organization

Transcription

1 Layout of 400-series Chips Commonly Used in CDA 30: Introduction to Computer Hardware and Organization Charles N. Winton Department of Computer and Information Sciences University of North Florida 999

2 Vcc : QUAD 2-INPUT NAND

3 : TRIPLE 3-INPUT NAND

4 : DUAL 4-INPUT NAND

5 : 8-INPUT NAND

6 : QUAD 2-INPUT NOR

7 : TRIPLE 3-INPUT NOR

8 : INVERTERS

9 : QUAD 2-INPUT AND

10 : TRIPLE 3-INPUT AND

11 : DUAL 4-INPUT AND

12 : QUAD 2-INPUT OR

13 : QUAD 2-INPUT XOR

14 Make No External Connection : DUAL 2-WIDE 2-INPUT AOI

15 Data Inputs Address Inputs V cc Data Inputs 45: 8-INPUT MULTIPLEXER 5 Output 6 Output Active on Enable LOW (otherwise Output is HIGH) Enable 8

16 Inputs Outputs A B C D 9 8 A =, B = 2, C = 4, D = 8 Selected output goes LOW Outputs 442: 4 TO 0 LINE BCD TO DECIMAL DECODER

17 Outputs (5V) f g a b c d e a The ripple blanking inputs (BI and BI/RBI) are normally held HIGH (they provide for zero suppression). Lamp Test LOW selects all segments. Selected output goes LOW B=2 C=4 D=8 A= f e g b c d B C D A Inputs 2 3 Lamp Test 4 BI/RBI 5 RBI 6 Inputs 8 44: BCD TO -SEGMENT DECODER DRIVER

18 Data Outputs When enable input G is HIGH, a binary input on Select inputs C, B, A turns the corresponding output line LOW (the remaining output lines are HIGH). The output selected is based on C=4, B=2, A=. When G is LOW, all the output lines are HIGH. A B C 2 Select 3 Tie to Tie to LOW LOW G Enable Data Output 438: 3 TO 8 DECODER/DEMULTIPLEXER 8

19 24 Select Enable Outputs A B C D G2 G When enable inputs G2 and G are both LOW, a binary input on Select inputs D, C, B, A turns the corresponding output line LOW (the remaining output lines are HIGH). The output selected is based on D=8, C=4, B=2, A=. When either G2 or G is HIGH, all the output lines are HIGH Outputs 454: 4 TO 6 LINE DECODER 2

20 Data Inputs A 3 B 2 A 2 A B A 0 B 0 Words of length > 4 are compared by connecting comparators in cascade. Word order is A 3, A 2, A, A 0 and B 3, B 2, B, B 0 with A 3 and B 3 the most significant bits. Data Input B 3 A<B A=B A>B A<B A=B A>B 2 3 Cascade Inputs 4 485: 4-BIT MAGNITUDE COMPARATOR 5 6 Outputs 8

21 Input(A) Q 0 Q 3 Q Q Q 3, Q 2, Q, Q 0 are the state outputs of 4 internal JK Master-Slave flip-flops connected as a standard BCD counter. To reset to 0 both Resets must be HIGH. Pulse Input(A) for the BCD counting sequence. (There are alternate connections to permit divide by 5 and 9's complement support) Tie to Q 0 Reset Reset V cc Tie to 0 Tie to 0 490: DECADE COUNTER

22 Input(A) Q 0 Q 3 Q Q Q 3, Q 2, Q, Q 0 are the state outputs of 4 internal JK Master-Slave flip-flops connected as a standard Mod 6 counter. To reset to 0 both Resets must be HIGH. Pulse Input(A) for the Mod 6 counting sequence. (There are alternate connections to permit divide by 2 and divide by 8 support) Tie to Q Reset Reset V cc 493: 4-BIT BINARY COUNTER

23 Data Clear Outputs Load Data A Borrow Carry C D V cc (Presettable, Synchronous, Dual Clocks) Pulse the Count Up or Count Down clock to produce the change of count on Q D, Q C, Q B, Q A (hold the clock not in use HIGH). Setting data on D, C, B, A with Load LOW and then taking Load HIGH will preset the counter. Likewise, taking Clear from LOW to HIGH will zero the counter. In cascading counters, for counting up, the Carry goes to the Count Up of the next counter; for counting down, the Borrow goes to the Count Down of the next counter. Count Count B Q B Q A Down Up Q C Q D Data Outputs Inputs Outputs 493: 4-BIT BINARY UP/DOWN COUNTER

24 C C BUFFER IS ACTIVE WHEN C IS HIGH C C : QUAD TRI-STATE BUFFER

25 G BA B B 2 B 3 B ISOLATED IF G BA = L G AB = H G BA = H G AB = H G BA = L G AB = L 2 G AB A A 2 A 3 A : QUADRUPLE BUS TRANSCEIVER

26 20 9 G(2) B () A (2) B 2 () A 2 (2) B 3 () A 3 (2) B 4 () A 4 (2) G() A () B (2) A 2 () B 2 (2) A 3 () B 3 (2) A 4 () B 4 (2) 4244: OCTAL TRI-STATE BUFFERS/LINE DRIVERS

27 J() Q() Q() K(2) Q(2) Q(2) J Q J Q K Q CLR K Q CLR 2 3 (NEGATIVE EDGE TRIGGERED WITH CLEAR) Clock() Clear() K() V cc Clock(2) Clear(2) 43: DUAL JK MASTER-SLAVE FLIP-FLOP J(2)

28 Clear(2) D(2) Clock(2) Set(2) Q(2) Q(2) (POSITIVE EDGE TRIGGERED) CLR Q D PR Q D PR Q CLR Q (WITH PRESET & PRECLEAR) Clear() D() Clock() Set() Q() Q() 44: DUAL D FLIP-FLOP

29 K() Q() Q() K(2) Q(2) Q(2) J(2) J PR Q J PR Q CK CK K Q CLR K Q CLR Clock() Set() Clear() J() V cc Clock(2) Set(2) Clear(2) 46: DUAL JK MASTER-SLAVE FLIP-FLOP (WITH PRESET AND PRECLEAR, NEGATIVE EDGE TRIGGERED)

30 B 3 S 3 C OUT C IN B 0 A 0 S Adder A 3 Adder A 2 Adder A Adder A 0 B 3 B 2 B B 0 C O3S3 C I3 C O2S2 C I2 C OS C I C O0S0 C I A 3 S 2 A 2 B 2 V cc S B A 483: 4-BIT BINARY FULL ADDER W/FAST CARRY

31 Parallel Outputs Shift V cc Right Load Q A Q B Q C Q D For a right shift, set Mode Control LOW and pulse the Shift Right input. The shift direction is Serial Data Q A Q B Q C Q D. For a parallel load from the inputs A, B, C, D set Mode Control HIGH then pulse the Load input. A shift left requires connecting Q B to A, Q C to B, Q D to C, and the Serial Input to D, then executing a parallel load. Serial Input A B C D Parallel Inputs 6 Mode Control 495: 4-BIT BIDIRECTIONAL PARALLEL SHIFT REG

32 A A 8 A 9 CS D OUT D IN V cc A 6 A 5 WE A A 2 A 3 A 4 A 0 202: K x -BIT STATIC RAM - Vcc = +5V

33 A A 8 A 9 I/O I/O 2 I/O 3 I/O 4 WE A 6 A 5 A 4 A 3 A 0 A A 2 CS 24: K x 4-BIT STATIC RAM - Vcc = +5V

34 +5V: V CC 408: AND 432: OR 404: NOT x I I 0 z z INPUTS OUTPUTS SELECT x z DATA I I 0 z 2-INPUT MULTIPLEXER University of North Florida Department of Computer and Information Sciences Breadboard Template, 999

35 University of North Florida Department of Computer and Information Sciences Breadboard Template, 999