X9279. Single Supply/Low Power/256-Tap/2-Wire Bus. Single Digitally-Controlled (XDCP ) Potentiometer FN Data Sheet November 22, 2005

Transcription

1 X9279 ingle upply/low Power/256-ap/2-ire Bus Data heet FN ingle Digitally-ontrolled (XDP ) Potentiometer FEUE 256 esistor aps 2-ire erial Interface for rite, ead, and ransfer perations of the Potentiometer iper esistance, 100Ω 5V 16 Nonvolatile Data egisters for Each Potentiometer Nonvolatile torage of Multiple iper Positions Power-on ecall. Loads aved iper Position on Power-up. tandby urrent < 5µ Max V : 2.7V to 5.5V peration 50kΩ, 100kΩ Versions of End to End esistance Endurance: 100,000 Data hanges per Bit per egister 100 yr. Data etention 14 Ld P Low Power M Pb-Free Plus nneal vailable (oh ompliant) DEIPIN he X9279 integrates a single digitally controlled potentiometer (XDP) on a monolithic M integrated circuit. he digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. he position of the wiper on the array is controlled by the user through the 2-ire bus interface. he potentiometer has associated with it a volatile iper ounter egister () and a four nonvolatile Data egisters that can be directly written to and read by the user. he contents of the controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (D0) to the. he XDP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNINL DIGM V H 2-ire Bus Interface ddress Data tatus Bus Interface and ontrol rite ead ransfer Inc/Dec ontrol Power-on ecall iper ounter egister () Data egisters 16 Bytes wiper 50kΩ and 100kΩ 256-taps P V L 1 UIN: hese devices are sensitive to electrostatic discharge; follow proper I Handling Procedures INEIL or Intersil (and design) is a registered trademark of Intersil mericas Inc. XDP is a trademark of Intersil mericas Inc. opyright Intersil mericas Inc ll ights eserved ll other trademarks mentioned are the property of their respective owners.

2 rdering Information P NUMBE P MING V LIMI (V) PENIMEE GNIZIN (kω) EMP NGE ( ) PGE X9279V14* X9279V 5 ±10% to Ld P (4.4mm) X9279V14Z* X9279VZ 0 to Ld P (4.4mm) (Pb-free) X9279V14I* X9279V I -40 to Ld P (4.4mm) X9279V14IZ* X9279V ZI -40 to Ld P (4.4mm) (Pb-free) X9279UV14* X9279UV 50 0 to Ld P (4.4mm) X9279UV14Z* (Note) X9279UV Z 0 to Ld P (4.4mm) (Pb-free) X9279UV14I* X9279UV I -40 to Ld P (4.4mm) X9279UV14IZ* (Note) X9279UV ZI -40 to Ld P (4.4mm) (Pb-free) X9279V14-2.7* X9279V F 2.7 to to Ld P (4.4mm) X9279V14Z-2.7* X9279V ZF 0 to Ld P (4.4mm) (Pb-free) X9279V14I-2.7* X9279V G -40 to Ld P (4.4mm) X9279V14IZ-2.7* X9279V ZG -40 to Ld P (4.4mm) (Pb-free) X9279UV14-2.7* X9279UV F 50 0 to Ld P (4.4mm) X9279UV14Z-2.7* (Note) X9279UV ZF 0 to Ld P (4.4mm) (Pb-free) X9279UV14I-2.7* X9279UV G -40 to Ld P (4.4mm) X9279UV14IZ-2.7* (Note) X9279UV ZG -40 to Ld P (4.4mm) (Pb-free) *dd "1" suffix for tape and reel. NE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are oh compliant and compatible with both npb and Pb-free soldering operations. Intersil Pb-free products are ML classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J D-020. DEILED FUNINL DIGM V Bank 0 Power-on ecall L D 2 1 INEFE ND NL IUIY D0 D1 IPE UNE EGIE () D2 D3 50kΩ and 100kΩ 256-taps H L 0 D Bank 1 Bank 2 Bank 3 P D0 D1 D0 D1 D0 D1 ontrol D2 D3 D2 D3 D2 D3 12 additional nonvolatile registers 3 Banks of 4 registers x 8-bits V 2 FN8175.3

3 IUI LEVEL PPLIIN Vary the gain of a voltage amplifier Provide programmable dc reference voltages for comparators and detectors ontrol the volume in audio circuits rim out the offset voltage error in a voltage amplifier circuit et the output voltage of a voltage regulator rim the resistance in heatstone bridge circuits ontrol the gain, characteristic frequency and Q-factor in filter circuits et the scale factor and zero point in sensor signal conditioning circuits Vary the frequency and duty cycle of timer Is Vary the dc biasing of a pin diode attenuator in F circuits Provide a control variable (I, V, or ) in feedback circuits YEM LEVEL PPLIIN djust the contrast in LD displays ontrol the power level of LED transmitters in communication systems et and regulate the D biasing point in an F power amplifier in wireless systems ontrol the gain in audio and home entertainment systems Provide the variable D bias for tuners in F wireless systems et the operating points in temperature control systems ontrol the operating point for sensors in industrial systems rim offset and gain errors in artificial intelligent systems PIN NFIGUIN N 0 N 2 L D V P 1 14 X V L H 3 1 P PIN IGNMEN Pin P ymbol Function 1 N No onnect 2 0 Device ddress for 2-ire bus. 3 N No onnect 4 2 Device ddress for 2-ire bus. 5 L erial lock for 2-ire bus. 6 D erial Data Input/utput for 2-ire bus. 7 V ystem Ground. 8 P Hardware rite Protect 9 1 Device ddress for 2-ire bus Device ddress for 2 wire-bus. 11 iper erminal of the Potentiometer. 12 H High erminal of the Potentiometer. 13 L Low erminal of the Potentiometer. 14 V ystem upply Voltage. 3 FN8175.3

4 PIN DEIPIN Bus Interface Pins EIL D INPU/UPU (D) he D is a bidirectional serial data input/output pin for a 2-ire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-ire master at the rising edge of the serial clock L, and it shifts out data after each falling edge of the serial clock L. It is an open drain output and may be wire-ed with any number of open drain or open collector outputs. n open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. EIL L (L) his input is used by 2-ire master to supply 2-ire serial clock to the X9279. DEVIE DDE (2-0) he ddress inputs are used to set the least significant 3 bits of the 8-bit slave address. match in the slave address serial data stream must be made with the ddress input in order to initiate communication with the X9279. maximum of 8 devices may occupy the 2-ire serial bus. Potentiometer Pins H, L he H and L pins are equivalent to the terminal connections on a mechanical potentiometer. he wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias upply Pins YEM UPPLY VLGE (V ) ND UPPLY GUND (V ) he V pin is the system supply voltage. he V pin is the system ground. ther Pins N NNE No connect pins should be left open. his pins are used for Intersil manufacturing and testing purposes. HDE IE PE INPU (P) he P pin when L prevents nonvolatile writes to the Data egisters. 4 FN8175.3

5 PINIPLE F PEIN he X9279 is a integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. his section provides detail description of the following: esistor rray Description. erial Interface Description. Instruction and egister Description. rray Description he X9279 is comprised of a resistor array (ee Figure 1). he array contains, in effect, 255 discrete resistive segments that are connected in series. he physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer ( H and L inputs). t both ends of each array and between each resistor segment is a M switch connected to the wiper ( ) output. ithin each individual array only one switch may be turned on at a time. hese switches are controlled by a iper ounter egister (). he 8-bits of the ([7:0]) are decoded to select, and enable, one of 256 switches (ee able 1). he may be written directly. hese Data egisters can the can be read and written by the host system. Power-up and Down ecommendations. here are no restrictions on the power-up or powerdown conditions of V and the voltages applied to the potentiometer pins provided that V is always more positive than or equal to V H, V L, and V, i.e., V V H, V L, V. he V ramp rate specification is always in effect. Figure 1. Detailed Potentiometer Block Diagram EIL D PH FM INEFE IUIY EGIE 0 EGIE 1 (D0) (D1) 8 8 BN_0 nly EIL BU INPU PLLEL BU INPU U N E H EGIE 2 EGIE 3 (D2) (D3) IF = 00[H] HEN = L IF = FF[H] HEN = H UP/DN MDIFIED IPE UNE EGIE () IN/DE LGI UP/DN L D E D E L 5 FN8175.3

6 EIL INEFE DEIPIN erial Interface he X9279 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master will always initiate data transfers and provide the clock for both transmit and receive operations. herefore, the X9279 will be considered a slave device in all applications. lock and Data onventions Data states on the D line can change only during L L periods. D state changes during L HIGH are reserved for indicating start and stop conditions. ee Figure 2. tart ondition ll commands to the X9279 are preceded by the start condition, which is a HIGH to L transition of D while L is HIGH. he X9279 continuously monitors the D and L lines for the start condition and will not respond to any command until this condition is met. ee Figure 2. top ondition ll communications must be terminated by a stop condition, which is a L to HIGH transition of D while L is HIGH. ee Figure 2. cknowledge cknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. he transmitting device, either the master or the slave, will release the D bus after transmitting eight bits. he master generates a ninth clock cycle and during this period the receiver pulls the D line L to acknowledge that it successfully received the eight bits of data. he X9279 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9279 will respond with a final acknowledge. ee Figure 2. Figure 2. cknowledge esponse from eceiver L FM ME D UPU FM NMIE D UPU FM EEIVE NLEDGE 6 FN8175.3

7 cknowledge Polling he disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPM write cycle time. nce the stop condition is issued to indicate the end of the nonvolatile write command the X9279 initiates the internal write cycle. polling, Flow 1, can be initiated immediately. his involves issuing the start condition followed by the device slave address. If the X9279 is still busy with the write operation no will be returned. If the X9279 has completed the write operation an will be returned and the master can then proceed with the next operation. FL 1: Polling equence Nonvolatile rite ommand ompleted Enter Polling Issue Issue lave ddress eturned? Yes Further peration? Yes Issue Instruction Proceed No No Issue P Issue P Proceed INUIN ND EGIE DEIPIN Device ddressing: Identification Byte ( ID and ) he first byte sent to the X9279 from the host, following a going HIGH to L, is called the Identification byte. he most significant four bits of the slave address are a device type identifier. he ID[3:0] bits is the device ID for the X9279; this is fixed as 0101[B] (refer to able 1). he [2:0] bits in the ID byte is the internal slave address. he physical device address is defined by the state of the 2-0 input pins. he slave address is externally specified by the user. he X9279 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9279 to successfully continue the command sequence. nly the device which slave address matches the incoming device address sent by the master executes the instruction. he 2-0 inputs can be actively driven by M input signals or tied to V or V. Instruction Byte (I) he next byte sent to the X9279 contains the instruction and register pointer information. he three most significant bits are used provide the instruction opcode I [2:0]. he B and bits point to one of the four Data egisters. P0 is the P selection; since the X9279 is single P, the P0 = 0. he format is shown in able 2. egister Bank election (B,, P1, P0) here are 16 registers organized into four banks. Bank 0 is the default bank of registers. nly Bank 0 registers can be used for Data egister to iper ounter egister operations. Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for 2-ire write and read operations. he Data egisters in Banks 1, 2, and 3 cannot be used for direct read/write operations between the iper ounter egister. 7 FN8175.3

8 egister election (0 to 3) able egister B election perations Data egister ead and rite; iper ounter egister perations Data egister ead and rite; iper ounter egister perations Data egister ead and rite; iper ounter egister perations Data egister ead and rite; iper ounter egister perations egister Bank election (Bank 0 to Bank 3) able P1 P0 Bank election perations Data egister ead and rite; iper ounter egister perations Data egister ead and rite nly Data egister ead and rite nly Data egister ead and rite nly able 1. Identification Byte Format Device ype Identifier et to 0 for proper operation Internal lave ddress ID3 ID2 ID1 ID (MB) (LB) able 2. Instruction Byte Format Instruction pcode egister election P1 and P0 are used also for register Bank election for 2-ire egister rite and ead operations egister election I3 I2 I1 I0 B P1 P0 (MB) (LB) Pot election (Bank election) et to P0 = 0 for potentiometer operations egister elected B D0 0 0 D1 0 1 D2 1 0 D FN8175.3

9 able 3. Instruction et Instruction ead iper ounter egister rite iper ounter egister XF iper ounter egister to Data egister Increment/Decrement iper ounter egister Note: 1/0 = data is one or zero Instruction et I3 I2 I1 I0 B P 1 P 0 peration ead the contents of the iper ounter egister rite new value to the iper ounter egister ead Data egister /0 1/0 1/0 1/0 ead the contents of the Data egister pointed to by P1 - P0 and B - rite Data egister /0 1/0 1/0 1/0 rite new value to the Data egister pointed to by P1 - P0 and B - XF Data egister to iper ounter egister X /0 1/0 0 0 ransfer the contents of the Data egister pointed to by B - (Bank 0 only) to the iper ounter egister /0 1/0 0 0 ransfer the contents of the iper ounter egister to the egister pointed to by B- (Bank 0 only) Enable Increment/decrement of the iper ounter egister DEVIE DEIPIN iper ounter egister () he X9279 contains contains a iper ounter egister, for the DP potentiometer. he iper ounter egister can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. he contents of the can be altered in four ways: it may be written directly by the host via the rite iper ounter egister instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XF Data egister instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (ee Instruction section for more details). Finally, it is loaded with the contents of its Data egister zero (D0) upon power-up. he iper ounter egister is a volatile register; that is, its contents are lost when the X9279 is powereddown. lthough the register is automatically loaded with the value in D0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the D0 value into the. he D0 value of Bank 0 is the default value. Data egisters (D) he potentiometer has four 8-bit nonvolatile Data egisters (D3-D0). hese can be read or written directly by the host. Data can also be transferred between any of the four Data egisters and the associated iper ounter egister. ll operations changing data in one of the Data egisters is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data egisters can be used as regular memory locations for system parameters or user preference data. Bit [7:0] are used to store one of the 256 wiper positions (0~255). 9 FN8175.3

10 able 4. iper counter egister, (8-bit), [7:0]: Used to store the current wiper position (Volatile, V) V V V V V V V V (MB) (LB) able 5. Data egister, D (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NV NV NV NV NV NV NV NV MB LB Instructions Four of the seven instructions are three bytes in length. hese instructions are: ead iper ounter egister read the current wiper position of the potentiometer, rite iper ounter egister change current wiper position of the potentiometer, ead Data egister read the contents of the selected Data egister; rite Data egister write a new value to the selected Data egister. he basic sequence of the three byte instructions is illustrated in Figure 4. hese three-byte instructions exchange data between the and one of the Data egisters. transfer from a Data egister to a is essentially a write to a static M, with the static M controlling the wiper position. he response of the wiper to this action will be delayed by t L. transfer from the (current wiper position), to a Data egister is a write to nonvolatile memory and takes a minimum of t to complete. he transfer can occur between the potentiometer and one of its four associated registers (Bank 0). wo instructions require a two-byte sequence to complete. hese instructions transfer data between the host and the X9279; either between the host and one of the data registers or directly between the host and the iper ounter egister. hese instructions are: XF Data egister to iper ounter egister his transfers the contents of one specified Data egister to the iper ounter egister. XF iper ounter egister to Data egister his transfers the contents of the iper ounter egister to the specified Data egister. he final command is Increment/Decrement (Figure 5 and 6). he Increment/Decrement command is different from the other commands. nce the command is issued and the X9279 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each L clock pulse (t HIGH ) while D is HIGH, the selected wiper will move one resistor segment towards the H terminal. imilarly, for each L clock pulse while D is L, the selected wiper will move one resistor segment towards the L terminal. ee Instruction format for more details. Figure 3. wo-byte Instruction equence L D ID3 ID2 ID1 ID I3 I2 I1 I0 B P1 P0 Device ID Internal Instruction ddress pcode egister ddress Pot/Bank ddress P hese commands only valid when P1 = P0 = 0 10 FN8175.3

11 Figure 4. hree-byte Instruction equence L D ID3 ID2 ID1 ID I3 I2 I1 I0 B P1 P0 Device ID External Instruction ddress pcode egister Pot/Bank ddress ddress D7 D6 D5 D4 D3 D2 D1 D0 [7:0] valid only when P1=P0=0; or Data egister D[7:0] for all values of P1 and P0 P Figure 5. Increment/Decrement Instruction quence L D ID3 ID2 ID1 ID I3 I2 I1 I0 Device ID External Instruction ddress pcode B egister ddress P1 P0 Pot/Bank ddress I N 1 I N 2 I N n D E 1 D E n P Figure 6. Increment/Decrement iming Limits IN/DE MD Issued t ID L D V / Voltage ut 11 FN8175.3

12 INUIN FM ead iper ounter egister () Device ype Identifier Device ddresses Instruction pcode D/Bank ddresses iper Position (ent by X9279 on D) M P rite iper ounter egister () Device ype Identifier Device ddresses Instruction pcode D/Bank ddresses iper Position (ent by Master on D) P ead Data egister (D) Device ype Identifier Device ddresses Instruction pcode D/Bank ddresses B P1 P0 iper Position (ent by X9279 on D) M P rite Data egister (D) Device ype Identifier Device ddresses Instruction pcode D/Bank ddresses B P1 P0 iper Position (ent by Master on D) P HIGH-VLGE IE YLE ransfer iper ounter egister () to Data egister (D) Device ype Identifier Device ddresses Instruction pcode D/Bank ddresses B 0 0 P HIGH-VLGE IE YLE 12 FN8175.3

13 ransfer Data egister (D) to iper ounter egister () Device ype Identifier Device ddresses Instruction pcode D/Bank ddresses B 0 0 P Increment/Decrement iper ounter egister () Device ype Identifier Device ddresses Instruction pcode D/Bank ddresses Increment/Decrement (ent by Master on D) I/D I/D.... I/D I/D P Notes: (1) M / : stands for the acknowledge sent by the master/slave. (2) 3 ~ 0 : stands for the device addresses sent by the master. (3) X : indicates that it is a 0 for testing purpose but physically it is a don t care condition. (4) I : stands for the increment operation, D held high during active L phase (high). (5) D : stands for the decrement operation, D held low during active L phase (high). 13 FN8175.3

14 BLUE MXIMUM ING emperature under bias to +135 torage temperature to +150 Voltage on L, D any address input with respect to V... -1V to +7V V = (V H - V L )...5.5V Lead temperature (soldering, 10s) I (10s)...±6m MMEN tresses above those listed under bsolute Maximum atings may cause permanent damage to the device. his is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EMMENDED PEING NDIIN emp Min. Max. ommercial Industrial Device upply Voltage (V ) (4) Limits X9279 5V ± 10% X V to 5.5V NLG HEII (ver recommended industrial (2.7V) operating conditions unless otherwise stated.) ymbol Parameter Limits Min. yp. Max. Units est onditions L End to End esistance 100 kω version L End to End esistance 50 kω U version End to End esistance olerance ±20 % Power ating 50 m 25, each pot I iper urrent ±3 m iper esistance 300 Ω I = ± V = 3V iper esistance 150 Ω I = ± V = 5V V EM Voltage on any H or L Pin V V V V = 0V Noise -120 dbv/ Hz ef: 1V esolution 0.4 % bsolute Linearity (1) ±1 MI (3) w(n)(actual) - (5) w(n)(expected) elative Linearity (2) ±0.2 MI (3) w(n + 1) - [ w(n) + MI ] (5) emperature oefficient of L ±300 ppm/ atiometric emp. oefficient 20 ppm/ H / L / Potentiometer apacitances 10/10/25 pf ee Macro model Notes: (1) bsolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) elative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = / 255 or ( H - L ) / 255, single pot (4) During power-up V > V H, V L, and V. (5) n = 0, 1, 2,...,255; m =0, 1, 2,..., FN8175.3

15 D.. PEING HEII (ver the recommended operating conditions unless otherwise specified.) ymbol I 1 I 2 ENDUNE ND D EENIN PINE PE-UP IMING Parameter V supply current (active) V supply current (nonvolatile write).. E NDIIN Limits Min. yp. Max. Units est onditions 3 m f L = 400kHz; V = +6V; D = pen; (for 2-ire, ctive, ead and Volatile rite tates only) 5 m f L = 400kHz; V = +6V; D = pen; (for 2-ire, ctive, Nonvolatile rite tate only) I B V current (standby) 5 µ V = +6V; V IN = V or V ; D = V ; (for 2-ire, tandby tate only) I LI Input leakage current 10 µ V IN = V to V I L utput leakage current 10 µ V U = V to V V IH Input HIGH voltage V x 0.7 V + 1 V V IL Input L voltage -1 V x 0.3 V V L utput L voltage 0.4 V I L = 3m V H utput HIGH voltage Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years ymbol est Max. Units est onditions (6) IN/U Input / utput capacitance (D) 8 pf V U = 0V (6) IN Input capacitance (L, P, 2, 1 and 0) 6 pf V IN = 0V ymbol Parameter Min. Max. Units t r V (6) V Power-up rate V/ms t (7) PU Power-up to initiation of read operation 1 ms t (7) PU Power-up to initiation of write operation 50 ms Input Pulse Levels V x 0.1 to V x 0.9 Input rise and fall times 10ns Input and output timing level V x 0.5 Notes: (6) his parameter is not 100% tested (7) t PU and t PU are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued. hese parameters are periodically sampled and not 100% tested. 15 FN8175.3

16 EQUIVLEN.. LD IUI 5V 3V PIE Macromodel 1533Ω 867Ω L D pin D pin H L 100pF 100pF L 10pF 25pF L 10pF IMING ymbol Parameter Min. Max. Units f L lock Frequency 400 khz t Y lock ycle ime 2500 ns t HIGH lock High ime 600 ns t L lock Low ime 1300 ns t U: tart etup ime 600 ns t HD: tart Hold ime 600 ns t U: top etup ime 600 ns t U:D D Data Input etup ime 100 ns t HD:D D Data Input Hold ime 30 ns t L and D ise ime 300 ns t F L and D Fall ime 300 ns t L Low to D Data utput Valid ime 0.9 µs t DH D Data utput Hold ime 0 ns I Noise uppression ime onstant at L and D inputs 50 ns t BUF Bus Free ime (Prior to ny ransmission) 1200 ns t U:P 0, 1 etup ime 0 ns t HD:P 0, 1 Hold ime 0 ns HIGH-VLGE IE YLE IMING ymbol Parameter yp. Max. Units t High-voltage write cycle time (store instructions) 5 10 ms 16 FN8175.3

17 XDP IMING ymbol Parameter Min. Max. Units t P iper response time after the third (last) power supply is stable 5 10 µs t L iper response time after instruction issued (all load instructions) 5 10 µs YMBL BLE VEFM INPU UPU Must be steady May change from Low to High May change from High to Low Don t are: hanges llowed N/ ill be steady ill change from Low to High ill change from High to Low hanging: tate Not nown enter Line is High Impedance. 17 FN8175.3

18 IMING DIGM tart and top iming () t t F (P) L t U: t HD: t U: t t F D Input iming t Y t HIGH L t L D t U:D t HD:D t BUF utput iming L D t t DH 18 FN8175.3

19 XDP iming (for ll Load Instructions) (P) L D LB t L Vx rite Protect and Device ddress Pins iming () (P) L D... (ny Instruction) t U:P t HD:P P 0, 1 19 FN8175.3

20 PPLIIN INFMIN Basic onfigurations of Electronic Potentiometers V +V I hree terminal Potentiometer; Variable voltage divider wo terminal Variable esistor; Variable current pplication ircuits Noninverting mplifier Voltage egulator V + V V IN 317 V (EG) 1 2 I adj 1 2 V = (1+ 2 / 1 )V V (EG) = 1.25V (1+ 2 / 1 )+I adj 2 ffset Voltage djustment omparator with Hysterisis V 1 100kΩ + 2 V V + V 10kΩ L072 } 1 } 2 10kΩ 10kΩ V UL = { 1 /( )} V (max) L L = { 1 /( )} V (min) +12V -12V 20 FN8175.3

21 pplication ircuits (continued) ttenuator Filter V V V + V = 2 = 3 = 4 = 10kΩ 1 2 V = G V -1/2 G +1/2 G = / 1 fc = 1/(2π) Inverting mplifier Equivalent L- ircuit V 1 } 2 } + V V V = G V G = - 2 / 1 Z IN 1 3 Z IN = 2 + s 2 ( ) 1 = 2 + s Leq ( ) >> 2 Function Generator + } } B frequency 1, 2, amplitude, B 21 FN8175.3

22 PGING INFMIN 14-LED PLI, P, PGE YPE V.025 (.65) B.169 (4.3).252 (6.4) B.177 (4.5).193 (4.9).200 (5.1).047 (1.20).0075 (.19).0118 (.30).002 (.05).006 (.15) (.50).029 (.75) Detail(20X).010 (.25) Gage Plane eating Plane.031 (.80).041 (1.05) ee Detail NE: LL DIMENIN IN INHE (IN PENHEE IN MILLIMEE) ll Intersil U.. products are manufactured, assembled and tested utilizing I9000 quality systems. Intersil orporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see 22 FN8175.3