DP7111 DEVICE MARKING INFORMATION

Transcription

1 00-Tap Digital Potentiometer () with Buffered Wiper Description The is a single digital potentiometer () designed as an electronic replacement for mechanical potentiometers. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The contains a series resistor array connected between two terminals R H and R L. An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper,. The wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non volatile memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new system values without effecting the stored setting. Wiper l of the is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down. The digital potentiometer can be used as a buffered voltage divider. For applications where the potentiometer is used as a l variable resistor, please refer to the. The buffered wiper of the is not compatible with that application. Features 00 position Linear Taper Potentiometer Non volatile EEPROM Wiper Storage; Buffered Wiper Low Power CMOS Technology Single Supply Operation:. V.0 V Increment Up/Down Serial Interface Resistance Values: 0 k, 0 k and 00 k Available in SOIC, TSSOP and MSOP Packages These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant Applications Automated Product Calibration Remote Control Adjustments Offset, Gain and Zero Control Tamper proof Calibrations Contrast, Brightness and Volume Controls Motor Controls and Feedback Systems Programmable Analog Functions CS V CC INC U/D Pin Name INC U/D R H GND R L CS V CC SOIC TSSOP SOIC (V), MSOP (Z) MSOP PIN CONFIGURATIONS INC V CC U/D CS R H R L GND TSSOP (Y) (Top Views) PIN FUNCTION Increment Control Up/Down Control R L GND R H Potentiometer High Terminal Ground Function Buffered Wiper Terminal Potentiometer Low Terminal Chip Select Supply Voltage ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. NIDEC COPAL ELECTRONICS CORP. August, 00 Rev. Publication Order Number: /D

2 SOIC DEVICE MARKING INFORMATION MSOP TSSOP RLA CATVI YMXXXX AARL YMP ARL YMXXX R = Resistance: AARL = ZI 0 T = 0 k AAPT = ZI 0 T = 0 k AAPX = ZI 00 T = 00 k Y = Production Year (Last Digit) L = Assembly Location M = Production Month = Lead Finish NiPdAu ( 9, A, B, C or O, N, D) A = Product Revision (Fixed as A ) P = Product Revision CATV = Device Code I = Temperature Range (Industrial) Y = Production Year (Last Digit) M = Production Month ( 9, A, B, C or O, N, D) XXXX = Last Four Digits of Assembly Lot Number A = Device Code R = Resistance: = 0 k = 0 k = 00 k L = Assembly Location = Lead Finish NiPdAu Y = Production Year (Last Digit) M = Production Month ( 9, A, B, C or O, N, D) XXX = Last Three Digits of XXX = Assembly Lot Number R H V CC R H U/D INC CS Control and Memory Power On Recall R L GND R L Figure. Functional Diagram Figure. Electronic Potentiometer Implementation

3 Pin Description INC: Increment Control Input The INC input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D input. U/D: Up/Down Control Input The U/D input controls the direction of the wiper movement. When in a high state and CS is low, any high to low transition on INC will cause the wiper to move one increment toward the R H terminal. When in a low state and CS is low, any high to low transition on INC will cause the wiper to move one increment towards the R L terminal. R H : High End Potentiometer Terminal R H is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the R L terminal. Voltage applied to the R H terminal cannot exceed the supply voltage, V CC or go below ground, GND. : Wiper Potentiometer Terminal (Buffered) is the buffered wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC, U/D and CS. R L : Low End Potentiometer Terminal R L is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the R H terminal. Voltage applied to the R L terminal cannot exceed the supply voltage, V CC or go below ground, GND. R L and R H are electrically interchangeable. CS: Chip Select The chip select input is used to activate the control input of the and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper. Device Operation The operates like a digital potentiometer with R H and R L equivalent to the high and low terminals and equivalent to the mechanical potentiometer s wiper. There are 00 available tap positions including the resistor end points, R H and R L. There are 99 resistor elements connected in series between the R H and R L terminals. The wiper terminal is connected to one of the 00 taps and controlled by three inputs, INC,U/D and CS. These inputs control a seven bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs. With CS set LOW the is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement the wiper (depending on the state of the U/D input and seven bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the is powere down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. With INC set low, the may be selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory.

4 Table. OPERATION MODES INC CS U/D Operation High to Low Low High Wiper toward R H High to Low Low Low Wiper toward R L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby R H C H R WI C W C L R L Figure. Potentiometer Equivalent Circuit Table. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Supply Voltage V CC to GND 0. to V Inputs CS to GND 0. to V CC 0. V INC to GND 0. to V CC 0. V U/D to GND 0. to V CC 0. V R H to GND 0. to V CC 0. V R L to GND 0. to V CC 0. V to GND 0. to V CC 0. V Operating Ambient Temperature ffix) 0 to C Junction Temperature 0 C Storage Temperature to 0 C Lead Soldering (0 s max) 00 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table. RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min Typ Max Units V ZAP (Note ) ESD Susceptibility MIL STD, Test Method V I LTH (Notes, ) Latch Up JEDEC Standard 00 ma T DR Data Retention MIL STD, Test Method Years N END Endurance MIL STD, Test Method 00,000,000 Stores. This parameter is tested initially and after a design or process change that affects the parameter.. Latch up protection is provided for stresses up to 00 ma on address and data pins from V to V CC V

5 Table. DC ELECTRICAL CHARACTERISTICS (V CC =. V to V unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units POWER SUPPLY V CC Operating Voltage Range. V I CC Supply Current (Increment) V CC = V, f = MHz, I W = 0 00 A V CC = V, f = 0 khz, I W = 0 00 A I CC Supply Current (Write) Programming, V CC = V 000 A V CC = V 00 A I SB (Note ) Supply Current (Standby) CS = V CC 0. V U/D, INC = V CC 0. V or GND 0 A LOGIC INPUTS I IH Input Leakage Current V IN = V CC 0 A I IL Input Leakage Current V IN = 0 V 0 A V IH TTL High Level Input Voltage. V V CC. V V CC V V IL TTL Low Level Input Voltage 0 0. V V IH CMOS High Level Input Voltage. V V CC V V CC x 0. V CC 0. V V IL CMOS Low Level Input Voltage 0. V CC x 0. V POTENTIOMETER CHARACTERISTICS R POT Potentiometer Resistance 0 Device 0 k 0 Device 0 00 Device 00 Pot. Resistance Tolerance 0 % V RH Voltage on R H pin 0 V CC V V RL Voltage on R L pin 0 V CC V Resolution % INL Integral Linearity Error I W A 0. LSB DNL Differential Linearity Error I W A LSB R OUT Buffer Output Resistance 0.0 V CC V WB 0.9 V CC, V CC = V I OUT Buffer Output Current 0.0 V CC V WB 0.9 V CC, V CC = V ma TC RPOT TC of Pot Resistance 00 ppm/ C TC RATIO Ratiometric TC 0 ppm/ C C RH /C RL /C RW Potentiometer Capacitances // pf fc Frequency Response Passive Attenuator, 0 k. MHz V WB(SWING) Output Voltage Range I OUT 00 A, V CC = V 0.0 V CC 0.99 V CC. This parameter is tested initially and after a design or process change that affects the parameter.. Latch up protection is provided for stresses up to 00 ma on address and data pins from V to V CC V. I W = source or sink. These parameters are periodically sampled and are not 00% tested.

6 Table. AC TEST CONDITIONS V CC Range Input Pulse Levels Input Rise and Fall Times Input Reference Levels. V V CC V 0. V CC to 0. V CC 0 ns 0. V CC Table. AC OPERATING CHARACTERISTICS (V CC =. V to.0 V, V H = V CC, V L = 0 V, unless otherwise specified) Symbol Parameter Min Typ (Note ) Max Units t CI CS to INC Setup 00 ns t DI U/D to INC Setup 0 ns t ID U/D to INC Hold 00 ns t IL INC LOW Period 0 ns t IH INC HIGH Period 0 ns t IC INC Inactive to CS Inactive s t CPH CS Deselect Time (NO STORE) 00 ns t CPH CS Deselect Time (STORE) 0 ms t IW INC to V OUT Change s t CYC INC Cycle Time s t R, t F (Note ) INC Input Rise and Fall Time 00 s t PU (Note ) Power up to Wiper Stable ms t WR Store Cycle 0 ms. Typical values are for T A = C and nominal supply voltage.. This parameter is periodically sampled and not 00% tested. CS INC t CI t IL t CYC t IH t IC (store) t CPH 90% 90% 0% U/D t DI t ID t F t R t IW MI (Note 9) Figure. A.C. Timing 9. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.

7 Applications Information (a) resistive divider (b) variable resistance (c) two port Figure. Potentiometer Configuration Applications V ( ) V / V () R R R R R R V 9 A 0 R A = A = A = / LM0 R = R = R = k R POT = 0 k V O. V V R R A pr POT R B C R ( p)r POT 0.0 F 0.00 F V 0.0 F Figure. Programmable Instrumentation Amplifier Figure. Programmable Sq. Wave Oscillator () OSC CS ICA / HC 0 k 0.0 F V 00 mv / IC 0 k V CORR 99 k ICB 99 k V ICA V REF = V V OUT = V mv V Sensor 99 k 99 k V SENSOR = V 0 mv Figure. Sensor Auto Referencing Circuit

8 V IN (UNREG) SHUTDOWN V F 00 k / V OUT 9 SD FB GND. V R k R 0 R 0 k 0. F Figure 9. Programmable Voltage Regulator. F V O (REG) I S V / pr ( p)r 0 0 M V V 0 k A A V O LT09 Figure 0. Programmable I to V Converter. V OSC 0 k IC HC 0. F V CLO CHI IC 9 V LL R V UL V IC V / V 0 k V O 0 V AI O. V IC V S. V 0 V S. V Figure. Automatic Gain Control R R V S F V C 0.00 F R 0 k / 0.00 F R 0 k C R 00 k V A. V Figure. Programmable Bandpass Filter V O V V R 00 k Serial Bus / V S. V R 00 k R 00 k V R. k I S R 00 k. V A A = A = LMC0A Figure. Programmable Current Source/Sink

9 PACKAGE DIMENSIONS SOIC, 0 mils SYMBOL MIN NOM MAX A.. A b E E c D E.0.0 E.0.00 e. BSC h PIN # IDENTIFICATION L º º TOP VIEW D h A A c e b L SIDE VIEW END VIEW Notes: () All dimensions are in millimeters. Angles in degrees. () Complies with JEDEC MS-0. 9

10 PACKAGE DIMENSIONS TSSOP,.x b SYMBOL MIN NOM MAX A.0 A A b E E c D E E e 0. BSC L.00 REF L º º e TOP VIEW D A A c SIDE VIEW A L END VIEW L Notes: () All dimensions are in millimeters. Angles in degrees. () Complies with JEDEC MO-. 0

11 PACKAGE DIMENSIONS MSOP, x SYMBOL MIN NOM MAX A.0 A A b c E E D E E e 0. BSC L L 0.9 REF L 0. BSC 0º º TOP VIEW D A A DETAIL A A e b c SIDE VIEW END VIEW L Notes: () All dimensions are in millimeters. Angles in degrees. () Complies with JEDEC MO-. DETAIL A L L

12 Example of Ordering Information (Note ) Prefix Device # Suffix V I 0 G T Company ID (Optional) Product Number Package V: SOIC Y: TSSOP Z: MSOP Temperature Range I = Industrial ( 0 C to C) Resistance 0: 0 k 0: 0 k 00: 00 k Lead Finish G: NiPdAu Blank: Matte-Tin Tape & Reel T: Tape & Reel :,000 Units / Reel Table. ORDERING INFORMATION Orderable Part Number Resistance (k ) Package Pins Lead Finish VI 0 GT 0 SOIC NiPdAu VI 0 GT 0 VI 00 GT 00 YI 0 GT 0 TSSOP NiPdAu YI 0 GT 0 YI 00 GT 00 ZI 0 T 0 MSOP Matte-Tin ZI 0 T 0 ZI 00 T All packages are RoHS compliant.. Standard lead finish is NiPdAu, except MSOP package is Matte-Tin..The device used in the above example is a GT (SOIC, Industrial Temperature, 0 k, NiPdAu, Tape & Reel,,000/Reel). NIDEC COPAL reserves the right to make changes without further notice to any products herein. NIDEC COPAL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NIDEC COPAL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in NIDEC COPAL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. NIDEC COPAL does not convey any license under its patent rights nor the rights of others. NIDEC COPAL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NIDEC COPAL product could create a situation where personal injury or death may occur. Should Buyer purchase or use NIDEC COPAL products for any such unintended or unauthorized application, Buyer shall indemnify and hold NIDEC COPAL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NIDEC COPAL was negligent regarding the design or manufacture of the part. /D