NV34C04. EEPROM Serial 4-Kb SPD Automotive Grade 1 for DDR4 DIMM

Transcription

1 V3404 EEPM erial 4-b PD utomotive Grade 1 for DD4 DIMM Description he V3404 is a EEPM erial 4 b, which implements the JEDE J42.4 (EE1004 v) erial Presence Detect (PD) specification for DD4 DIMMs and supports the tandard (100 khz), Fast (400 khz) and Fast Plus (1 MHz) I 2 protocols. ne of the two available 2 b EEPM banks (referred to as PD pages in the EE1004 v specification) is activated for access at power up. fter power up, banks can be switched via software command. Each of the four 1 b EEPM blocks can be Write Protected by software command. Features JEDE J42.4 (EE1004 v) erial Presence Detect (PD) ompliant utomotive Grade 1 emperature ange: 40 to +125 upply ange: 1.7 V 3.6 V I 2 / MBus Interface chmitt riggers and oise uppression Filters on L and D Inputs 16 Byte Page Write Buffer Hardware Write Protection for Entire Memory Low Power M echnology 2 x 3 x 0.5 mm UDF Package hese Devices are Pb Free and are oh ompliant 1 UDF8 MU3 UFFIX E 517Z 1 2 V PI FIGUI 0 1 (op View) UDF (MU3, MUW3) V WP L D For the location of Pin 1, please consult the corresponding package drawing. MIG DIGM XXX ZZ YM 1 UDF8 MUW3 UFFIX E 517DH UDF8 L 2, 1, 0 V V3404 D XXX = pecific Device ode = ssembly Location ode ZZ = ssembly Lot umber (Last wo Digits) Y = Production Year (Last Digit) M = Production Month (1 9,,, D) = Pb Free Package WP V Figure 1. Functional ymbol Pin ame 0, 1, 2 D L WP V V DP PI FUI Function Device ddress Input erial Data Input/utput erial lock Input Write Protect Input Power upply Ground Backside Exposed DP at V DEIG IFMI ee detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. emiconductor omponents Industries, LL, 2016 eptember, 2018 ev. 0 1 Publication rder umber: V3404/D

2 V3404 able 1. BLUE MXIMUM IG Parameter ating Units perating emperature 45 to +130 torage emperature 65 to +150 Voltage on any pin (except 0 ) with respect to Ground (ote 1) 0.5 to +6.5 V Voltage on pin 0 with respect to Ground 0.5 to V tresses exceeding those listed in the Maximum atings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V V. he 0 pin can be raised to a HV level for WP command execution. L and D inputs can be raised to the maximum limit, irrespective of V. able 2. ELIBILIY HEII ymbol Parameter Min Units ED (ote 2) Endurance 1,000,000 Write ycles D Data etention 100 Years 2. Page Mode, V = 2.5 V, 25 able 3. HEML HEII (ote 3) Parameter est onditions/omments Max Unit hermal esistance J Junction to mbient (till ir) 92 /W 3. Power Dissipation is defined as P J = ( J )/ J, where J is the junction temperature and is the ambient temperature. he thermal resistance value refers to the case of a package being used on a standard 2 layer PB. able 4. D.. PEIG HEII (Vcc = 1.7 V to 3.6 V, = 40 to +125, unless otherwise specified) ymbol Parameter est onditions Min Max Units I ead urrent ead, f L = 400 khz or 1 MHz 1 m I W Write urrent Write, during t W (ote 4) 1 m I B tandby urrent ll I/ Pins at GD or Vcc Vcc < 2.2 V 1 Vcc 2.2 V 2 I L I/ Pin Leakage Pin at GD or V 2 V IL Input Low Voltage *Vcc V V IH Input High Voltage 0.7*Vcc V V V L1 utput Low Voltage V 2.2 V, I L = 20 m 0.4 V V L2 utput Low Voltage V < 2.2 V, I L = 6.0 m 0.2 V V P+ Power n eset hreshold (ote 4) 1.3 V V P Power ff eset hreshold (ote 4) 0.8 V 4. ested initially and after a design or process change that affects this parameter Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 2

3 V3404 able 5... HEII (ote 6) V = 1.7 V to 3.6 V, = 40 to +125, unless otherwise specified. ymbol Parameter tandard V = 1.7 V 3.6 V Fast V = 1.7 V 3.6 V Fast Plus V = 2.2 V 3.6 V Min Max Min Max Min Max F L (ote 5) lock Frequency ,000 khz t HD: ondition Hold ime s t LW Low Period of L lock s t HIGH High Period of L lock s t U: ondition etup ime s t HD:DI Data In Hold ime s t U:D Data In etup ime ns t (ote 7) D and L ise ime 1, ns t F (ote 7) D and L Fall ime ns t U: P ondition etup ime s t BUF Bus Free ime Between P and Units s t HD:D Data ut Hold ime ns i (ote 7) oise Pulse Filtered at L and D Inputs ns t U:WP WP etup ime s t HD:WP WP Hold ime s t W Write ycle ime ms t II (otes 7, 8) Power-up to eady Mode ms t PFF (ote 9) Warm power cycle off time ms t IMEU (ote 10) Detect clock low timeout ms 5. he minimum clock frequency of 10 khz is an MBus recommendation; the minimum operating clock frequency is limited only by the MBus time out. he device also meets the Fast and tandard I 2 specifications, except that i and t DH are shorter, as required by the 1 MHz Fast Plus protocol. 6. est conditions according to.. est onditions table. 7. ested initially and after a design or process change that affects this parameter. 8. t II is the delay between the Power n eset threshold (V P+ ) and the device is ready to accept commands. 9. Power ff delay to ensure a proper eset when the V drops below V P 10. timeout condition can only be ensured if L is driven low for t IMEU(Max) or longer; then, V3404 is reset and ready to receive a new condition. V3404 does not reset if L is driven low for less than t IMEU(Min). he interface will reset itself and will release the D line if the L line stays low beyond the t IMEU limit. he time out count takes place when L is low in the time interval between and P. able 6... E DII Input Levels Input ise and Fall imes Input eference Levels utput eference Levels utput Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.3 x V, 0.7 x V urrent ource: I L = 6 m; L = 100 pf able 7. PI PIE ( = 25, V = 3.6 V, f = 1 MHz) ymbol Parameter est onditions/omments Min Max Unit I D, Pin apacitance V I = 0 8 pf Input apacitance (other pins) V I = 0 6 pf 3

4 V3404 able 8. IPU IMPEDE ymbol Parameter est onditions Min Max Unit Z IL Input Impedance for 0, 1, 2, WP Pins V I < 0.3 * Vcc 30 k Z IH Input Impedance for 0, 1, 2, WP Pins V I > 0.7 * Vcc 800 k Pin Description L: he erial lock input pin accepts the erial lock generated by the Master (Host). D: he erial Data I/ pin receives input data and transmits data stored in the memory. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 0, 1 and 2: he ddress pins accept the device address. hese pins have on chip pull down resistors. WP: he Write Protect input pin inhibits all write operations, when pulled HIGH. his pin has an on chip pull down resistor. he Write Protect pin should be tied directly either to Vcc or GD. Power n eset (P) he V3404 incorporates Power n eset (P) circuitry which protects the device against powering up to an undetermined logic state. s V exceeds the P trigger level, the device will power up into standby mode. he device will power down into eset mode when V drops below the P trigger level. his bi directional P behavior protects the V3404 against brown out failure following a temporary loss of power. he P trigger level is set below the minimum operating V level. Device Interface he V3404 supports the Inter Integrated ircuit (I 2 ) and the ystem Management Bus (MBus) data transmission protocols. hese protocols describe serial communication between transmitters and receivers sharing a 2 wire data bus. Data flow is controlled by a Master device, which generates the serial clock and the and P conditions. he V3404 acts as a lave device. Master and lave alternate as transmitter and receiver. Up to 8 V3404 devices may be present on the bus simultaneously, and can be individually addressed by matching the logic state of the address inputs 0, 1, and 2. I 2 /MBus Protocol he I 2 /MBus uses two wires, one for clock (L) and one for data (D). he two wires are connected to the V supply via pull up resistors. Master and lave devices connect to the bus via their respective L and D pins. he transmitting device pulls down the D line to transmit a 0 and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, the D line must remain stable while the L line is HIGH. n D transition while L is HIGH will be interpreted as a or P condition (Figure 2). he condition precedes all commands. It consists of a HIGH to LW transition on D while L is HIGH. he acts as a wake up call to all laves. bsent a, a lave will not respond to commands. P he P condition completes all commands. It consists of a LW to HIGH transition on D while L is HIGH. he P tells the lave that no more data will be written to or read from the lave. Device ddressing he Master initiates data transfer by creating a condition on the bus. he Master then broadcasts an 8 bit serial lave address. he first 4 bits of the lave address (the preamble) determine whether the command is a read/write command (1010b) or a utility command (0110b), as described in able 9. he next 3 bits, 2, 1 and 0, select one of 8 possible lave devices. he last bit, /W, specifies whether a ead (1) or Write (0) operation is being performed. cknowledge matching lave address is acknowledged () by the lave by pulling down the D line during the 9 th clock cycle (Figure 3). fter that, the lave will acknowledge all data bytes sent to the bus by the Master. When the lave is the transmitter, the Master will in turn acknowledge data bytes in the 9 th clock cycle. he lave will stop transmitting after the Master does not respond with acknowledge (o) and then issues a P. Bus timing is illustrated in Figure 4. D L BI Figure 2. tart/top iming P BI 4

5 V3404 L FM ME D UPU FM MIE D UPU FM EEIVE Figure 3. cknowledge iming WLEDGE t F t LW t HIGH t L 70% 70% 70% 30% 30% 70% D I t U: t HD: t HD:D t U:D 70% 30% t U: 70% 30% 30% 70% 70% t BUF t HD:D D U 70% 30% Figure 4. Bus iming able 9. MMD E (otes 11, 12) Function pecific Preamble elect ddress /W_n 0 Pin Function bbr b7 b6 b5 b4 b3 b2 b1 b0 ead EE Memory PD L2 L1 L0 1 0 or 1 Write EE Memory WPD 0 et Write Protection, block 0 WP V HV et Write Protection, block 1 WP V HV et Write Protection, block 2 WP V HV et Write Protection, block 3 WP V HV lear ll Write Protection WP V HV ead Protection tatus, block 0 P , 1 or V HV ead Protection tatus, block 1 P , 1 or V HV ead Protection tatus, block 2 P , 1 or V HV ead Protection tatus, block 3 P , 1 or V HV et PD Page ddress to 0 (elect Lower Bank) et PD Page ddress to 1 (elect Upper Bank) P , 1 or V HV P , 1 or V HV ead PD Page ddress P , 1 or V HV eserved ll ther Encodings 11. Lx stands for Logic tate of ddress pin x. 12.If V HV is not applied on the 0 pin during WP/WP commands, the V3404 will respond with o after the 3rd byte and will not execute the WP/WP instruction. During P/P/P commands the state of pin 0 must be stable for the duration of the sequence. 5

6 V3404 EEPM Bank election Upon power up, the address pointer is initialized to 00h pointing to the first location in the lower 2 b bank (PD page 0). nly one PD page is visible (active) at any given time. he lower PD page is automatically selected at power up. he upper PD page can be activated (and the lower one implicitly de activated) by executing the P1 utility command. he P0 utility command can then be used to re activate the lower PD page without powering down. he identity of the active PD page can be retrieved with the P command. PD page selection related command details are presented in able 11c, able 11d, Figure 12 and Figure 13. Write perations EEPM Byte Write o write data to the EEPM, the Master creates a condition on the bus, and then sends out the appropriate lave address (with the /W bit set to 0 ), followed by a starting data byte address, followed by data. he matching lave will acknowledge the lave address, EEPM byte address and the data byte (Figure 5). he Master then ends the session by creating a P condition on the bus. he P starts the internal Write cycle for the (non volatile) EEPM data (Figure 6). EEPM Page Write Each of the two 2 b banks is organized as 16 pages of 16 bytes each (not to be confused with the PD page, which refers to the entire 2 b bank). ne of the 16 memory pages is selected by the 4 most significant bits of the byte address, while the 4 least significant bits point to the byte position within the page. Up to 16 bytes can be written in one Write cycle (Figure 7). During data load, the internal byte position pointer is automatically incremented after each data byte is loaded. If the Master transmits more than 16 data bytes, then earlier data will be replaced by later data in a wrap around fashion within the 16 byte wide data buffer. he internal Write cycle then starts following the P. cknowledge Polling cknowledge polling can be used to determine if the V3404 is busy writing to EEPM, or is ready to accept commands. Polling is executed by interrogating the device with a elective ead command (see ED PEI). he V3404 will not acknowledge the lave address as long as internal EEPM Write is in progress. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the V3404. he state of the WP pin is strobed on the last falling edge of L immediately preceding the first data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the V3404 will not acknowledge the data byte and the Write request will be rejected. Delivery tate he V3404 is shipped unprotected, i.e. none of the oftware Write Protection (WP) flags is set. he entire memory is erased, i.e. all bytes are 0xFF. ead perations Immediate ead V3404 presented with a lave address containing a 1 in the /W position will acknowledge the lave address and will then start transmitting EEPM data from the current address pointer location. he Master stops this transmission by responding with o, followed by a P (Figure 9). elective ead he ead operation can be started from a specific address, by preceding the Immediate ead sequence with a data less Write sequence. he Master sends out a, lave address and byte address, but rather than following up with data (as in a Write operation), the Master then issues another and continuous with an Immediate ead sequence (Figure 10). equential EEPM ead EEPM data can be read out indefinitely, as long as the Master responds with (Figure 11). he internal address pointer is automatically incremented after every data byte sent to the bus. If the end of the active 2 b bank is reached during continuous ead, then the address count wraps around to the beginning of the active 2 b bank, etc. equential ead works with either Immediate ead or elective ead, the only difference being that in the latter case the starting address is intentionally updated. BU IVIY: ME LVE DDE BYE DDE D P P D LIE LVE Figure 5. EEPM Byte Write 6

7 V3404 L D 8th Bit Byte n t W P DII DII DDE Figure 6. EEPM Write ycle iming BU IVIY: ME LVE DDE BYE DDE (n) D n D n+1 D n+p P D LIE P LVE E: In this example n = XXXX 0000(B); X = 1 or 0 Figure 7. EEPM Page Write DDE BYE D BYE L D a 7 a 0 d 7 d 0 t U:WP WP t HD:WP Figure 8. WP iming BU IVIY: ME LVE DDE P D LIE P LVE D Figure 9. EEPM Immediate ead 7

8 V3404 BU IVIY: ME LVE DDE BYE DDE (n) LVE DDE P D LIE P LVE D n Figure 10. EEPM elective ead BU IVIY: ME LVE DDE P D LIE P LVE D n D n+1 D n+2 Figure 11. EEPM equential ead D n+x oftware Write Protection Each 1 b memory block can be individually protected against Write requests. Block identities are: Block 0: byte address 0x00...0x7F (PD page address = 0) Block 1: byte address 0x80...0xFF (PD page address = 0) Block 2: byte address 0x00...0x7F (PD page address = 1) Block 3: byte address 0x80...0xFF (PD page address = 1) Block oftware Write Protection (WP) flags can be set or cleared in the presence of a very high voltage V HV on address pin 0. he V HV condition must be established on pin 0 before the and maintained just beyond the P. he D.. PEIG DII for WP operations are shown in able 10. WP command details are listed in ables 11a and 11b. WP lave addresses follow the standard I 2 convention, i.e. to read the state of a WP flag, the LB of the lave address must be 1, and to set or clear a flag, it must be 0. For et/lear commands a dummy byte address and dummy data byte must be provided (Figure 12). In contrast to a regular memory ead, a WP ead does not return data. Instead the V3404 will respond with o if the flag is set and with if the flag is not set (Figure 13). able 10. WPn D WP D.. PEI DII ymbol Parameter est onditions Min Max Units V HV 0 verdrive (V HV V ) 4.8 V I HVD 0 High Voltage Detector urrent 1.7 V < V < 3.6 V 0.1 m V HV 0 Very High Voltage 7 10 V 8

9 V3404 able 11a. WP E MMD DEIL (following lave ddress) ommand Block(x) Protection lave ddress Byte lave Data Byte lave WPx(ote 13) ot et (Dummy) (Dummy) Yes et o (Dummy) o (Dummy) o o WP X (Dummy) (Dummy) Yes able 11b. WP QUEY MMD DEIL (following lave ddress) ommand Block(x) Protection lave Data Byte Master () Data Byte Master () Px (ots 13, 14) ot et Dummy (o) Dummy (o) et o Dummy (o) Dummy (o) able 11c. PD PGE ELE MMD DEIL (following lave ddress) ommand PD ctive Page lave ddress Byte lave Data Byte lave Px (otes 15, 16) X (Dummy) (Dummy) /o* o able 11d. PD IVE PGE QUEY MMD DEIL (following lave ddress) ommand P (otes 13, 14, 17) PD ctive Page lave Data Byte Master () Data Byte Master () 0 Dummy (o) Dummy (o) 1 o Dummy (o) Dummy (o) Write ycle Write ycle 13.he Master can terminate the sequence by issuing a P once the V3404 responds with o 14. he Master can terminate the sequence by responding with (o) followed by P after any dummy data byte. 15.etting the PD Page ddress to 0 selects the lower 2 b EEPM bank, setting it to 1 selects the upper 2 b EEPM bank. 16. he lower 2 b EEPM bank (corresponding to PD page address 0 ) is active (visible) immediately following power up. 17.he device will respond with when the lower 2 b EEPM bank is active and with o when the upper 2 b EEPM bank is active. *he V3404MU3VG will respond with o following the dummy Data Byte, while the V3404MUW3VG will respond with BU IVIY: ME LVE DDE Dummy DDE Dummy D P D LIE LVE or or or X = Don t are Figure 12. WP & P iming BU IVIY: ME LVE DDE P D LIE LVE or Dummy D Dummy D X = Don t are Figure 13. P & P iming 9

10 V3404 PGE DIMEI UDF8, 2x3 EXEDED PD E 517Z IUE PI E EFEEE E DEIL 0.10 D ÇÇÇ ÇÇÇ P VIEW 1 IDE VIEW D2 1 4 DEIL B L B E 3 L1 EXPED u EIG PLE L DEIL LEE UI MLD MPD 1 DEIL B LEE UI L 8X 0.68 ÇÇ 3 E: 1. DIMEIIG D LEIG PE ME Y14.5M, LLIG DIMEI: MILLIMEE. 3. DIMEI b PPLIE PLED EMIL D I MEUED BEWEE 0.15 D 0.25MM FM HE EMIL IP. 4. PLIY PPLIE HE EXPED PD WELL HE EMIL. MILLIMEE DIM MI MX EF b D 2.00 B D E 3.00 B E e 0.50 B L L EMMEDED LDEIG FPI* 1.56 E e BM VIEW 8X b 0.10 M 0.05 M B E PIH 8X 0.30 DIMEI: MILLIMEE *For additional information on our Pb Free strategy and soldering details, please download the emiconductor oldering and Mounting echniques eference Manual, LDEM/D. 10

11 V3404 PGE DIMEI UDF8 2x3, 0.5P E 517DH IUE PI E IDI E D ÇÇ ÇÇ P VIEW DEIL B 1 IDE VIEW B E 3 L1 EXPED u EIG PLE L DEIL LEE UI ÉÉ ÇÇ MLD MPD DEIL B LEE UI L ÉÉÉ 1 3 E: 1. DIMEIIG D LEIG PE ME Y14.5M, LLIG DIMEI: MILLIMEE. 3. DIMEI b PPLIE PLED EMIL D I MEUED BEWEE 0.15 D 0.25MM FM HE EMIL IP. 4. PLIY PPLIE HE EXPED PD WELL HE EMIL. 5. F DEVIE P IIG W PI, DEIL B LEE UI I PPLIBLE. MILLIMEE DIM MI MX EF b D 2.00 B D E 3.00 B E e 0.50 B L L DEIL D2 1 4 L EMMEDED LDEIG FPI* 1.56 E2 8X e BM VIEW 8X b 0.10 M B 0.05 M 1 E 3 XXXXX WLYW PIH 8X 0.30 DIMEI: MILLIMEE *For additional information on our Pb Free strategy and soldering details, please download the emiconductor oldering and Mounting echniques eference Manual, LDEM/D. XXXXX = pecific Device ode = ssembly Location WL = Wafer Lot Y = Year W = Work Week = Pb Free Package 11

12 V3404 DEIG IFMI Device rder umber pecific Device Marking Package ype emperature ange Lead Finish hipping V3404MU3VG V2U UDF 8 40 to +125 ipdu ape & eel, 4,000 Units / eel V3404MUW3VG D2W UDF 8 40 to +125 ipdu ape & eel, 3,000 Units / eel 18. ll packages are oh compliant (Lead free, Halogen free) 19. he standard lead finish is ipdu. 20. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and eel Packaging pecifications Brochure, BD8011/D. emiconductor is licensed by Philips orporation to carry the I 2 Bus Protocol. emiconductor and are trademarks of emiconductor omponents Industries, LL dba emiconductor or its subsidiaries in the United tates and/or other countries. emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of emiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. emiconductor reserves the right to make changes without further notice to any products herein. emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by emiconductor. ypical parameters which may be provided in emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. emiconductor does not convey any license under its patent rights nor the rights of others. emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that emiconductor was negligent regarding the design or manufacture of the part. emiconductor is an Equal pportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLII DEIG IFMI LIEUE FULFILLME: Literature Distribution enter for emiconductor P.. Box 5163, Denver, olorado U Phone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: Phone: emiconductor Website: rder Literature: For additional information, please contact your local ales epresentative V3404/D