16-Bit D-Type Flip-Flop with 3-State Outputs. Product Features. Product Description. Logic Block Diagram

Transcription

1 with 3-State Product Feature The PI4CX Family i deigned for low voltage operation, = 8 to I/O Tolerant and Support Live Inertion Balanced Drive, ±24mA Ue patented Noie Reduction Circuitry Typical OLP ( Ground Bounce) < 6 at = 2., T A = 2ºC Typical OH ( OH Underhoot) < 6 at = 2., T A = 2ºC Power-Off high impedance input and output Indutrial operation at 40 C to +8 C Packaging (Pb-free & Green available): 48-pin 240 mil. wide platic TSSOP (A) Logic Block Diagram 1OE 1 Product Decription The PI4CX1634 i particularly uitable for implementing buffer regiter, I/O port, bidirectional bu driver, and working regiter. Thi device can be ued a two 8-bit Flip-Flop or one 16-bit flipflop. On the poitive tranition of the clock (CLK) input, the Q output of the flip-flop take on the logic level et up at the date (D) input. A buffered Enable (OE) input can be ued to place the eight output in either a normal logic tate (high or low logic level) or a high-impedance tate in which the output neither load nor drive the bu line ignificantly. The high-impedance tate and the increaed drive provide the capability to drive bu line without need for interface or pullup component. OE doe not affect internal operation of the flip-flop. Old data can be retained or new data can be entered while the output are in the high impedance tate. To enure the high-impedance tate during power up or power down, OE hould be tied to through a pullup reitor; the minimum value of the reitor i determined by the currentinking capability of the driver. The PI4CX family i I/O Tolerant, allowing it to operate in mixed 8/3.6 ytem. 48 1CLK 4 1D1 >C1 1D 2 1Q1 To Seven Other Channel 2OE CLK 36 2D1 >C1 1D 13 2Q1 To Seven Other Channel 1

2 with 3-State Product Pin Decription Truth Table (1) Pin Name Decription OE Enable (Active LOW) OE CLK D Q CLK Clock Dx Data L H H Qx 3-State L L L Ground Power L H or L X Q 0 Product Pin Configuration H X X Z Note: H = High Signal Level L = Low Signal Level X = Don t Care or Irrelevant Z = High Impedance 1OE CLK 1Q D1 1Q D Q3 44 1D3 1Q D4 42 1Q D 1Q D Q 1Q8 2Q1 2Q2 2Q3 2Q4 2Q 2Q6 2Q 2Q8 2OE D 1D8 2D1 2D2 2D3 2D4 2D 2D6 2D 2D8 2CLK 2

3 with 3-State Maximum Rating (Above which the ueful life may be impaired. For uer guideline, not teted.) Supply oltage Range,... to 4.6 oltage Range, I... - to 4.6 oltage Range, O (3-Stated)... - to 4.6 oltage Range, O (1) (Active)... to + DC Diode Current (I IK ) I <... -0mA DC Diode Current (I OK ) O <... -0mA O >... -0mA DC Source/Sink Current ( / )... ±0mA DC or Current per Supply Pin (I CC or )... ±100mA Storage Temperature Range, T STG... 6 C to10 C Note: Abolute maximum of I O mut be oberved. Note: Stree greater than thoe lited under MAXIMUM RATINGS may caue permanent damage to the device. Thi i a tre rating only and functional operation of the device at thee or any other condition above thoe indicated in the operational ection of thi pecification i not implied. Expoure to abolute maximum rating condition for extended period may affect reliability. Recommended Operating (1) Parameter I O Δ t/ Δv T A Decriptio n Supply voltag e High-level input voltag e Low-level input voltag e C ondition M in. Operating Data Retention Only = 2. to = 2. to voltag e voltag e = 3. to 3.6 current in IOH/ IOL = 2.3 to 2. = 8 tranition rie or fall rate (2) Active State 0 Off State ±24 ±18 ±6 ma 0 10 n/ Operating free-air temperatur e 40 8 C Note: Unued control input mut be held HIGH or LOW to prevent them from floating. 2 A meaured between 8 and 2., = 3.. 3

4 with 3-State Electrical Characteritic over Recommended Operating Free-Air Temperature Range (unle otherwie noted) DC Characteritic (2. < 3.6) Parameter OH OL I I I OZ IOFF I DD ΔI DD Decriptio n HIGH Level oltag e D D M in. T yp. LOW Level oltag e HIGH Level oltage LOW Level oltage 2.0 I O H = 100μA - 2 I O H = 12mA I O H = 18mA I O H = 24mA 2. 2 = 100μA = 12mA 2. 4 = 18mA = 24mA I =, 1 = ±. 0 3-STATE Leakage Power-OFF Quiecent Supply Current Increae in IDD per inpu t 0 O 3.6 I = IH or IL ±10 0 ( I, O) I = to ( I, O) ± = D D -6, Other input at or 0 μa 4

5 with 3-State DC Characteritic (2.3 2.) Parameter OH OL I I I OZ IOFF Decriptio n HIGH Level oltag e D D M in. T yp. LOW Level oltag e HIGH Level oltag e LOW Level oltag e 6 = -100μA - 2 = -6mA = -12mA 8 = -18mA = 100μA = 12mA = 18mA 4 1 =, 1 = ±. 0 3-STATE Leakage Power-OFF 0 O 3.6 I = IH or IL ±10 0 ( I, O) μa I DD Quiecent Supply Current I = or ( I , O) 3.6 ± DC Characteritic (8 2.3) Parameter OH OL I I Decriptio n HIGH Level oltag e LOW Level oltag e HIGH Level oltag e LOW Level oltag e = -100μA D D M in. T yp x - 2 = -6mA 4 2 x = 100μA 2 8 = 6mA 3 1 =, 1 = 8 ±. 0 I OZ IOFF 3-STATE Leakage Power-OFF 0 O 3.6 I = IH or IL ±10 0 ( I, O) μa I DD Quiecent Supply Current I = or 8 ( I, O) ±

6 with 3-State AC Electrical Characteritic (1) Symbol fmax t PLH, tphl tpzh, tpzl tphz, tplz t OSHL, toslh Note: For C L = 0pF add approximatly 300p to AC maximum pecification. 2. Skew i defined a the abolute value of the difference between the actual propagation delay for any two eparate output of the ame device. The pecification applie to any output witching in the ame direction, either HIGH or LOW (t OSHL ) or LOW to HIGH (t OSLH ). AC Setup Requirement Parameter T A = -40 C to +8 C, CL = 30pF, RL = 00Ω = 3.3 ± 3 = 2. ± 2 = 8 M in. M ax. M in. M ax. M in. Maximum Clock Frequenc y MHz Prop Delay, CLK to Q Enable Tim e Diable Tim e O utput to Skew( 2) T A = -40ºC to +8ºC, CL = 30pF, RL= 00Ω n Symbol t SU t H t W Parameter = 3.3 ± 3 = 2. ± 2 = 8 M in. T yp. M in. T yp. M in. Typ. Setup Tim e 2. Hold Tim e Pule Widt h 3. 0 n Dynamic Switching Characteritic Symbol OLP OLP OLP Quiet Quiet Quiet Parameter Dynamic Peak OL Dynamic alley OL Dynamic alley OH C L = 0pF = = C L = 0pF = = C L = 0pF = = T A = +2 C Typical Capacitance Symbol Parameter T A = +2 C Typical C IN C OUT C PD Capacitanc e = 8, 2. or 3.3, I = or 6 Capacitanc e I = or, = 8, 2. or 3.3 Power Diipatio n Capacitance I = or, F = 10 MHz = 8, 2. or 3.3 pf 6

7 with 3-State Tet Circuit and Switching Waveform Parameter Meaurement Information ( = 8-3.6) Switch Poition Tet S1 2 x t PD Open From Under Tet 30pF CL (See Note A) R1 00Ω RL 00Ω Open tp LZ/tPZL tp HZ/tPZH Pule Width 2 x Setup, Hold, and Releae Timing Data Timing tsu th /2 /2 Note: A. C L include probe and jig capacitance. B. Waveform 1 i for an output with internal condition uch that the output i LOW except when diabled by the output control. Waveform 2 i for an output with internal condition uch that the output i HIGH except when diabled by the output control. All input pule are upplied by generator having the follow ing characteritic: P RR 10 MHz, Z O = 0Ω, t R 2n, t F 2n, meaured from 10% to 90%, unle otherwie pecified. The output are meaured one at a time with one tranition per meaurement. Low-High-Low Pule High-Low-High Pule Propagaton Delay Oppoite Phae Tranition tplh tphl Enable Diable Timing Control (Active LOW) Waveform 1 S1 at 2x (ee Note B) tpzl tpzh tw /2 tplz tphz /2 /2 /2 tphl /2 OL tplh /2 +1 /2 OL Waveform 2 S1 at (ee Note B) /2-1 OH

8 with 3-State Packaging Mechanical: 48-pin TSSOP (A) Max SEATING PLANE X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS.019 BSC BSC 8.1 Ordering Information Ordering Code Package Code Package Type PI4CX1634A A 48-pin TSSOP PI4CX1634AE A Pb-free & Green, 48-pin TSSOP Note: Thermal characteritic can be found on the company web ite at E = Pb-free & Green Adding an X uffix = Tape/Reel Pericom Semiconductor Corporation