THE DIGITAL LOGIC LEVEL
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1 3 THE DIGITL LOGIC LEVEL 1
2 +V CC +V CC +V CC V out Collector V 1 V out V out V in V 2 V 1 V 2 ase Emitter (a) (b) (c) Figure 3-1. (a) transistor inverter. (b) NND gate. (c) NOR gate.
3 NOT X NND X NOR X ND X OR X X X X X X (a) (b) (c) (d) (e) Figure 3-2. The symbols and functional behavior for the five basic gates.
4 C C 1 4 C 5 C C M 2 8 M C C 3 C 7 C (a) (b) Figure 3-3. (a) The truth table for the majority function of three variables. (b) circuit for (a).
5 (a) + + (b) (c) Figure 3-4. Construction of (a) NOT, (b) ND, and (c) OR gates using only NND gates or only NOR gates.
6 + C ( + C) C C C + C C C + C (a) C + C ( + C) (b) Figure 3-5. Two equivalent functions. (a) + C. (b) ( + C).
7 Name ND form OR form Identity law Null law Idempotent law Inverse law Commutative law ssociative law Distributive law bsorption law De Morgan's law 1 = 0 = 0 = = 0 = ()C = (C) + C = ( + )( + C) ( + ) = = = 1 + = 1 + = + = 1 + = + ( + ) + C = + ( + C) ( + C) = + C + = + = Figure 3-6. Some identities of oolean algebra.
8 = + + = (a) (b) = + + = (c) (d) Figure 3-7. lternative symbols for some gates: (a) NND. (b) NOR. (c) ND. (d) OR.
9 XOR (a) (b) (c) (d) Figure 3-8. (a) The truth table for the XOR function. (b)-(d) Three circuits for computing it.
10 F F F 0 V 0 V 0 V V 5 V 0 V V 0 V 0 V V 5 V 5 V (a) (b) (c) Figure 3-9. (a) Electrical characteristics of a device. (b) Positive logic. (c) Negative logic.
11 V CC Pin 8 Notch GND Figure n SSI chip containing four gates.
12 D 0 D 1 D 2 D 3 D 4 F D 5 D 6 D 7 C C C Figure n eight-input multiplexer circuit.
13 V CC D 0 D 0 D 1 D 1 D 2 D 2 D 3 D 4 F D 3 D 4 F D 5 D 5 D 6 D 6 D 7 D 7 C (a) C (b) Figure (a) n MSI multiplexer.. (b) The same multiplexer wired to compute the majority function.
14 D 0 D 1 D 2 D 3 C C D 4 D 5 C D 6 D 7 Figure to-8 decoder circuit.
15 EXCLUSIVE OR gate = Figure simple 4-bit comparator.
16 If this fuse is blown, is not an input to ND gate = 24 input signals L 24 input lines If this fuse is blown, ND gate 1 is not an input to OR gate input lines outputs Figure input, 6-output programmable logic array. The little squares represent fuses that can be burned out to determine the function to be computed. The fuses are arranged in two matrices: the upper one for the ND gates and the lower one for the OR gates.
17 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 C S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 Figure bit left/right shifter.
18 Sum Carry Exclusive OR gate Sum Carry Figure (a) Truth table for 1-bit addition. (b) circuit for a half adder.
19 Carry in Carry in Sum Carry out Sum Carry out (a) (b) Figure (a) Truth table for full adder. (b) Circuit for a full adder.
20 Logical unit Carry in INV EN EN + Sum Output Enable lines F 0 Full adder F 1 Decoder Carry out Figure bit LU.
21 F1 F bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU INC O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 Carry in Carry out Figure Eight 1-bit LU slices connected to make an 8- bit LU. The enables and invert signals are not shown for simplicity.
22 C1 Delay C2 (a) (b) C (c) Figure (a) clock. (b) The timing diagram for the clock. (c) Generation of an asymmetric clock.
23 S S NOR R R 1 0 (a) (b) (c) Figure (a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR.
24 S Clock R Figure clocked SR latch.
25 D Figure clocked D latch.
26 d a b d b ND c c c (a) b a Time (b) Figure (a) pulse generator. (b) Timing at four points in the circuit.
27 D Figure D flip-flop.
28 D D D D CK CK CK CK (a) (b) (c) (d) Figure D latches and flip-flops.
29 V CC CLR D CLR D CK PR CK PR (a) GND V CC D D D D CK CLR CK CLR CK CLR CK CLR CLR CK CLR CK CLR CK CLR CK D D D D GND (b) Figure (a) Dual D flip-flop. (b) Octal flip-flop.
30 Data in I 2 I 1 I 0 Write gate D CK D CK D CK Word 0 Word 0 select line D CK D CK D CK Word Word 1 select line D CK D CK D CK Word 2 Word 2 select line D CK D CK D CK Word 3 CS RD CS RD O 1 O 2 O 3 OE Output enable = CS RD OE Figure Logic diagram for a 4 3 memory. Each row is one of the four 3-bit words. read or write operation always reads or writes a complete word.
31 Data in Data out Control (a) (b) (c) (d) Figure (a) noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) n inverting buffer.
32 K 8 Memory chip (4 Mbit) D0 D1 D2 D3 D4 D5 D6 D RS CS 4096K 1 Memory chip (4 Mbit) D CS WE OE CS WE OE (a) (b) Figure Two ways of organizing a 4-Mbit memory chip.
33 yte Type Category Erasure alterable Volatile Typical use SRM Read/write Electrical Yes Yes Level 2 cache DRM Read/write Electrical Yes Yes Main memory ROM Read-only Not possible No No Large volume appliances PROM Read-only Not possible No No Small volume equipment EPROM Read-mostly UV light No No Device prototyping EEPROM Read-mostly Electrical Yes No Device prototyping Flash Read/write Electrical No No Film for digital camera Figure comparison of various memory types.
34 ddressing us arbitration Data us control Typical Micro- Processor Coprocessor Status Interrupts Miscellaneous Symbol for clock signal Φ +5v Power is 5volts Symbol for electrical ground Figure The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins are used. For a specific CPU, a number will be given to tell how many.
35 CPU chip Registers uses us controller Memory bus Memory LU I/O bus On-chip bus Disk Modem Printer Figure computer system with multiple buses.
36 Master Slave Example CPU Memory Fetching instructions and data CPU I/O device Initiating data transfer CPU Coprocessor CPU handing instruction off to coprocessor I/O Memory DM (Direct Memory ccess) Coprocessor CPU Coprocessor fetching operands from CPU Figure Examples of bus masters and slaves.
37 20-it address 20-it address it address Control Control 4-it address Control 4-it address Control 8-it address (a) (b) Control (c) Control Figure Growth of an address bus over time.
38 Read cycle with 1 wait state T 1 T 2 T 3 Φ T D DDRESS Memory address to be read T DS DT Data MRE T ML T M T MH RD T RH T RL T DH WIT Time (a) Symbol T D T ML T M T RL T DS T MH T RH T DH Parameter Min Max Unit ddress output delay ddress stable prior to MRE MRE delay from falling edge of Φ in T 1 RD delay from falling edge of Φ in T 1 Data setup time prior to falling edge of Φ MRE delay from falling edge of Φ in T 3 RD delay from falling edge of Φ in T 3 Data hold time from negation of RD nsec nsec nsec nsec nsec nsec nsec nsec (b) Figure (a) Read timing on a synchronous bus. Specification of some critical times. (b)
39 DDRESS Memory address to be read MRE RD MSYN DT Data SSYN Figure Operation of an asynchronous bus.
40 us request rbiter us grant us grant may or may not be propagated along the chain rbiter us request level 1 us request level 2 us grant level 2 us grant level I/O devices (a) (b) Figure (a) centralized one-level bus arbiter using daisy chaining. (b) The same arbiter, but with two levels.
41 +5v rbitration line In Out In Out In Out In Out In Out us request usy Figure Decentralized bus arbitration.
42 T 1 T 2 T 3 T 4 T 5 T 6 T 7 Φ DDRESS Memory address to be read DT Count Data Data Data Data MRE RD WIT LOCK Figure block transfer.
43 CPU INT INT RD WR 0 CS D0-D Interrupt controller IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Clock Keyboard Disk Printer +5 v Figure Use of the 8259 interrupt controller.
44 14.0 cm Pentium II SEC cartridge 6.3 cm Pentium II processor 512 K unified L2 cache 16 K level 1 instruction cache To local bus 16 K level 1 data cache Contact 1.6 cm Figure The Pentium II SEC package.
45 us arbitration Request Error PRI# LOCK# Misc# # DS# RE# Parity# Misc# RESET# Interrupts VID Compatibity Snoop Misc# 3 Pentium II CPU 11 Diagnostics Response Data RS# TRDY# Parity# D# DRDY# DSY# Parity# Initialization Power management Miscellaneous Φ Power Figure Logical pinout of the Pentium II. Names in upper case are the official Intel names for individual signals. Names in mixed case are groups of related signals or signal descriptions.
46 us cycle T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12 Φ Transaction Req Error Snoop Resp Data Req Error Snoop Resp Data Req Error Snoop Resp Data Req Error Snoop Resp Data Req Error Snoop Resp Data Req Error Snoop Resp Data Req Error Snoop Resp Data Figure Pipelining requests on the Pentium II s memory bus.
47 Pin 1 Index Figure The UltraSPRC II CPU chip.
48 Level 2 cache tags Level 2 cache data Tag address Tag valid Tag data us arbitration Memory address ddress parity ddress valid Tag parity UltraSPRC II CPU 20 Data address Data address valid Wait Reply 4 Level 1 caches 128 Data 16 Parity 5 Control UP interface to main memory UD II memory buffer Memory data Memory ECC Figure The main features of the core of an UltraSPRC II system.
49 Programmable I/O lines PCI bus 16 MicroJava 701 CPU Level 1 caches I D Flash PROM Memory bus Main memory Figure microjava 701 system.
50 Motherboard PC bus connector PC bus Contact Plug-in board Chips CPU and other chips New connector for PC/T Edge connector Figure The PC/T bus has two components, the original PC part and the new part.
51 Cache bus Local bus Memory bus Level 2 cache CPU PCI bridge Main memory PCI bus SCSI US IS bridge IDE disk Graphics adaptor vailable PCI slot Mouse IS bus Keyboard Monitor Modem Sound card Printer vailable IS slot Figure rchitecture of a typical Pentium II system. The thicker buses have more bandwidth than the thinner ones.
52 PCI arbiter RE# GNT# PCI device RE# GNT# PCI device RE# GNT# PCI device RE# GNT# PCI device Figure The PCI bus uses a centralized bus arbiter.
53 Signal Lines Master Slave Description CLK 1 Clock (33 MHz or 66 MHz) D 32 Multiplexed address and data lines PR 1 ddress or data parity bit C/E 4 us command/bit map for bytes enabled FRME# 1 Indicates that D and C/E are asserted IRDY# 1 Read: master will accept; write: data present IDSEL 1 Select configuration space instead of memory DEVSEL# 1 Slave has decoded its address and is listening TRDY# 1 Read: data present; write: slave will accept STOP# 1 Slave wants to stop transaction immediately PERR# 1 Data parity error detected by receiver SERR# 1 ddress parity error or system error detected RE# 1 us arbitration: request for bus ownership GNT# 1 us arbitration: grant of bus ownership RST# 1 Reset the system and all devices (a) Sign Lines Master Slave Description RE64# 1 Request to run a 64-bit transaction CK64# 1 Permission is granted for a 64-bit transaction D 32 dditional 32 bits of address or data PR64 1 Parity for the extra 32 address/data bits C/E# 4 dditional 4 bits for byte enables LOCK 1 Lock the bus to allow multiple transactions SO# 1 Hit on a remote cache (for a multiprocessor) SDONE 1 Snooping done (for a multiprocessor) INTx 4 Request an interrupt JTG 5 IEEE JTG test signals M66EN 1 Wired to power or ground (66 MHz or 33 MHz) (b) Figure (a) Mandatory PCI bus signals. (b) Optional PCI bus signals.
54 us cycle Read Idle White T 1 T 2 T 3 T 4 T 5 T 6 T 7 Φ D ddress Turnaround Data ddress Data C/E# Read cmd Enable Write cmd Enable FRME# IRDY# DEVSEL# TRDY# Figure Examples of 32-bit PCI bus transactions. The first three cycles are used for a read operation, then an idle cycle, and then three cycles for a write operation.
55 Time (msec) 0 Idle Frame 0 Frame 1 Frame 2 Frame 3 Packets from root Packets from root SOF SOF IN DT CK SOF SOF OUT DT CK Data packet from device SYN PID PYLOD CRC From device SYN PID PYLOD CRC Figure The US root hub sends out frames every 1.00 msec.
56 CS 0-1 WR RD RESET D0-D Parallel I/O chip Port Port Port C Figure n 8255 PIO chip.
57 EPROM at address 0 RM at address 8000H PIO at FFFCH,, 0 4K 8K 12K 16K 20K 24K 28K 32K 36K 40K 44K 48K 52K 56K 60K 64K Figure Location of the EPROM, RM, and PIO in our 64K address space.
58 0 ddress bus 15 CS CS CS 2K 8 EPROM 2K 8 RM PI0 (a) 0 ddress bus 15 CS CS CS 2K 8 EPROM 2K 8 RM PI0 (b) Figure (a) Full address decoding. (b) Partial address decoding.
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