Chapter 2. Digital Logic Basics
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1 Chapter 2 Digital Logic Basics 1
2 2 Chapter Implementation using NND gates: We can write the XOR logical expression B + B using double negation as B+ B = B+B = B B From this logical expression, we can derive the following NND gate implementation: B Figure 2.1: 2-input XOR gate using only NND gates. Implementation using NOR gates: We can write the XOR logical expression as B+ B = B+B = + B + + B From this logical expression, we can derive the following NOR gate implementation: B Figure 2.2: 2-input XOR gate using only NOR gates.
3 Chapter Implementation using NND gates: We can write the exclusive-nor logical expression B+ B using double negation as B+B = B + B = B B From this logical expression, we can derive the following NND gate implementation: B
4 4 Chapter 2 Implementation using NOR gates: We can write the exclusive-nor logical expression as B+B = B+B = + B + + B From this logical expression, we can derive the following NOR gate implementation: B lternative Implementations: lternatively, we can derive the following NND implementation by modifying the logic circuit in Figure 2.1 by adding an output inverter: B
5 Chapter 2 5 Similarly, we derive the following NOR implementation by modifying the logic circuit in Figure 2.2 by deleting the output inverter: B
6 6 Chapter NOT gate can be implemented by holding one input at 1 as shown below: 1
7 Chapter By keeping one input at, we can turn an XOR gate into a buffer that passes input to output as shown below: It is clear from this and the last exercise that by controlling one input (call it control input), we can turn an XOR gate into either an inverter or a buffer. If the control input is 1, the XOR gate acts as an inverter; if the control input is, it acts as a buffer.
8 8 Chapter We can write the ND logical expression ( B) using double negation as B = B = + B From this logical expression, we can derive the following implementation: B
9 Chapter We can write the OR logical expression ( + B) using double negation as + B = + B = B From this logical expression, we can derive the following implementation: B
10 1 Chapter The two transistors are in series. V out is low only when both transistors are turned on. This happens only when both V in1 and V in2 are high as shown below: V in1 V in2 V out low low high low high high high low high high high low s in the text, when we interpret low as and high as 1, it implements the NND function.
11 Chapter In this example, the two transistors are in parallel. V out is low when any of the two transistors are turned on. This happens when either V in1 or V in2 (or both) is high as shown below: V in1 V in2 V out low low high low high low high low low high high low s in the text, when we interpret low as and high as 1, it implements the NOR function.
12 12 Chapter We assume that input has 5% weight. The truth table is shown below: B C F We use the Karnaugh map to derive the simplified logical expression. BC BC From this K-map, we get the following logical expression: +BC The following logic circuit implements this function: B C
13 Chapter We assume that input has the veto power. The truth table is shown below: B C F The sum-of-products expression for F can be simplified by replicating the term ( B C) as shown below: F = B C + BC + BC = B C + BC + BC + BC = C + B = (B +C) You can also use the Karnaugh map method to derive the same logical expression. The following logic circuit implements this function: B C
14 14 Chapter (a) x x = x Let us start with x and show that it is equivalent to x x. x = x 1 (Identity) = x (x + x) (Complement) = (x x) + (x x) (Distribution) = (x x) + (Complement) = x x (Identity) (b) x + x = x Let us start with x and show that it is equivalent to x + x (very similar to the last exercise). x = x + (Identity) = x +(x x) (Complement) = (x + x) (x + x) (Distribution) = (x + x) 1 (Complement) = x + x (Identity) (c) x = s in the previous examples, we start with the right hand side () and show that it is equivalent to x. = x x (Complement) (d) x +1 = 1 This is the dual of the last exercise. = x (x + ) (Identity) = (x x) + (x ) (Distribution) = + (x ) (Complement) = x (Identity) 1 = x + x (Complement) = x + (x 1) (Identity) = (x + x) (x + 1) (Distribution) = 1 (x + 1) (Complement) = x + 1 (Identity)
15 Chapter We have to show (x y) (x + y) = and (x y) + (x + y) = 1. (x y) (x +y) = xyx + xyy = + = (x y) + (x +y) = xy + x(y + y) + y(x + x) = xy + x y + x y + y x + y x = (x y + x y) + (x y + y x) = (x y + x y) + (x y + y x) = y + y = 1
16 16 Chapter We have to show (x + y) (x y) = and (x + y) + (x y) = 1. (x + y) (x y) = x x y + y x y = + = (x + y) + (x y) = x( y + y) + y (x + x) + (x y) = xy + x y+yx + y x + x y = x ( y + y + y) + x(y + y) = x + x = 1
17 Chapter ND version: B C= + B + C The truth table below verifies the ND version. B C B C + B + C OR version: + B + C= B C The truth table below verifies the OR version. B C + B + C B C
18 18 Chapter From the 3-input NND gate shown in Figure 2.23b, we can see that each additional input needs an inverter and a 2-input NND gate. Since we implement the inverter with a 2-input NND gate as well, we need two 2-input NND gates for each additional input. Thus, for an n input NND gate, we need 1+2(n 2) 2-input NND gates. To build an 8-input NND gate we need 1+2(8 2)=13gates Since there are four gates in the 74 chip, we need four 74 chips.
19 Chapter (a) (x +y) (x +y) = (x y) x y (de Morgon s law) = (b) x + yx = x (1 + y) + yx = x + xy + yx = x + y (x + x) = x + y (c) B B = ( + B) ( + B) = + B + B + B B = B + B
20 2 Chapter Truth table: B C F Sum-of-products form: B C + BC + B C + BC Product-of-sums form: ( + B + C) ( + B + C) ( + B + C) ( + B + C)
21 Chapter We start with the product-of-sums expression and derive the sum-of-products expression. ( + B + C) ( + B + C) ( + B + C) ( + B + C) =( + B+C+ B+ BC+ C+B C) ( +B + C) (+B+C) =( BC+ B C+B+ BC+ BC+ BC+C+ B C) (+B+C) = B C + BC + B C + BC
22 22 Chapter Logic expression for Figure 2.1a is ( B). Logic expression for Figure 2.1b is + B. We show that this expression is equivalent to ( B). + B= B (de Morgon s law)
23 Chapter We start with the product-of-sum expression and derive the other expression. ( + B + C) ( + B + C) ( + B + C) ( + B + C) =( + B+ C+ B + BC+ C+B C) ( + B+C) (+B + C) =( + B+ C+ BC+ C+BC+ B+ B C + B C+BC)(+B + C) = BC + B + BC + BC + BC + C + B C By observing that B + BC + BC + C is equivalent to ( B C), we derive the sum-ofproducts expression.
24 24 Chapter We start with the product-of-sums expression and derive the sum-of-products expression. ( + B + C) ( + B + C) ( + B + C) ( + B + C) =( + B+ C+B+ B C+C+ B C) (+B + C) ( +B+C) =( B C+ B C + B+ BC+B C+BC+ C+ B C) ( +B+C) = B C + B C + B C + BC
25 Chapter Replace the exercise in the book by the following: Using Boolean algebra show that the following two expressions are equivalent: B C + C D + B C + B D + BC + C + BCD Solution: + B D + C D + B C + BCD B C + BC + C D + B C + B D + C + BCD = C(B + B) + C D + B C + B D + C + BCD =( C + C) + C D + B C + B D + BCD = + C D + (1 + C D) + B C + (1 + B C) + B D + (1 + B D) + BCD + (1 + BCD) = + C D + B C + B D + BCD
26 26 Chapter The logic circuit is shown below:
27 Chapter We need a 7-input XOR gate to derive the parity bit. We can construct 1 7-input XOR using 2-input XOR gates as shown below: P We need to add an inverter at the output to generate odd parity bit.
28 28 Chapter B D + C D + BD = B D(1 + C) + C D (B + B) + BD = B D + B D C + BC D + B C D + BD = B D + B C(D + D) + BD(1 + C) = B D + B C + BD
29 Chapter The truth table is shown below: B C F B C + B C + B C + BC = C(B + B) + C(B + B) = C( + ) = C Clearly, we just need one inverter to implement this simplified logical expression.
30 3 Chapter The truth table is shown below: From the following Karnaugh map B C D F B CD C D we get the simplified logical expression as (C D). We just need a single NOR gate to implement this.
31 Chapter The following table finds the prime implicants: Column 1 Column 2 Column 3 B C D p C D p C D B C D p B C D p B C D p B C D p BC D p C D p There is no need for Step 2. The simplified expression is C D.
32 32 Chapter The truth table is shown below: B C D F From the following Karnaugh map B CD we derive the simplified expression as B D + B C + BD + BC = B(C + D) + B (C + D) The following circuit implements this logic expression:
33 Chapter 2 33 B C D B C D
34 34 Chapter The following table finds the prime implicants: Column 1 Column 2 B D B C D p B C B C D p BD BCD p BC B C D p B C D p BCD p Step 2: Prime implicants B D B C BD BC Input product terms B C D B C D BCD B C D B C D BCD N N N N The minimal expression is B D + B C + BD + BC = B(C + D) + B (C + D)
35 Chapter The truth table is shown below: B C D F From the following Karnaugh map B CD we derive the following simplified logic expression: B C D + B CD + B C + BD = B C ( D + D) + B C + BD n implementation of this logic expression is shown below:
36 36 Chapter 2 B C B D D B C
37 Chapter The following table finds the prime implicants: Column 1 Column 2 B C D B C B C D B C D p BD B C D p BCD p B CD BCD p Step 2: Prime implicants Input product terms B C D B C D B C D BC D B CD BCD B C B C D BD B C D B CD N N N N We derive the following simplified logic expression: B C D + B CD + B C + BD = B C ( D + D) + B C + BD
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