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Transcription

1 FEATURES!" #$$ % %&' % '( $ %( )$*++$ '(% $ *++$ %(%,- *(% (./ *( #'% # *( 0% ( *( % #$$ *( '( + 2' %( $ '( 2! '3 ((&!( *( 4 '3.%" / '3 3.% 7" 28" 9' 9,*: $ 9,*: $% (+'( / *(.( # ( 2(- %3 # $((% # ;' '3$-,( #, $,(,9,'3-% &,- # (%& ( = 0,% %,( #, $,(,9,'3-% & 0,% #% ( - + % '% #%,( #, $,(,9,'3-% & ( $ ( ( = 7( *( $ ( %'( + &% $& $ $' (-, ( ( /= $ (-('% / $('% $'$ 9, ' -& APPLICATIONS ($( &%% (,., ( 2 + $ ('( &%% GENERAL DESCRIPTION 2 (% %&' % '( $ %( (% $ '('(% $(' ($% +& ($$ + $! %&' % '('( ' % ( %(- '3- (% $%(-$ + % ( (''%% %$ %&%% $ & %$ ( $ ( $( ( ==/= $(' ++% %(- # %( + ==.=" ==/.=="?="?=" /=!! $ /!! (''%% +((% (% +('$ %(- $'$ & " ( (- +' $%(& 2,#. = '%% ($ (- +' $ '%(" $ (% '3-$ ( (,#," = (,#," $ (,9 ORDERING INFORMATION Part No. Pin Package Operating Temperature Range ==/=@,9 ==/=7. #, ==/=,.= =,#, ==/=,.,#, ==/=@,9 A= ==/=7. #, A= ==/=,.= =,#, A= ==/=,.,#, A=

2 * * #, #,/,, #,, 8 8 $ -(%% % -(% 8 8 $ -(%% % -(% - + '% #,, '( ' 9-(', * #,, # *% ( # ((- #; * *% *++ * $ '$ # # *( 0.( $$%% '$ # %'( B 22 #2# #2 #: #7.9: Figure. Block Diagram of the XR88C8

3 PIN CONFIGURATION ; #, 22.9: 7 / B * *,, / # Lead PDIP (0.00 ) / = = / = / = / / = = / = 40 Lead PDIP, CDIP (0.00 ) / #7,/,,,.9: #, 22 #,.#2# #,.#2 #,/.#: ; 07,,,, * * B #, #, #, XR-8C8CJ PLCC 22.9: 7,,,,,, * 7 * B #, 44 Lead PLCC,,/ #, #, 7 ;'' #,.#2# #,.#2 #,/.#: #, 07 7 #7 / = / = / = / = /

4 PIN DESCRIPTION 44 PLCC/ LCC 40 DIP, CDP 28 DIP, CDIP Symbol Type Description 7 No Connection. # LSB of Address Input. (% (" - ( $$%% #%" %$ %' '( -(%% ( ( $('" $(- 2 $ B#2 (% (, #, #? # Input Port 3. 0,% # B (% (- ( #$" (% ( ' % %$ %! ''3 ( + %( B (% (- (?$" (% ( ' %$ %! ''3 ( + '( # Address Input. #, * / # Address Input. # Input Port. 0,% # (% ( ' % %$ % '( 9" C * $D ( * / # MSB of Address Input. (% (" - ( $$%% # %" %$ %' '( -(%% ( ( $('" $(- 2 $ B#2 (% (, = #, # Input 0. 0,% # (% ( ' % %$ % '(" C $D ( = B # Write Strobe (Active-Low). CD (% ( ( (% % CD (% '% + *% ( $ $%%$ -(%" ( ( %+ ''% (%(- $- + B / # Read Strobe (Active Low). CD (% ( ( (% % CD '% '% + $$%%$ -(% " $ % * # Receive Serial Data Input (Channel B). % %(-(+(' ( + ' ' (% '($ +(% #+! '( ''3" *" (% %'(+($" $ (% %$ (%(- $- + (% ''3 7 No Connect. = * Transmitter Serial Data Output (Channel B). % %(- (+(' ( + ' ' (% %($ +(% (% (% $ ( (- 3(- % %( (% ($" $(%$" ' (% (- ( ' 9, *: $ #+! %( ''3 (% %'(+($" *" %($ $ (% % (+$ + % ( (+ -(% +(- $- + (% ''3

5 44 PLCC/ LCC 40 DIP, CDP 28 DIP, CDIP, *, * *. G /, G. 99 *, G * Symbol Type Description = / #. Bi-Directional Data Bus. #. Bi-Directional Data Bus. = #. Bi-Directional Data Bus. Output (General Purpose Output). (% ' % -$ +'( % '(" C * E%$D * Output 3 (General Purpose Output). (% ' % -$ +'( %4 C * % ( ''3D * " C * '( ''3D * " $("'( C.( $&D. G Output (General Purpose Output Pin). (% ( ' % -$ +'( % $(" '(" * C'( $&D C'( # D ($(' G *. 99 * Output 7. (General Purpose Output Pin). (% ( ' % -$ +'( % $(" '(" C%( $&D ($(' + *G * #. MSB of the Eight Bit Bi-Directional Data Bus. %+%, $ 3 ' (% % '%(%(- + (% % (% (%$ ( (% C (- D"!' $(- #: '&' (? $ 07,B Signal Ground. 7 No Connect. #7 Interrupt Request Output (Active Low, Open Drain). #7 (% %%$ ''' + + ' (H% %3 ((- '$((% (% %(- ( ( %%$ - # (' ( $ ( -$ ' '$((% '%(- # E% % (($ / / #. Bi-Directional Data Bus. / #. Bi-Directional Data Bus. = #. Bi-Directional Data Bus. = #. LSB of the Eight Bit Bi-Directional Data Bus. %+%, $ 3 ' (% % % (% (%$ ( (% C (- D"!' $(- #: '&' (?$ /,/ G Output (General Purpose Output). (% ( ' % -$ +'( % $(" '( " C%( $&D ($(' + G

6 44 PLCC/ LCC 40 DIP, CDP 28 DIP, CDIP, G. 99 =, /, Symbol Type Description Output 4 (General Purpose Output). (% ( ' % -$ +'( % $(" '(" C'( $&D C # D ($(' + G. 99 Output 2 (General Purpose Output). (% ( ' % -$ +'( % & + + (-4 %( / ''3 / " '( ''3 Output 0 (General Purpose Output). (% ( ' % -$ +'( % '(" E%$ + Transmitter Serial Data Output (Channel A). % %(-(+(' ( + ' ' (% %($ +(% (% (% $ ( 3(- (- % %( (% ($" $(%$" (- ( 9' 9,*: $ #+! %( ''3 (% %'(+($" " $ (% % (+$ + %( (+ -(% +(- $- + ''3 7 No Connect. # Receive Serial Data Input (Channel A). % %(-(+(' ( + ' ' (% '($ +(% #+! '( ''3" " (% %'(+($" $ (% %$ (%(- $- + ''3 /.9: # Crystal Output of External Clock Input. (% ( (% ''( + %($ + '&% $ ''( -$ ( %'( (% %$ #+ %'( (% %$"! ''3 %(- % %($ (% ( # $ + ==/= $(' +'( &" % % %& %(- ( +E'(% 8I $ 8I (% E( ' & ( '&% %'( &! 9'( ''3 %(- Crystal Input. '( + %($ + '&% %( +.9: #+ %'( (% %$" ''( % % ''$ + (% ( -$ (% ( % + (+! ''3 (% %($.9: /

7 44 PLCC/ LCC 40 DIP, CDP 28 DIP, CDIP Symbol Type Description = 22 # Master Reset (Active High). %%(- (% ( '% ( -(%%" " #" #","," $ ((((I% #; / %%(- (% ( % %%. (" %,, ( (- %" $ '% %( ' % ( ('( % ( $ * % 3(- (- / # Chip Select (Active Low). $ % (% (%$ (% C (- D %+%, $ ( $ (% CD / #,. 2 #,/ * # Input 2. (General Purpose Input). (% ( ( ' % -$ +'( % C.(! ''3D (. 2 # Input (I-Mode). 0,% # ( (% ( ( ' % -$ +'( % 2! '( '3 + * * #: # Interrupt Acknowledge Input (Z-Mode). '( 9 (% ( (%,H% %% # E% (%%$ & $(' B, %%% (% (" ( ($('% H% ( E% (% %('$" $ &! '&' ( # '3$- &' ( %$,H% # '3$- & '(- '% + # ;' -(% #; $ % = #, * = #2?$ #, #2#?$ # Input (I-Mode). 0,% # ( (% ( ' % '+(-$ +'( %! ''3 ( + %( + * * Interrupt Enable Output (Z-Mode). '( 8(- (% ( (% & C (- D 8" ( + +(- '$((% ' '% (% ( -$ --$ CD #+ #2# # 2 # ( (% CD #+ #2 (% CD '% + #2# (" #2 ( -- C (- D ' #2# % --$ C (- D % (%%$ # E%, #7 ( (% --$ CD #+ #2 (% CD '% % E%$ #" #2 ( ( CD" - # (' (" (, % (3$ CD '$ # Input 4 (I-Mode). 0,% # ( (% ( ( ' % '+(-$ +'( %! ''3 ( + '( + # Interrupt Enable Input (Z-Mode). '( 8(- #+ (% '( (- ( (% -(' C (- D" (% ' + -(- %3$ # E%%, #+ (% ( (% -(' CD" (% ( (($ + -(- & # E%%, = ;,B Most Positive Power Supply.

8 DC ELECTRICAL CHARACTERISTICS, 2, 3 Test Conditions: J" ; J; K %% (% %'(+($ Symbol Parameter Min. Typ. Max. Unit Conditions ; #9 # 9 ;- = ; ; #8 # 8(- ;- ; ; ; #8 # 8(- ;- ((& ; J ; #8 # 8(- ;-.9: ; ; ; 9 9 ;- ; # 9 J ; 8 8(- ;- ; # 8 J # #9 # 93- ; #7 J; # #929 ',( 93- A ; #7 J; # 9 # 9 ; #7 J # 9 # 9 # #8 # 8(- ; #7 J; # 8 # 8(- ; #7 J; # 99 *% ( 93- ; J; # ( 93- ; J; #, & / '( $ #, & $& $ Notes. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 2C, V CC = V and typical processing parameters. 2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure For prime grade N, P, J, L, M, ML, V CC =V+0%. 4. Measured operating with a 3.84MHz crystal and with all outputs open. =

9 AC ELECTRICAL CHARACTERISTICS, 2, 3 Test Conditions: J" ; J; K %% (% %'(+($ Symbol Parameter Min. Typ. Max. Unit Conditions Reset Timing (See Figure ) 2 22,% B($ XR88C8 Read and Write Cycle Timing (Figure 2) 4 ( " B % 9 8 8$ ( + " B % 9 ( " B 9 % 8 8$ ( + " B % 8(- B " B,% B($ % ;($ + 9 / % *% (- + 8(- % ( B 8(- % 8 8$ ( + B 8(- % B 8(- ( * $% $. B(% " / % Z-Mode Interrupt Cycle Timing (Figure 3) # #2 & ( + #2# % # #: ( 9 % #8 #: 8$ ( + 8(- % 2# #2# ( 9 % 2 #2 & ( + #7 9 % Port Timing (Figure 4) 4,, # (. 9,8, # 8$ ( +. 8(-,, ;($ + B. 8(- Interrupt Output Timing (Figure ) # Clock Timing (Figure ) 9: 9: #7,, %$ % #% 8( #% % *(% ( # #, + # %3 ( #.9: 2! 8(- 9 (.9: &% 2! E'& % % % % % % 8I

10 AC ELECTRICAL CHARACTERISTICS, 2, 3 (CONT D) Test Conditions: J" ; J; K %% (% %'(+($ Symbol Parameter Min. Typ. Max. Unit Conditions Clock Timing (Figure ) (Cont d.).( 2! '3 % 8(- 9 ( #,.( 2! '3 8I E'& $ 2! 8(- % 9 ( = + $ 2! E'& / Transmitter Timing (Figure 7) & % 2! 9 & # 9 % ( % 2! 8(- 8 8$ ( + % 2! 8(- Notes. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 2C, V CC = V and typical processing parameters. 2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure AC test conditions for outputs: CL = 0pF, RL = 2.7k to V CC. 4. If CS is used as the strobing input, this parameter defines the minimum high time between CSs.. Consecutive write operations to the same register require at least three edges of the X clock between writes.. This specification imposes a MHz maximum 8000 clock frequency if a read or write cycle follows immediately after the previous read or write cycle. A higher 8000 clock can be used if this is not the case. 7. This specification imposes a lower bound on CS and IACK low, guaranteeing that they will be low for at least one CLK period. 8. The minimum high time must be at least. times the X/CLK period and the minimum low time must be at least equal to the X/CLK period if either channel s Receiver is operating in external X clock mode. / 8I 8I Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS & ;- ; - / ;-% ( %' 0$ ; A;. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the Electrical Characteristics section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

11 2. This product includes circuitry specifically designed for the protection of its internaldevices fromdamaging effectsof excessivestatic charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltage larger than the rated maximum.

12 SYSTEM DESCRIPTION ==/= '%(%% + ($$" +$! '('( ' %L ' '%(%(- + ( %( $ '( 2' ' + & ($$& -$ + (- $ $ $ + ' (+' ($ - + '%%% ( (( + '% (- %$ + ' '( $ %( & %'$ + + (& -$ +(!$ ( %" + ''3 $($ + ( '.(" +!& %($! /! ''3 ( - %' + $(++ +(!$ ( % ' $('& + '&% ''$ '%% (% +! ''3 ((& ($$& - (- %$ + '( $ %( + ' ' 3% '( + %( %$ ' ('(% %' % '%$ ( %&%% '( $ (% E$$ ++$ $ %( $ (% $++$ ( ' ( # % ( $ (((I (%3 + '( $ $' $ ( ( $( ('(% % ($% + ' '((& ( (( %(%%( + $(' ++ + '((- (% +" % (- %% + $ % ($% - % / ( '.( (' & % %$ % - ( -%" ( (% ( $ = ( (% + ( #, $ (,9 '3-% & PRINCIPLES OF OPERATION Figure %% '3 $(- + % (%$ ( '3 $(-" '%(%% + +(- M +'( '3%4 *% *++ # #, ( ('( % $ * ( ((-, A. DATA BUS BUFFER $ % ++ ($% (+' ( ( ( ' ( $! $ %% # (% '$ & ( ' '3 $ %+% 3 ' %, $ B. OPERATION CONTROL BLOCK ' -(' + ( '3 '(% (- '$% +, $ -% %(-% (% %'(% + ( *'3 +'(% % % (+' % + $(' '(+('&" ( (% %%( + -(% $$%% '$(-" $ $ '$(- + '$% % $ %" (&" '('( ' %" % %.( $(- C%% -(%D ( $ '('( +' % - - ( *'3 ( *'3 ( ' +' %$ +(- ( %(-% $$%% #%" B 22 B %(- /= +(& '%%" ( E( % - -(' #+'(- /= (&,'%% ' %(& ' ($ & ('$(- % +! -(' $('%" % $('$ ( Figure 2

13 .B B 2 '' Figure 2. External Logic Circuitry required to interface a 800 Family Processor to the XR88C8 Device B. DUART Register Addressing $$%%(- + ( -(%% + (% %$ ( Table Please note that some of the registers are Read Only and others are Write Only. 2' ' (% ($$ ( +(- $$('$ $$%% -(%% $ -(%% $ -(%% $ % -(%% '3 ' -(%% '( 8$(- -(% 8 $ %( 8$(- -(% 8 $$((&" '(% +(- -(%% %.' ' % # % -(% # %3 -(% %3$ # % -(% # ;' -(%!((& -(% $ +(&" % '(% -(%% % +'(% %( $ '('(" %' % % $ '%.(%,, -(% #, #, +(-( -(%.( *& -(% 9.( 9 *& -(%

14 Address (Hex) Read Mode Registers Write Mode Registers $ -(%" % -(%" %3$ # % -(%! 8$(- -(%" #, - -(% # % -(% /.( *& -(%.( 9 *& -(% = $ -(%" * % -(%" * Register Name Symbol Register Name Symbol " $ -(%" " '3 ' -(%" # $ -(% 8! 8$(- -(%" 8 #,!((& -(% # # %3 -(% # 9 *" * *.( *& -(%.( 9 *& -(% $ -(%" * '3 ' -(%" * 22;2 $ -(%" * *! 8$(- -(%" * # ;' -(% 8*! 8$(- -(%" * # ;' -(% #, #,, +(-( -(%,, 2.( $.( $ #;, *(% $, *(% $ 9 *" * * * 8* #;,,*,* Table. DUART Port and Register Addressing Note: The shaded blocks are not Read/Write registers but are rather Address-Triggered Commands. Table ($('% ' ' (% E($ ( $ -(%% %%'($ ( ' + % $ -(% (% (% C$ -(%D ( ( ' (.%&% 22 ' ( (% C((- D ' -(% Please note that the suffix n is used at the end of many of the DUART registers symbols in order to refer, generically, to either channels A or B 8" '% + ( ( % (+ + $$%% + -(% + -(%" ($(& +(- & $ B( ''%% -(% ( ( '( C( D -(% ( $ % ''% ( C22,#72D '$ % (3$ C22,#72D '$ ' (%%$ & ((- ( $ ( ' H% $ -(% +" $ -(%%" ( ( -(

15 ' " % -(' $$%% +% $ +'(% + '$ & $ -(%% $(%'%%$ ( $( ( Section G.3 B.2 Command Decoding 2' ' (% E($ ( $ -(% # -" + % $ -(%%.$(% %(".$(% '(" - ( +'(((- %(% + (%'% '$% ( + + ' $ -(% (% %$ ( Bit 7 Bit Bit Bit 4 Bit 3 Bit 2 Bit Bit 0 Miscellaneous Commands Enable/Disable Receiver Enable/Disable Transmitter (-! J 7 - J 2! J (%! J 7 ($ $ % J 7 - J 2! J (%! J 7 ;($ % Table 2. (CRA, CRB) Bit Format for Command Registers of Channels A & B +'( + ( + $ -(%% (% +(& %(- +$ (% ( (% %$ ( $(% %( $. '( ( + $ -(% (% %$ (3 %(% + (%'% '$% Table 3 $+(% '$% %%'($ ( ( + $ -(%% Please note that the upper nibble commands through B effects only the performance of Command Register s Channel 8" '$% / $ / ++'% %&% ' ( ( Bit 7 Bit Bit Bit 4 Description Null Command. Reset MRn Pointer. %% H% ( ( Reset Receiver. % ($(($ ' '( % (+ 8$ % % ($ '( (% $(%$ $ # (% +% $ Reset Transmitter. %% ($(($ ' %( % (+ 8$ % $ ($ (% +'$ (- Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified (Cont d Next Page)

16 Bit 7 Bit Bit Bit 4 Description Reset Error Status. % '($ *3 *",(& 2,2" (- 2 2 $ 2 2 %% (%" N4O '(+('&" (+ 2 $" + (' ' (% % C*'3D 2 $" (% '$ ( % + '( 2 #$('% ( % -(% # *'3 2 $" ' (,2" 2" 2" * ''%" ( '( +--$ ( % -(%" ( (% '$ (% (%%$ #+ 2 $" + (' ' (% % C ' 2 $D" '% + % -(% +,2" 2" $ * +'$ ' ' & ' ' %(% # C ' 2 $D" % + % ($('% (% %$ & ' ' (% ($(' (% &% %$ % C*'3 2 $D ($('" $ E(% (% '$ % Reset Break Change Interrupt. % ' H% 3 ' - ( %% ( Start Break. '% %( % $ % 3 #+ %( (% &" % + 3 & $&$ ( (% #+ %( (% ' (" 3 -(% %(%%( + % ' '% ( 8 (% '$" (I" 2, % + 3 ( -( Stop Break. ( ( - (- ( ( ( (% ( ( (- + ( ( +! ' '" (+ &" (% %($ Set Rx BRG Select Extend Bit. % ' H% C'( *0 ' 2!$ *(D Clear Rx BRG Select Extend Bit. % ' H% C'( *0 ' 2!$ *(D Set Tx BRG Select Extend Bit. % ' H% C%( *0 ' 2!$ *(D Clear Tx BRG Select Extend Bit. % ' H% C%( *0 ' 2!$ *(D Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified (Cont d) /

17 Bit 7 Bit Bit Bit 4 Description Set Standby Mode (Channel A). B (% ' $ (% (3$ ( $ -(% " (% $ + ' + %(%" '(%" '.( $ $$(( '('(% ' ( %$& $ Please note that this command effects the operation of the entire chip 7 ( (% %$ & $ % & (3(- C2 #;2 2D '$ Reset IUS Latch (Channel B). B (% '$ (% (3$ ( * $ -(%" $ (% (- (?$" ( '%% #$(' # ' % (%" ( " ( '% #2 -- C (- D Set Active Mode (Channel A). B (% ' $ (% (3$ ( $ -(% " (% $ + $& $ $ %% ( Set Z-Mode (Channel B). B (% '$ (% (3$ ( * $ -(%" (% '$(($ (?$ $($ $(%'%%( + H% ( ( (?$",% % Section C..2 7 ( + = ( #, '3-$ $('% Reserved. Reserved. Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified (Cont d) # $$(( '$% (' ( - '$ -(%%" % ++% C$$%%(--$D '$% % '$% (%$ ( Table " C, 7 20#2 2#70DL $ + ($(+($ & (- C% $$D ( Table '(+('&" % '$% 4 72.#2 7, 72.#2 7 2,, *# 7 92,, *# 7 2' + % '$% (3$ & ( $(- ((- $ ( '%$(- $$%%% % %'(+($ ( Table 2!4 72.#2 7 (% (3$ & '$ + $(- $$%% 2 / Please note that this Read Operation will not result in placing the contents of a DUART register on the data bus. & (- ( " ( %% (% '$ (%.( ( ((( '(- $($ $(%'%%( ( ( +.(" % % Section D.2! + $$%%(--$ '$% (% C2,, *#D $ (% '$ (% (3$ & +(- ( + $ $$%% 2 / B % (3% (% '$".% (% %(- '( (% CD ( (,, -(% (%" ( (, %'(+($ %" ' -$ % + (% '% + ($(($ (% ( (, 8'" (+,NO (% % CD" % + '%$(- ("," (% % -(' CD %E&" ' (3 + C2,, *#D '$ % C92,,,#7D '$ $($ $(%'%%( ( ( +,%" % % Section F

18 C. INTERRUPT CONTROL BLOCK # *'3 % % & ( C# (D ( ('$% ( E% %(- #7" (' & -$ %%$ ''' + & + +(- %4 %( 8$ -(% * $& '( 8$ -(% * $& '( # * 2$ + '($ *3 ( % * 2$ +.( ' $ - + ( (%" #," #," #," #, # *'3 '%(%% + # % -(%% #" # %3 -(%% #" %3$ # % -(%% # $ # ;' -(% #; Table 4 (%% % -(%%" ( $$%% '( ( ( Register Description Address Location (in DUART Address Space) # # # #; # % -(% # %3 -(% %3$ # % -(% # ;' -(% / $ & / B( & / $ & / Table 4. Listing and Brief Description of Interrupt System Registers $ % + ' + % -(%% $+($ C. Interrupt Status Registers (ISR) '% + # ($('% %% + ( ( '$((% #+ & (% ( ( % -(%% --$ C (- D" '%$(- '$(( % (% ''(- # -" '% + # ( ($(' '%%" %' % + # E% + +" & ( %(' ( + % $ -( & $(- ( (% -(% # %3$ # % -(% (+ + # (% %$ ( Table 4 Bit 7 Bit Bit Bit 4 Bit 3 Bit 2 Bit Bit 0 Input Port Change JG% Delta Break B JG% RXRDY/ FFULLB JG% TXRDYB JG% Counter Ready JG% Delta Break A JG% RXRDY/ FFULLA JG% TXRDYA JG% Table. ISR Bit Format $+((( + (- ($ ' + % (% (% %$ ISR[7]: Input Port Change of State #+ (% ( (% -(' CD" ' - + % % $'$ #, (% #, #, % $ %(' (% ( & $(- #, (+ #NO J #NO (% '$, % $ #, +(-( -(% #, *& $(- #," % ( $(4 ($(($ #, ( ' -$ % +( % + ($ ( %" +(- - + $($ $%'(( + #," % Section F Please note that in order to enable this Interrupt Condition, the user must do two things: B( ( $ ( +!((& -(%" N4O # (% %" % (% %'(+&(- (' #,(% % $ (-- C#, -D # E% =

19 B( -(' CD #NO ISR[] Delta Break Indicator - Channel B B (% ( (% %" ( ($('% * '( % $'$ -((- $ + '($ 3 * (% ( (% '$ %, (3% ' * C22 *2: 8702 #72,D '$ % Table 3 (+( ( H% %% *2: '$((" % % Section G.2 ISR[] RXRDY/FFULL B - Channel B Receiver Ready or FIFO Full +'( + (% ( (% %'$ & -(- *N/O #+ -$ % '( $& ($(' G*" ( ($('% % ' ' + $ (% ( 8* $ (% $& $ &, (% ( (% % ' ' (% %+$ + '( % (+ -(% 8* $ (% '$, $% 8* #+ %( ' '% ( 8* + $ (" ( ( % -( + 8* (% C$D #+ (% ( (% -$ % # + ($(' 99*" ( (% % ' ' (% %+$ + 8* $ %+ '%% 8* ' + (% ( (% '$, $% 8*L $ & C(-D # " 3(- +! ' ' #+ ' ' (% ((- ( '% 8* (% +" (% ( ( % -( + $ (" ' ' (% $$ ( 8* Note: If this bit is configured to reflect the FFULLB indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in RHRB, following data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. ISR[4] TXRDYB - Channel B Transmitter Ready (% ( (% $(' + G *" *NO (% (" %" ($('% 8* (% & $ (% $& '' ' ' +, ( (% '$, (% ' ' 8*L $ (% % -(" ' ' (% %+$ G* (% % %( (% (((& $ $ (% '$ %( (% $(%$ '% $$ ( 8* ( %( (% $(%$ ( %($ ISR[3] Counter Ready # #2 $"..( ( % #NO ' ' '&' + % %E (, ( #NO ( '$ & (3(- C, 72D '$ * ( ($" ( #2 $" C, 72D '$ ( %. # 72 $" (% ( (% % ' ' % ( ' / $ (% '$ ' (% %$ & C, 72D '$ B.( (% ( 72 $" C, 72D '$ ( %.( ISR[2]: Delta Break A - Channel A Change in Break %%( + (% ( ($('% ' '( % $'$ -((- + $ + '($ 3 * (% ( (% '$, (3% ' C22 *2: 8702 #72,D '$ (+( ( H% %% *2: '$((" % % Section G.2 ISR[] RXRDYA/FFULL A - Channel A Receiver Ready or FIFO Full +'( + (% ( (% %'$ & -(- N/O #+ -$ % '( $& ($(' G" (% ( ($('% (% % ' ' + $ ( 8" $ (% $& $ &, (% ( (% % ' ' (% %+$ + 8 $ (% '$, $% C%D 8 #+ %( ' '% ( 8" +(- $ (" ( ( % -( + 8 (% C$D #+ (% ( (% -$ % # 8 + ($(' 99" ( (% % ' ' (% %+$ + 8 $ & %+$ ' ' '%% 8 ' + (% ( (% '$, $% 8 #+ ' ' (% ((- ( '% 8 (% +" (% ( ( % -(" +(- $ (" ' ' (% $$ ( 8 Note: If this bit is configured to reflect the FFULLA indicator, this bit will not be set (nor will produce an interrupt request) if

20 one or two characters are still remaining in RHRA, following data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. Therefore, the user is advised to read RHRA until empty. ISR[0]: Channel A Transmitter Ready (% ( (% $(' + G " NO (% (" %" ($('% 8 (% & $ (% $& '' ' ' +, ( (% '$, (% ' ' 8L $ (% % -(" ' ' (% %+$ G (% % %( (% (((& $ $ (% '$ %( (% $(%$ '% $$ ( 8 ( %( (% $(%$ ( %($ C.2 Interrupt Mask Register (IMR) # %3 -(% (% CB( &D -(% (' % % %' '$((% ( '% (%% # E% '%% # $%" % % ( + %3(- '3(- '( '$((% + '%(- (%% # E% +" (+ + # (% %%(& % % # 8" + '%%" *( + # (% %$ Bit 7 Bit Bit Bit 4 Bit 3 Bit 2 Bit Bit 0 Input Port Change J++ J Delta Break B J++ J RXRDY/ FFULLB J++ J TXRDYB J++ J Counter Ready J++ J Delta Break A J++ J RXRDY/ FFULLA J++ J TXRDYA J++ J Table. IMR Bit Format #+ % (% % '( (".% % $ ( CD ( ( ( #" '%$(- # $(( 9(3(%" $(% %3 '( '$(( '%(- (" % % $ ( CD ( '( '%$(- '$(( (% % $ ( / CD% (% -(%% Please note that IMR is a Write Only Registers, and can therefore not be read by the processor. C.3 Masked Interrupt Status Register (MISR) ' + # -(% (% %('& %% + 7(- # $ # - # J N# %O N# %O ((( + # (' (% & $(- # (% (% ( ( # ' -- C (- D $ ( '%$(- '$((% & $ & # +" %" +(- $(- # % -(%" ( 3 (%(% +L $!' C(&(D 7 + # $ # '% (' # (% CB( &D -(% $ ' $ & '%%" '% + # ( %$ ( %&% &" + ' $$(( $ $ %+ $ E($ % (% '((& ' (($ ( % + # C.4 Interrupt Vector Register, IVR (% -(% (% & %$ + # ;' -( (% '$$ ( %'(?$ B ( ( (% $" '% + #; (% &('& $ %(- $$%% + % # (' ( (%" ( #$" # ;' -( (% &('& +$ ++' ( B (% (- ( #$" #; ' %$ % - % $.( -(%% + #;" ( (% (- (?$ (% %$ ( Section C. C. Limitations of the DUART Interrupt Structure # ' ++$ & % % - - (% ( %% '( 8 $ 8 # '$((%L.( $& '$((" $ ' -% ( *3 $(( '( 8" %($ + C *3 $((D *" H% # ' $% + ( E%% $

21 '( % %' %,(& 2,2" '( 2 2" (- 2 2 % $% ++ % ((& '+(- + % & ''' + & + % '$((% +" %% % (% ((- % % + C 9(3 9&D ' '3(- %' %' % " % (% $(%$ C($D '($ $ & +E& $(- % -(%L $ ' '3(- + & I ( % (% (% %'(& '% (+ % % % 2 $ C 'D NO J C. Servicing DUART Interrupts # %('(- ( ==/= +% ( $ '-(%4 #$ $?$ #$ % (%('& +$ % C#D $ 9(3(%"?$ % +$ % C?(-D $ B (% (- (?$" ( ' = ( C( 'D $ %"," $(- C# '3$-D #: '&', ( $ (% ( ' + *%" $ $( + # ;' $ '( + ( ( %(' (" ( %&% & $$((&"?$ -(% % $ ' (((I ( E%% - % ( $('% (% (% $(%'%%$ ( - $( ( Section C..2 B (% (- ( #$" ( ($ & ( ' (+(," $(- #: '&' # ;' (+(" & % - ' ( # (' (" (% ''(% $! ( ( #$ +(- $ % % % (3 C?$D '$" ( $ '$ (?$ - #$ % +$ % C#D $" $?$ % C?(-D $L (% $% % % $ & (?$ (+'(-?(- (''%%" ( #$ (+'(- # (''%% $((%( #$ $?$ (% '%%& - C'D (% #+ & (+'(- +(- (''%%%. (''%" % ( #$ =, ==, ==, /=8?=, # $% $ 8" % $ (- (?$ (+'(- +(- (''%%%. (''% ===, ==/, ==/ ==/,%,(,?=, # $%! + %'(% ( ($ $($ $(%'%%(% +.(''%% (+'(- $ ( '%%(- ' + ($ (''%%% (% $(%'%%(" $($ $%'(( + #$ # '%%(- $?$ # '%%(- ( - C.. I-Mode Interrupt Servicing ( ( #$ +(- + #" $ % # -", (+'(- (- ( #$" ( +'( % +%" $(- ( %('(- #+ E(% ( %(' +," ( ( %%% #7 (, ', % $'$ ( E%" ( ( $( '( + ( ( %(' (" $ ( ' - ' '(, ( ''(% + (% ( ($(- C# '3$-D %(- & + ('( ( ', % (($ '%% + H% ( E%" ( - (% #7 (, (!( CD ( %(' ( $ ( % '%%(- # - ' %,% '& % ' ( ( %(' (" (+'$ ( #$ (' #,'%%(- 2! ;'$#,'%%(- Direct Interrupt Processing #+, &% C(' #,'%%(-D ', % $'$ ( E%" $ % '$ (% ' (%'(", ( ' - ' %'(+(' '( ( %&% &

22 ,% & $(' (%" (% C'(D (% +(!$ &, '('(& (%+ 2!4 #+ #7 ( E% ( (" + = " (% %%$", ( ' - ' '( / ( %&% & (% '( (% +(!$ & '('( $%(- + =, $ ' ' -$ & % (External) Vectored Interrupt Processing,% & (% + + ( '%%(- &('& # '3$- ( (% C#:D C#7D ( %$ - C( 'D (+( *%" (! $ C2!D (% %$ $%'( (% + + '$( '%%(-L '% '( + ( %(' ( (% $($ & $ C!D %,%" %' % == $ ==," (% C( 'D (+( (% & '$ + 99 (%'( %'( C2 %(D '( + (% C2 %(D (% +(!$ &, '('( $%(- #+ % &% (% ' + ( '%%(-".% (% %%( + (%(- ( ( %(' (" '$(( ' (%'( ( %(' ( %($% (% '( ( & 2' + % #,'%%(- ' (E% ( %$ ( - $( ( +(- %'(% % ($ (" % $ (- ( #$" (+'$,. %$ ( Table 7 Table 7 % %% & + ( '%%(- (% &$ & ' + %,%. % P/ C Type of Interrupt Processing Comments = (' = %! # E% (%4 #7 $ #7 ==, 2! ;'$ ==, ( % + = $(++ '$% + C99D (%'(% # (' (% ==, $ ( ( ' 3$- " #7" (' ' %$ C-D C99D (%'(% *% ==, (' $ 2! ;'$ ==, % C('D! # E% (%4 " /" $ $$((&" (%, %!' % C'D (% % $% ==, /=8 (' /=8 % %(- C%3D! # E% (L #)?=, # $ 2! ;'$?=, %%!' % ' % %$ + ==,?=, (' #?= ( ' =8 ( %&% & (+ #7 ( E% ( (% %%$ Table 7. Summary of P/ C and their types of Interrupt Processing (I - Mode) (+( %$ ( Table 7 (% $(%'%%$ ( $( ( +(- %'(%

23 C Microcontroller = +(& + (''% (% +'$ & # $ '% ( (& + ((% + % ((% ('$4 ' ( %( = ( #.,, / ( (% 3 &% + = &% + Figure 3 %% '3 $(- + = (''" $ Figure 4 %% ( + (% $(' #7 #7 2 # ( =.= ( ( (, -(%% = &% =.= = &% : =.= : = =: = ( =.= ( (, %'( *% #.,% (, 2 92,27,,,, Figure 3. Block Diagram of the 80 Microcontroller

24 , ;,,, =,,,, /,, /,,/, = 80 Microcontroller,,/ /,, 2, 92, #7,27, #7 =,,,/, /,,/ B /,,, 9 =, 9, ;, = Figure 4. Pin Out of the 80 Microcontroller = '%(%% + =( #. % + % % +'(%" % ( $(%'%%$ Port 0 (P0.0 - P0.7) (% (% $% (% + = # # (( ' $%(-%" ( (% %$ % - % #. - $%(-% (! &" ( '% (!$ $$%% $ $ % Port (P.0 - P.7), (% $$('$ #. (% = (%" $%(-$ %,","," " ( + (+'(- % E($ 7 ( +'(% %%(-$ +, (%L % & %$ %& + (+'(-! $('% 2!'(% =.= #%" (' %, $, ( % #. (% %! (% ($ ( Port 2 (P2.0 - P2.7),,(% = (% $% ' +'( % - % #." % (- & + $$%% % + $%(-% (! '$ & + / &% +! $ & =

25 Port 3, (% $% (% # $$(( +'((- % - % #." % (% ( +'(% 2' + % (% %" % (%$ ( Table 8 Bit Name Alternate Function, '( + (,, %( + (,, #7 2! #, #7 2! #, (. 2! #, (. 2! #,/ B 2! & B(, 2! & $ Table 8. Alternate Functions of Port 3 Pins = % % % $$(( (% (' (+'(- ==/= ( % % (% 4 Interrupt #7 #7 Location 8 8 ALE - Address Latch Enable #+, (% %$ ( (% $ % $ % $ & + $$%% % 92 (% %(- ' % $$%% (! -(% $(- +(% + + & '&' ' (% (% $", (% ( + $ ( $(- %'$ + + & '&'" $ %+ 3% ' INT0 (P3.2) and INT (P3.3) #7 $ #7! ( E% (% = 2' + % ( (% % C$(' (D '%%(- # (% '%" C$('D % (+ + % (% %%$" - ' ( ('& ' %'(+(' +(!$ '( ( '$ & (% '( (% $($ & '('( $%(- + = # $ ' ' -$ Table 9 %% '( ( '$ & - ' ( ' " (+ ( + % (% %%$ Table 9. Interrupt Service Routine locations (in Code Memory) for INT0 and INT +" (+ % (% %(- ( + % (% % ( E% (" % % (% ( ( %(' ( '$(( ' (%'( ( %(' ( (% '$ + % $$%% '(% #+ = (% E($ (+'! '% ( $ & %' + %(I% - / &%",% $, % %$ % $$%% $ $ (%, ( +'( % (!$ $$%%.$ % (- +(% + + & '&'", ( % $$%% & (- %'$ + + & '&', ( % ($('( $ %, ( %$ % $$%% & 92 $ % + 9 % ' $(' ' %$ $(! $$%% $ % %(-% Figure %% %' (' (%(- ==/= ' (+'$ =

26 , #7 B #7 B 8 ) 92, = $$%% '$(- 9-(' 80 CPU XR88C8 #% Figure. An Approach to Interfacing the XR88C8 DUART to the 80 Microcontroller '('(& %$ Figure $ +'( % +% $(- E%$ ( $(' E%% ( +, & %%(- (% '( #7 ( (% ( '% #7 ( (, - B (% % =, ( +((%!'(- (% ' (%'(" $ ( ' - ' ( %(' ( # '% + Figure " %(' H% #7 ( (% ($ #7 ( + " -((- + ( %(' ( ( '$ ( 8 ( '$ & =, $% (%% # '3$- %(- '3 # ( M% -( '%%(- - H% ( %(' ( ', % (($ '%% + ( E%" H% #7 ( ( -$ - C (- D $, ( + ( %(' ( $ % ( C A Microprocessor == (''%% (% + ( %( + # '%%% # -" ( (% =( (''%% E(% A;" ;" $ A; %(% $$((&" (% (''%% E(% ' (%" ( $ ' C'D, $ &('&" % $('% $ = '3 0 $ == &% = /

27 '3 0 (% %%( + '$(((- $ -(- '%%& ((- %' + ==," +! '&% == &% (% %%( + ++(- ($('( *% $$((&" %(' ==, $(' $% $('& ($ ' % %(-%" == (' (% %%( + %(- %(-(- (+(" + == $('" ( +(- *% %(-%L ( $ ''%% & $ ( $('% #7 # '3$- 2 & $ 2B & B( # #, $ #B, B( Figure %% %' (' + ==, $ 07 A; ; A; 8080A CPU 89 #7 #72 B *#7 89 7:,8# 9 G#7 2#7 A; A; Clock Generator B# 2G 22 G7 *2 / 07 A; 8228 System / Controller #7 2 2B *27 # #B Figure. Schematic of 8080A CPU Module 8080A CPU Module Interrupt Structure C# 'D + ==, (% $%'($ ==, $(' '%(%% + %(-%4 #72 $ #7 $$((&" == *(('( *% '%(%% + %(- %(-" #7 #72 (% '( (- # 2 " $ #7 (% '( (- # E% ( #+ C2 #D '$ % (3$" #72 ( C (- D ($('(- ==, ( ( E%% + ( % B #7 ( (% %%$ & ( $(' E%(- (", ( ' (% ' (%'( + '( + (% (%'(", $ ( %% #7 ( == *(('( *% ( & --(- #7 CD #7 (% '( C# '3$-D %(-, $ % (

28 $ ((( '%% + ( %('(- ==, $ & %% C!D '$( '%%(- 8'" #7 (% %%$", $ (% ((- C'D (+( % # '% + ==, $" (% C'D (+( (% &('& '$ (%'(% ==, %% (- $(++ (%'(% - % (%'(% & '% %'(+(' '(% ( (,H% & %'" ( ( %(' (!(%% Table 0 %% (% + % 2 (%'(%" '$%" $ '%$(- 2 $$%% Op-Code (hex) Mnemonic Restart Address (hex) = = 2 2 = / = Table A and 808 CPU Restart Instructions Used With Vectored Interrupts +" ', '(% '$ + + % 2 (%'(%" ( ( -(!'(- (% (%'( & $(-,- ( ( C% $$%%D +$%" - ' ( ' $ C% $$%%D '( 2!4 #+ '$ C2 / D (% $$ *% $(- #7 '&'" (% '$ '%$% ( C D '$ $", ( $ / (,- $ - ' ( ' '( ( & % Table 0 Interfacing the 8080 CPU Module to the XR88C8 DUART for Interrupt Processing ==, ' ''$ ==/= $ ( # ( $ Figure 7 %% ' ' ($ (+'(- ==/= ==, + C!D '$ ( '%%(- Please note that (- = only includes information pertaining to DUART interrupt servicing. '('(& %' % = '3 0" $$%% *%" ' ($ + %' (' # (% %' ('" # (' ( (% '$ / ( & $$((&" % '+(-$ ( #$ +'( $%'(( + (% '('( (% %$ ==/= ( E% ( ==," & --(- (% #7 CD (% %(- (% ($ $ ($ '( (- #7 ( +, ' ==, % '$ (% ' (%'(" ( ( %% '( #7 %(- + == *(('( *% ( (% (" #7 %(- + $ #7 %(- + == ' -(' CD #7 $ #7 %(-% $ ( - 8'" #7 $ #7 -(' CD" + - ( % -(' CD" $ & %%( (% + 79 *% ++ (% C(-D + #7 $ #7 %(-% (% %$ (% & ( $(' E%(- ( (% '(% %(' -" %%( %%$ #7 %(- ' 2 (% + %%$" $" ($ ( + (% $(' ( + (% $('" $ (% + == $(' Please note that, in this example, the value E7 is hard-wired into the input of U3 (% (% '$ + C D '$ 8'" ' (% $ (% -$ (, $" ( $ %", ( $ / ( (%,- $ ' - ' '( # (' ( +!(%% (% '( ( & =

29 U ;'' U4 #72 #7 / #7 ; '' *#7 8080A CPU / U Bi-Directional BUS Driver U3 2 / 2 # # # # # # #/ # 79 XR88C8 DUART #7 Figure 7. Circuit Schematic depicting approach to Interface the XR88C8 DUART to the 8080A CPU, for External Vectored Interrupt Processing (Interrupt Service Routine resides at 0020 in Memory) (' ==, ' % = $(++ (%'(%" ( ' % = $(++ ($( ( $('% (% ' ' ($ & ('(- ' " %$ ( Figure 7" $ & $((- '$% + ' + 2 (%'(% (% + *++% % Table 0 % *++% % $ $ & $(- #7 '&'" $ & ( %%'($ ( E%$ ( %(' C Microprocessor ==, (% & # (''%%" - ( (% $'$ ==, + $'% $ ( %(( + == == ('$ '((- '3 0 +'(% + =, ' (" $$(- %3 ( E%" $$(- C$('D ( E% ( (%" $ $$(- % + + ( ((& == %( E(% % - -(' ( $ $' *% %(-% (" #" #B" 2" 2B " ( $ (((I ( '" == '(% (!$ $$%%. *% '(+('&" = (% + $$%% *% % (% ( = ( *% 8'" 9 =( ' (% $$ ( $ $(! $$%% $ %%

30 Figure 8 %% %' (' + ==, $ / / ), / #7 / ) ) ) ) /) ) / #7 92 = 74LS373 =) = #. B = # 2 #B 2B 808 CPU Figure 8. A Schematic of the 808 CPU Module Figure 9 (%% ' (+'(- ==/= ==, $ 7 ==/= " ( (% '%" (% & $ -" %(-% 2 $ 2B +, $ ''$ $ B (% + 8" % '$ M% % %(& ''$ ==/= $(', $H% #. -" %(- # $ #B +, $ ''$ $ B (% + " %'(&

31 = 92, / #7 #7 ) =) 74LS373 = Address Decoder = B #. B 2 2B XR88C8 82 # 808 CPU Figure 9. Schematic of the XR88C8 Interface to the 808 CPU Module (Memory Mapped). H% #7 ( % $(& ($ + Figure 9" '% (% % ( $$%%$ ( Figure 0 $ Figure 808 CPU Module Interrupt Structure ==, %% (' $ C2!D ;'$ # '%%(- == % %3 ( E% (% " /" " $ #7" $ %3 ( E% (, B $(%'%%(- (+'(- + ( %('(- + ( $('% %' % " & ''$ ( %3 ( E% (% + + %3 ( E% (%L + % (% % C(' #D '%%(- ((- ( E% %% C2! ;'$ #D '%%(- Table (%% % # E% (% $ ( ' '(%('%.+%

32 Input Name Trigger Priority Type Acknowledge Address (Hex) Signal?,%(( 2$- (--$ (' 7 / 8(- 9 ( $ (' 7 8(- 9 ( $ (' 7 #7 8(- 9 ( $ 2! ;'$ #7 J C9D Table 0 Table. 808 CPU Maskable Interrupt Request Inputs and their Features Direct Interrupts ==, (% " /" $ C(' #D E% (% '(+('&" (+ & + % (% %%$" - ' +, (%" '( + ' (%'(" ('& $$ ( & '( $($ & '('(& ( ( == $('" $ ' % - ' '( % C('D (% $ ($ ( $(' ( & % + C# '3$-D 8'" ''$(- Table " (+ ( %%$" C / D $ $$ ( - ' +," $ - ' $ ' '( ( & % (% %%( (% '' ( %(' ( -(% '( ( & ==, ++% ( (((I(" ( ( % + %3 #% (% ((& (% +'$ Table # % $ $ % ((& % & & C$(-D ( E% ' (' ( % C+ ED $ (% (- %('$ &," (% (((I( %' - (% (' ( %E&" ( (% %%( ( E% '$ C(D ( %(' ( + (- ((& ( E% +" % % -$ -(% (% ( (%. +( Table % ($('% ==, ( % C!D '$ (% $ '$% %$ (! '$ ( '%%(- ($(' %$ + ==, % Section C...2 Figure 0 $ Figure % $(++ ' % ' %$ (+' ==/= ==, Figure 0 %% %' (' ( E% C('D / # ==, # (% '%" # (' ( + % -( / ( %&% & (% (% & %( (+' ' (E" '% (% C# '3$-D %(- $ (+'

33 ; '' / #7 ) 92 74LS373 = $$%% '$(- 9-(' #. B # 2 #B B 808 CPU 2B XR88C8 Figure 0. The XR88C8/808 CPU Interface for Direct Interrupt Processing (Interrupt Service Routine is located at 0034 in System Memory) Figure %% %' (' ( E% C2!;'$D # ==, # (% '%" # (' ( + % -( / ( %&% &

34 ;'' U #7 #7 / ;'' #7 U4 808 CPU 2 2 / / / # # # # # # #/ # XR88C8 92 / = 74LS373 ) ) ) ) ) /) ) =) SN74LS244 / Figure. The XR88C8/808 CPU Interface for Vectored Interrupt Processing (Interrupt Service Routine is located at 0020 in system memory) C...4 8HC Microcontroller +'% +(& + (''%" +$ % /=8 (''% (% +(& + (''% ++% % + +(- ((%4 ( '(,,% 2,.

35 Figure 2 %% '3 $(- + /=8 * #) #) 22 $ %'( '3 9-(' # 9-(' / *&%, ;8 ( &% *% 2!%( $$%% $$%%. ;9,# #. $ 8$% 3, #. P : # # =,, *,,, 2 Figure 2. Block Diagram of the MC8HC Microcontroller /=8 ' '+(-$ ( C(- (D $ ( C2!$$ (!$ *%D $ #+ $(' (% '+(-$ ( C(- (D $" ( /: &% + $$%% %' (% ( # Please note that this does not mean that there is 4K bytes of memory, or other addressable portions within the device /=8 '+(-$ + C(- (D $ ( ' $$%% & '%! +" (+ % $%($ (+' (% " % ( C2!$$(!$D $ /=8 (% '+(-$ ( 2!$$ (!$ $ & &(- $ * ( ;''" $ %(- $(' /=8 '%(%% + $(++ (+'( % 2' + % % (+& $(%'%%$ Port A, '%(%% + ( (%" (% $ ($('( ( (% (% %$ % ( &% + ( (% ' %$ +,%

36 '' + ( (% % ( ' +'(%L $ + + (% % ' +'(% Port B, * '%(%% + = (% #+ /=8 (% (- ( %(- ' ( $" (% +'(% % - % 8" (+ /=8 (% (- (!$$(!$ $" (% ( +'( % $$%% & + &.( $(' (+'(- = Port C, '%(%% + = ($('( (% B /=8 (% (- ( %(-' ( $" (% +'(% % - % ($('( 8" (+ /=8 (% (- (!$$(!$ $ (% ( +'( % (!$ $$%%.$ % '(+('&" $(- +(% + + & '&'" (% ( +'( % $$%% &, * (% $$%% & + $$%%(- & $('% $ ( '% (- %'$ + + & '&'" (% ( +'( % ($('( $ % (% ' $(!$ ( % + $$%% ( $ 9 ' $(' Port D, '%(%% + = ($('( (% 8" (% ' '+(-$ % ' ( (,( #+',#" $ ( ('(% #+' # Port E, 2 '%(%% + ( = (% $$(- '3-(- ( (% ' '+(-$ +'( % - % ( % (% ' (. ' % (% ( + (+'(- ==/= $(' + % (% $(%'%%$ IRQ (% (% C%3D ( E% ( #+ (% ( (% %%$ -" --$ CD" /=8 ( ' - ' " ( %&% & ' ( % (% %%( + (%(- ( ( %(' ( %($% (% '( ( & AS/STRA C$$%% D ' %$ $(! $$%%.$ % +, (% ( (% -(' C (- D $(- +(% + + & '&'L $ -(' CD $(- %'$ + + & '&' #+ /=8 (% ($$ (!$$(!$ $ $ (+' / &% + $$%% & %'",% * $ E($ % % ( Figure 3 Figure 3 % (%% ==/= '$ ''$ /=8 + ( $( ( #+ E%% (" (% '( #7 ( ( %%$ -- " (' (" ( " '% #) ( +, %%$ B (% ''% ( '(!'(- (% ' (%'( + '( + (% (%'(" - ' ( % (+ '( " ( %&% & % (% %%( (% H% ( %(' ( %($% (% '( ( & ( (%% ( '3$- %(- #%$" ( M% '%%% - ( %(' ( ' % (($ '%% + H% ( E%" #7 ( ( -$ $ ( + # (' ( $ % '%%(- ( % $ ($ Figure 3 --(' '('(& E($ - B" " $ 22 %(-% + " +.B" 22" $ 2 ''3 %$ ( Figure 2 (% '('(& % % ('$$ ( Figure 4 /

37 ; #% 2 *.B = $$%% '$ B #) #7 0 ) 74HC373 8HC XR88C8 Figure 3. XR88C8/MC8HC Microcontroller Interfacing Approach

38 .B B 2 '' Figure 4. Glue Logic Circuitry Required to Interface the MC8HC C to the XR88C8 DUART C... Z-80 CPU?=, ' (+'$ (- ( #$" (+ (, (% (- ( # $% 8" + %3 + C'%% '((&D" $(% %%'($ (?=, ( %$ ( Section C..2. C..2 Z-Mode Interrupt Servicing ( ( #$ +(- $ % + # % % (3 C?$D '$ % Table 3" ( $ '$ (?$ # -", (+'(- (- (?$ ( +'( % +% $(- ( %('(- #+ E%% ( %('(- +," ( ( %% #7 ( -" -- CD ', % $'$ ( E%" ( ( (%% #: # '3$- %(- '3 B, %$% #: %(- ( (% (+(- (% ( E% (% %$ B % '($ $'$ #: %(-" ( (" ( %%" ' '% + # ;' -(% #; *%, ( $ (% C( 'D (+(L $ $( +(- (-% %$ C( 'D (+( %' + ( E% -" (' ( $% %(' ( '( + ( %(' ( +$%" -' ( ' $ '( + ( %(' ( ' '(%(' +?$ ( (% ( % % (((I ( E%% + % ( $('%" ( $ % 9 % %% % $('%L $ ' + % $('% '+(-$ (?$ % '$ (((I ( E% + ' + % $('% & ''(- % $('% ( C$(%&' (D ( % %$ ( Figure =

39 ; #7 #7 #7 #7 #7 CPU ; #2# #2 #2# #2 #2# #2 #2# #2 #: #: #: #: #: 8#082,##G 9B2 Figure. A Diagram of Numerous DUARTs Configured in an Interrupt Daisy Chain (for Z-Mode Operation) # $$(( #7 $ #: (%"?$ % %% #2# $ #2 (%L (' $+($ % +%4 IEI - Interrupt Enable Input (% '( (- ( (% & ( (+ (% '+(-$ (?$ #+ (% ( (% -(' C (- D %3$ ( E%%" + (% " $ Note: Those interrupts which have been masked out by the IMR are still disabled. However, if this input is at a logic low, then all interrupts (whether masked or unmasked) are disabled. Hence, IEI can act to globally disable all DUART interrupt requests. IEO - Interrupt Enable Output (% '( (- (% & ( (+ (% '+(-$ (?$ (% (% + (% ''$ #2# ( + ((& $(' (% (% C (- D (+ + +(- '$((% $('H% #2# ( (% -(' C (- D $(' (% E%(- ( +, (" E%$ & $('" % M% %('$ #+ & + % '$((% +%" #2 ( ( -(' CD Note: Once the IEO pin has toggled low, and the CPU has acknowledged the interrupt request and has completed the interrupt service routine, the IEO pin will remain low until the user invokes the RESET IUS command (see Table 3). Therefore, if the DUART is going to operate in the Z-Mode, the user must include the RESET IUS Command at the very end of the DUART interrupt service routine. System Level Application of the IEI and IEO pins Figure $('% %(% + % ''$ ( $(%&' ( +% ( # (% +(-" +% % (- % ( ((& (% (% '% (% H% #2# ( (% $($ ;'' +" %3$ ( E%%" + (% &% $ $('" '$ M% (- + C (- % ( ((&D $(' (% + ( ((& (% (% '% #2# ( + (% ((& $(' (% ''$ #2 + (- % ((& B C (- % ((&D $(' E%% (" (% #2 ( -- CD (% ( ( " $(% C ((&D $('

40 + (%%(- & ( E%%, (% C ((&D ( (($ + (%%(- (% ( #2 ( + C (- % ((&D % --$ C (- D +(-" ' -(" Figure " + (- $(' (%" (% ( ((& (- % % %( ((& '% (% C( E%D '((& ' $(%$ & '(% + & + % + Figure %% ((- $(- $('(- %E' + % ( '' $(- $ +(- # E% + #7 #: 9 7 ;9# ;2 9 #2# #2 % # $ Figure. Timing Diagram Illustrating the Sequence of Events Occurring Between the DUART and the CPU During an Interrupt Request/Acknowledge and Servicing Additional Things to Note About Z-Mode Operation?$ ( (% %$ &?(-,( '%?(-,( '% # ;' -(%" # '3$- #: (" #2# (" $ #2 +" Figure '$ %(& ('$$ % ( '%" ( $$(( ( ( + % % ($ ("?$ ( (% '$$ (+ (% (+'$ +(- '%%%?= (''%% # $ === ==/, ==/ ==/, Please note that it is possible to interface the 80X8 Family of microprocessors to an I-Mode DUART, however, additional components and design complexity would be required in order to accomplish this ' (E.' % (+'(-?$ % (''%%% (% %$ ( $(" ( +(- %'(% C..2. Z-80 Microprocessor?=, '%(%% + = ( *%" / ( $$%% *% $ % ' (%?=, (% & +!( '%% (' ' '& (+' (?$ #$ $(' (% (% '%

41 ?=, ' '+(-$ ( + $(++ C( $%D?= (% % ( ( %% '('$ (+' % +,. % (%& ($ '% (% $$%% $ $ % (!$ Figure 7 %% %' (' + ( +?=, = = / /,8# / = / ; Z80 CPU 07 = 8 / 22 #7 / *) 7# B# 89 = *: 2) B #) Figure 7. Pin Out of the Z80 CPU Device?=, ( % $.B( (% & $ #.?= $% E( % $$(( - -(' ( $ (+' $('& & $ ( $('% (%'"?=, $(' $% ' ( ' % %(-%4 2 & $" 2B & B(" # #., $" #B #., B( #:.#7 # '3$- (% 2' + % +'(% ' $($ + " B" #)" 2) $ (% Figure 8 %% %' (' +?=, $" (' % % ' '!' ' % %(-% + %, ' (%

42 07 A; '3 (,8# #7 7# B# *) 89 8 *: B 2) #) 2B 2 #B # #7 22 Figure 8. Schematic of Z-80 CPU Module Z-80 CPU Interrupt Servicing Capability?=, '(% ( E% (%4 7# $ #7 7# (% C7%3D ( E% ( (L $ #7 (% C%3D ( E% ( ( %3 + (+'(- " & ''$ ( #7 (?=, ' '+(-$ ( + $(++ ( $%4 2! ;'$ (' C,( D ;'$ 2' + % ( $% % #7 ( +?=, $ ( $(%'%%$ ( +(- %'(% External Vectored Interrupt Processing (Interrupt Mode 0)?=, ( ( (% ( $ (+ C# D (%'( %!'$ B #7 ( (% %%$ & ( $(' E%(- (", ( ' (% ' (%'( + '( + (% (%'(", $ ( %% #7 -- CD #7 (% '( C# '3$-D %(-, $ % ( $ ((( '%% + ( %('(- B?=, % ( # $ " ( (%

43 ((- C' (+(D *%" +(- %%( + #7 # (% '% + (% ( $" (% C'D (+( (% '$ (%'(%?=, %% (- $(++ (%'(% =8 % (%'(% & '% %'(+(' '(% ( (,H% & %'" ( # %(' ( %($% Table 2 %% (% + % 2 (%'(%" '$% $ '%$(- 2 $$%%% Op-Code (hex) Mnemonic Restart Address (hex) = = = = =8 = 8 =8 = Table 2. Z-80 CPU Restart Instructions Used with Vectored Interrupts +" ', '(% '$ + + % 2 (%'(%" ( ( -(!'(- (% (%'( & $(-,- ( ( C%D $$%% +$%" - ' ( ' $ C% $$%%D '( 2!4 #+ '$ 2 / (% $$ *% $(- #7 '&'" (% '$ '%$% ( 8 (%'( $", ( $ / ( - ' $ - ' ( ' '( ( & % Table 2 % (% %%( + (%(- ( %(' ( -(% (% '( ( &! + '('( (I(- (% + + ( '%%(-" ( (+'(- " (% %$ ( Section C...2 (% %'( $(%'%%% (+'(- ==, $ (%!' % ' '$ %$ (?=," ($ (% (- ( #$ $?= (% (- ( # $ Direct Interrupt Processing (Interrupt Mode )?=, ( ( (% ( $ (+ C# D (%'( %!'$ B #7 ( (% %%$ & ( $(' E%(- (", ( ' (% ' (%'( +$%" - ' ( ('& $$ ( & '( $($ & '('( $%(- +?=, $(' $ - ' ( ' $ '( ( %&% & # (% '%" - ' $ ' = / ( & % (% %%( + (%(- ( ( %(' ( (% (' '( ( &?=, $ $% ($ ( $(' ( & % + C# '3$-D, M% '%%% - # (' (" ((% '%% + ( E% $ % ( Peripheral Vectored Interrupt Processing (Interrupt Mode 2)?=, ( ( (% ( $ (+ C# D (%'( %!'$ (% ( C$D (% & %+ (+ % (% % '' ( E% % + % ( % #7 ( +?=, (% ( $ % ((- $(' ($(+& (%+ '( (" M% ( ( %('(- B #7 ( (% %%$ & ( $(' E%(- (", ( '( ' (% ' (%'( ' (% ' (%'( (% '$", $ ( %% #7 %(- (+ ( $(' ( %(' (% -( ' ((- ( $(' % $'$ #7 %" ( ( ' C( 'D *% (% ( ' ( $ &, $, ( ' - ' '( +$ & ( ' Please note that if the IEI input to the DUART (or Zilog peripheral device) is low then the DUART (or Zilog peripheral device) will be disabled from generating any interrupt requests to the CPU! + (% ' (% %$ Figure 9 # (% '% ==/= (% '+(-$ (?$ $ (% (+'$?=, B E(% ( %('(-" ( ( %% (%

44 #7 (% '( (" ( " '% #7 ( +, %%$ ', % '$ (% ' (%'(", $ ( %% #7 %(- (% ( ( %% #: # '3$- ( % + %%$ #: %(- (% (+ &! '&' ( C#:D C# '3$-D '&' " ( %% #: %(-" ( ' '% + # ;' -(% #; *% (% $ ( $ &," $ - ' ( ' $ ( ( %(' ( # '% +?=," (% '( (% / ( $$%% (' (% $($ + Table 3 Most Significant Byte Least Significant Byte Bit Bit 4 Bit 3 Bit 2 Bit Bit 0 Bit 9 Bit 8 Bit 7 Bit Bit Bit 4 Bit 3 Bit 2 Bit Bit 0 % + # -(% ( (, % (-(+(' *(% ( ( # ;' -(% + Note: The LSB of the IVR is always set to 0 once read by the CPU. Interrupt Service Routines must begin at even ddresses. Table 3. The Relationship between the Contents of the Interrupt Vector Register (of the DUART) and the location of the Interrupt Service Routine (Z-80 CPU) $$((&" % % + '%.% $% ( # -(% +," $(- ( $$%% '$ ('(& + ;'' (- ((& ( ((& ( #2# #2 #7 #7 B 2) 2B 2 B Z80 CPU #) #7 #: XR88C8 Figure 9. Schematic of an Approach to Interface the DUART to the Z-80 CPU (for Z-Mode Operation)

45 C Microprocessor ==/ (''%% (% / ( (''%% +'$ & # ( Figure 20 %% ( $(- + (% # Please note that in (-, pins 24-3 have some additional labels, located off to the right of the package. These additional labels will be explained later in this text. 07 ; = /.. / =. /./ *82. = = 7. / 808 CPU ).0 ) : B =.#. / 27 / ) 92 7# ) #7 #7 = 2 9: 2G Figure 20. Pin Out of the 808 Microprocessor Device # - - % 3 ( ' + (% # & (!(- +'(% + & + % (% (% $(' '%(%% + / ( *% $ ( $$%% *% *% (% (!$ ( / $$%% *(% + $$%% *(% / (!$ ( %% (% / + /."." =. $./ + % (% $$%% (% $(- +(% + + & '&' 8" $(- %'$ + + & '&'" % (% 3 ( +'(%

46 -" '% " /../ '% / %'$ - + (!$ (% (% '$ & 7. ( ( B (% ( (% (- " C(D $ (% %'$ $ (% - 3 ' $+(((% % $ 7. J ' ( Table 4 B ==/, % ( (% $" ( %% ' % & %(( + ==," $ E(% & $$%% ' $ ''3 - +, $ Pin Number MN/MX = (Min Mode) MN/MX = 0 (Max Mode) 89 ).0 89 ).0 / B 9:.# = ) #7 ) Table 4. MN/MX Mode and Function of Pins 24-3 of 808 CPU Device. B 7. (% " ==/, (% (- ( C!D $ (% $ (% ($$ + '! ('(% ( (' ==/, E(% % + == (' $ '%% 7, # (% $" %'( % ' === (% E($ - & $ #. ' % %(-% ==/, '(% ( E% (%4 #7 $ 7# 7# (% '( (- C%3D ( E% (L $ #7 (% C%3D ( E% ( #+ ==/, (% (- ( C(D $" #7 # '3$- ( (% (,( % Figure 20 8" (+ ==/, (% (- ( C!D $" #7 %(- % $($ + " " $ (% ( === % ' Table %% '%% %% $ === '( % %$ " " $ C!D $ %% %(-% S2 S S0 Processor State 8288 Active Output # '3$- #7 $ #., # B( #., #B 8 7 $ ''%% $ & B( & B,%%( 7 Table. 808 Processor State/8288 Bus Controller Active Output as a function of S0, S and S2 /

47 Figure 2 $ Figure 22 % ==/, $" (- ( C(D $ C!D $%" %'(& #7 #7 ) C 74LS373 = = ) C 74LS373 = 27. #.# 2 ;'' CPU B #B 2B Figure 2. Schematic of the 808 CPU Mode (Min Mode)

48 9: 9: 27. B # #B #7 2 2B # #B # Bus Controller ) 74LS373 = = ) = CPU 74LS373 Figure 22. Schematic of the 808 CPU Mode (Max Mode) 808 C Interrupt Processing #+ ( ' E(% ( %(' +," ( ( %%,H% #7 ( & --(- ( (- ', % '$ (% ' (%'(" ( ( %% #7 ( (+ (- ( C(D $ % " " $ (% CD % Table # ( '%" #: ( + ( ( %%$ ' (% %" ((- ( (%!'$ ' C( 'D & + $ % ==/, ( $ (% $ $ (& (% & ( $ $( '( + ( %(' ( ( & (' (% C( 'D (% = (% ($" ==/, ' ''$ / $(++ ( '% $$((&" %(' ' ' (% (($ & CD" % (%!'$ % +(% : & + & + # (' (%.@ Figure 23 %% %' (' + ==/= (+'(- C(D $ ==/, $(' Please note that the DUART has been configured to operate in the Z-Mode. Therefore, the user must account for the IEI input to the DUART device =

49 74LS373 D Q C = = 89 74LS373 D Q = $$%% '$ 92 C 27. #7 #7.# + (- ((& $(' #: #7 #2# ; '' 7. B 2 2B B 808 CPU XR88C8 Figure 23. Schematic of the XR88C8 DUART Device Interfacing to a Min Mode 808 CPU Device D. TIMING CONTROL BLOCK ((- *'3 % % %'(+& ( %.% (% % %( $ '( $ ' ' ((- *'3 '%(%% + +(- %4 %'( ('( *( 0 / (.( 2! #,(% ''3 %(% $ '(%" $('& '3 ' -(%% 4 % Figure 24 %% '3 $(- + ((- '3 + ==/= $('

50 #, #,,% -(%% " 9 4! * #, N/O (($ & /. ( 4! (($ & / 4!*.9: %'( ('( *( 0 #, * #, * 4!* NO Figure 24. Block Diagram of DUART Timing Control Block 2' + ((- *'3 (% $(%'%%$ 4 D. Oscillator Circuit: '&% %'( (% &('& ''$!& '%%.9: $ (% %'( ('( ( ( ' ( +'(% % $ + % '&% %'(" $ ++% %(- %'((- %(-" + % & *( 0" $.( '&% 9 %(- +E'& + 8I $ 8I (% E($ + ( + 8" '&% 9 %(- +E'& + /=/ 8I (% E($ + -( + %$$ ( % & *( 0 Table 8 Figure 2 %% '$$ %' (' + 9 %'( '('(&

51 4 A & Q 4 A & Q 4 4 XR88C8 /=/8I, % &% Figure 2. A Recommended Schematic for the XTAL Oscillator Circuitry Note: The user also has an option to drive the Oscillator Circuit with a TTL input signal, in lieu of using a crystal oscillator. If this approach is used, the TTL must be driven into the X/CLK pin, and the X2 pin must be left floating. #+ % $%(% % % + %(- '&% %'(" Figure 2 %% ' $ '%%& '('(& ''(% (% M'( XR88C8 G /=8I 8 (% + % Figure 2. A Recommended Schematic to Drive Multiple DUARTs From the Same Crystal Oscillator. Note: The user is urged not to use the 74LS4 Schmitt Trigger Inverter in lieu of the 74HC4 device. The input of the 74LS4 tends to load down the oscillating signal from the DUART, to the point that the Schmitt Trigger inverter can no longer change state or respond to the oscillator signal.

52 D.2 Bit Rate Generator *0 *( 0 ''% ((- + %'( ('( $ - ''3 %(- + '& %$ $ '('( ( % -(- + % 3% Please note that the BRG will only generate these standard bit rates if the Oscillator Circuit is running at 3.84 MHz $$((&" ' ''3 +E'(% + *0 / (% % % % ' %' + $(++ %% + ( %" -$ + *0 (% %'( (% $ & %(- '(- NO (%(- + % %% + *( %" + *0" (% %$ ( $(%'%%( + '3 ' -(%% % ( Section D. '3 $(- + *0 '('(& (% %$ ( Figure 27 N4O 4 N4O NO 4.9: %'( ('( *( 0 % $ * *N4O 4 * *N4O 4 * Figure 27. Block Diagram of the Bit Rate Generator portion of the Timing Control Block

53 D.3 Counter/Timer ((- *'3 % '(% / (.(.. (% - / ( $' (' ' % + % ((- %'% % (% ( Figure 28 %% '3 $(- + '('(& %$(-. %'( + % ((- %'% +.( ' $ & ((- ( $ N/4O!((& -(% (% / -,% % Table + (% (.( $" ((- ' $ N/4O. (% ( '3 ' -(%% + % % - ( - + %(% $ '(% %'( ('(,% -(%% " 9 (($ & / 4 % #, * (($ & /.(. G, N/O Figure 28. A Block Diagram of the Circuitry Associated with the Counter/Timer Bit Bit Bit 4 C/T Mode Timing Source 2! # #, '3 + %( * '3 + * %(.9: # (($$ & / ( 2! # #, ( 2! # #," (($$ & / (.9: # (.9: # (($$ & / Table. ACR[:4] Bit Field Definition - C/T

54 D.3. Timer Mode: Please note that of the two C/T Modes, the Timer Mode is the only mode which is relevant to the function of Bit Rate Selection. 8" + '%%" $ (% % $(%'%%$ # ( $". '% % - $(($ $ -% %E % ($ (% (' ( ''3 ($% + '% +.( -(%%" $ 9. ' %$ % - ( - ( $ $' / ''3 + & ( ($$ & *0 %E" (-((- +. (%, (", #+. (% -$ ( ( $" +E'& + %(-. %E '!%%$ % +%4. E'& J E'& + '$ ((- ' RNOR = + N9O B 4 NO J '% + -(% ( $'( + NO J '% + 9 -(% ( $'( + ('. (% $$ % / ''3 %(- & '('(&" %(- ( (%./ +E'& +. %(- +" ( " $($ +. '!%%$ % +%4 *( J E'& + '$ ((- ' RNOR = + N9O '% + $ 9 -(%% & ' -$ & (" ( & -( 3 ++'! + '&' + %E. -(% ( %(- % (.9 '( + $$%%(-- C 72D '$ Table. % '(%& %%E C 72D '$ '%%. ( ' ((- '&' $ -( ((- '&' %(- ' % %$ ( $ G %% (" ( # % -(% #NO" (% % ' ' '&' + %E (% % % +. % ($(' ( -" (+ '$(( (% -$ - ( ( ( %3 -(% # #NO ' '$ & (%%(- $$%%(--$ C, 72D '$ Table # #2 $" " '$ $% '& %. D.3.2 COUNTER MODE # $". '% $ + %% ( (.9" -((- '( + C 72D '$ 72.2G %% ( #NO (% % ' (- ' + /. ( '( ' % / $ $+ (! ' (- / ( ( (% %$ &, ( C, 72D '$ #+, (% -$ +." ( ( (- ( ( ' (% ' $" (' ( -% # % (- % $ #NO (% '$. (% %$ ( C, 72D '$ C 72D '$ ( ' (% (- %% ' ( % (.9, & ' - '% + 9 & ( ' 3% ++' & + %%E 72 '$ #+ % -$ (% % %$ $ %$ +! '&' D.4 External Inputs % + % + #, (% #, #, %$ % $('! (% ((- *'3 % ((- %'% + %(% $ '(% + ' % Please note that the user can specify whether a clock signal, applied to one of these external inputs, is a X or a X clock signal; via the Clock Select Registers % Section D.. $($ $(%'%%( #, (% $ ( +'(" % % Section E D. Clock Select Registers, CSRA and CSRB # Figure 24" '3 ' -(%% 4 H% '3 ' -(%% % % ' %' (' ''3 %(-% ( $( %(% $ '(% + ' % % % %' $(++ %$$ ( % + *0".( " %! ( % ((- %' + %(%

55 $ '(% Table 7 $ Table 8 % (% ( '% + % $ ''3 %' $((- %(% $ '(% Bit 7 Bit Bit Bit 4 Bit 3 Bit 2 Bit Bit 0 '( '3 ' %( '3 ' Table 8 Table 8 Table 7. Bit Format of the Clock Select Registers, CSRA and CSRB Field Bit Rate CSR[7:4] ACR[7] = 0 ACR[7] = CSR[3:0] X=0 X= X=0 X= / / / : / : ==: ==: /: /: : : = = = = = = / / / / =: : : =: ( ( ( ( 2! / 2! / 2! / 2! / 2! 2! 2! 2! Note: the b suffix denotes a binary expression. x = don t care value. Table 8. Bit Format of the Clock Select Registers, CSR[3:0] and CSR[7:4] Please note that = calls for the user to specify the following parameters4 NO % %(-(+(' ( * +!( (& -(% 2!$ ( NO (% * +!((& -(%" $ ' %(& -$ & ((-!!!!!!!!!!!!!! " ( $ % '" %'(& X - The Select Extend bit 2' %( $ '(" ( ( %!$ ( ' % '$ & ((- ( $ ' H% $ -(% - (% (+( ' +$ ( Table 3 Table 9 %(I% % '$%" $ ( ++' 2!$ (%

56 Register Contents Resulting Action $ -(% " = /! *0 ' 2!$ *( J $ -(% " /! *0 ' 2!$ *( J $ -(% *" * /! *0 ' 2!$ *( J $ -(% *" * * /! *0 ' 2!$ *( J Table 9. Command Register Controls Over the Extend Bit Note: If the user programs either nibble of the Clock Select Register (CSRn[7:4] or CSRn[3:0]) with values ranging from 0 to C, then the user is using the BRG as a source for timing. However, these standard bit rates (presented in Table 8) apply only if the X/CLK pin is driven with a 3.84 MHz signal. If a signal with a different frequency (fo) is applied to the X/CLK pin, then the DUART channel is running at the following baud rate: Actual Baud Rate = N / *$ ;O R + /=/ 8I provided that fo is between 2.0 MHz and 4.0 MHz. Additionally, as in the case for standard baud rates, the actual frequency of the clock signal will be times these values. X vs X Clock Signals % C '3D $ C/ '3D ($ - (%! +" ( (% ( $(%'%% ( (- $ %(-(+('' C/ ''3D %% '($ %( $ & +' + / B % C ''3D & %% %(-% ' ( ($ (% % $ ''& ''$ - '''& ( % ' ($ ( % + / ''3 ( ( + ''3 +(- - % ( '(+& %% '( ( + ' % (% ''3$ & ' ((- %' + ((- *'3 #+ (% '( (% '( $ (% '((- $ + %( %(" %( (% % ''3$ & (% ' ((- %' 8'" (% - ''3 +E'& + '( (%!'& % % + %( (% (% ' '(%(' + %&' % %( $ '('( - '( $ %( -$ '( $ %( $!'& % $ " %++('( $(++'% ( +E'(% + ''3 %'% ' '( $ %( ' '( ( % ( '((- '%%" % %$ ( +(- $(%'%%( % %( $ %(%%( %&% % $('$ ( Figure 29 (% %&% '%(%% + %( " $ ' '( %( '3 '( '3 Figure 29. Example of a Serial Data Transmission System 9 % + %% '( (% ''3$ & %' (% %(- & +% + %(" $ '( (% & %(- %( $ ' ( ($ Figure 30 %% %% + (% /

57 Figure 30. Receiver (X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock Figure 30 % % % (% ( '(H% %(- ( $ ' %( $ ( (% ' -(- # (% '%" '( (% %(- ' %( $ (" ( $ ( ( ( ($" ( ' %''%%( $ ( (% (% 3 % '( $(+ #+ (% ''( + '( $(+" ( & % ( %(%%( $ '( + (% %( $" % $('$ ( Figure 3 '($ ' Figure 3. Illustration of an Error due to Receiver Drift Figure 3 % % '( %(- (- ( %(- + $ ( ( It is interesting to note that, in Figure 3, the Receiver sampled # % $ $ '( $(+ ' % (% ' '( (% % %( ''3