DATASHEET HI-506A, HI-507A, HI-508A, HI-509A. Features. Applications

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1 DATASHEET HI-506A, HI-507A, HI-508A, HI-509A 16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage rotection F3143 Rev.6.00 The HI-506A, HI-507A, HI-508A and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70V - levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents of resistance under this condition. These features make the HI-506A, HI-507A, HI-508A and HI-509A ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-506A is a single 16-channel multiplexer, the HI-507A is an 8-channel differential multiplexer, the HI-508A is a single 8-channel multiplexer and the HI-509A is a differential 4-channel multiplexer. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application ote A520. Features Analog Overvoltage V - o Channel Interaction During Overvoltage Maximum ower Supply V Fail Safe with ower Loss (o Latch-Up) Break-Before-Make Switching Analog Signal Range V Access Time ns ower Dissipation mW b-free Available (RoHS Compliant) Applications Data Acquisition Systems Industrial Controls Telemetry F3143 Rev.6.00 age 1 of 20

2 Ordering Information ART UMBER ART MARKIG TEM. RAGE ( C) ACKAGE KG. DWG. # HI1-0506A-2 HI1-506A-2-55 to Ld CERDI F28.6 HI1-0506A-5 HI1-506A-5 0 to Ld CERDI F28.6 HI1-0506A-8 HI1-506A-8-55 to Hour Burn-In 28 Ld CERDI F28.6 HI3-0506A-5 HI3-506A-5 0 to Ld DI E28.6 HI3-0506A-5Z (ote 1) HI3-506A-5Z 0 to Ld DI (ote 2) (b-free) E28.6 HI3-0507A-5 HI3-507A-5 0 to Ld DI E28.6 HI3-0507A-5Z (ote 1) HI3-507A-5Z 0 to Ld DI (ote 2) (b-free) E28.6 HI1-0508A-8 HI1-508A-8-55 to Hour Burn-In 16 Ld CERDI F16.3 HI3-0508A-5 HI3-508A-5 0 to Ld DI E16.3 HI3-0508A-5Z (ote 1) HI3-508A-5Z 0 to Ld DI (ote 2) (b-free) E16.3 HI1-0509A-2 HI1-509A-2-55 to Ld CERDI F16.3 HI1-0509A-5 HI1-509A-5 0 to Ld CERDI F16.3 HI1-0509A-8 HI1-509A-8-55 to Hour Burn-In 16 Ld CERDI F16.3 HI3-0509A-5 HI3-509A-5 0 to Ld DI E16.3 HI3-0509A-5Z (ote 1) HI3-509A-5Z 0 to Ld DI (ote 2) (b-free) E16.3 OTES: 1. These Intersil b-free plastic packaged products employ special b-free material sets; molding compounds/die attach materials and 100% matte tin plate LUS AEAL - e3 termination finish, which is RoHS compliant and compatible with both Snb and b-free soldering operations. Intersil b-free products are MSL classified at b-free peak reflow temperatures that meet or exceed the b-free requirements of IC/JEDEC J STD b-free DIs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. F3143 Rev.6.00 age 2 of 20

3 inouts HI-506A (CERDI, DI) TO VIEW HI-507A (DI) TO VIEW +V SULY V SULY 1 28 A C V SULY B V SULY C 3 26 I 8 C 3 26 I 8A I I 7 I 8B 4 25 I 7A I I 6 I 7B 5 24 I 6A I I 5 I 6B 6 23 I 5A I I 4 I 5B 7 22 I 4A I I 3 I 4B 8 21 I 3A I I 2 I 3B 9 20 I 2A I I 1 I 2B I 1A I EABLE I 1B EABLE GD ADDRESS A 0 GD ADDRESS A 0 V REF ADDRESS A 1 V REF ADDRESS A 1 ADDRESS A ADDRESS A 2 C ADDRESS A 2 HI-508A (CERDI, DI) TO VIEW HI-509A (CERDI, DI) TO VIEW A A 1 A A 1 EABLE 2 15 A 2 EABLE 2 15 GD -V SULY 3 14 GD -V SULY V SULY I V SULY I 1A 4 13 I 1B I I 5 I 2A 5 12 I 2B I I 6 I 3A 6 11 I 3B I I 7 I 4A 7 10 I 4B 8 9 I 8 A 8 9 B F3143 Rev.6.00 age 3 of 20

4 Truth Tables HI-506A A 3 A 2 A 1 A 0 E O CHAEL X X X X L one L L L L H 1 L L L H H 2 L L H L H 3 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 HI-508A A 2 A 1 A 0 E O CHAEL X X X L one L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 HI-509A A 1 A 0 E O CHAEL AIR X X L one L L H 1 L H H 2 H L H 3 H H H 4 HI-507A A 2 A 1 A 0 E O CHAEL AIR X X X L one L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 F3143 Rev.6.00 age 4 of 20

5 Functional Diagrams HI-506A HI-507A I 1 I 1A A I 2 I 16 DECODER/ DRIVER I 8A I 1B I 8B DECODER/ DRIVER B OVERVOLTAGE CLAM AD SIGAL ISOLATIO 5V REF LEVEL SHIFT DIGITAL IUT ROTECTIO V REF A 0 A 1 A 2 A 3 E OVERVOLTAGE CLAM AD SIGAL ISOLATIO 5V REF LEVEL SHIFT DIGITAL IUT ROTECTIO V REF A 0 A 1 A 2 E HI-508A HI-509A I 1 I 1A A I 2 I 8 DECODER/ DRIVER I 4A I 1B I 4B DECODER/ DRIVER B OVERVOLTAGE CLAM AD SIGAL ISOLATIO 5V REF LEVEL SHIFT DIGITAL IUT ROTECTIO A 0 A 1 A 2 E OVERVOLTAGE CLAM AD SIGAL ISOLATIO 5V REF LEVEL SHIFT DIGITAL IUT ROTECTIO A 0 A 1 E F3143 Rev.6.00 age 5 of 20

6 Schematic Diagrams ADDRESS IUT BUFFER AD LEVEL SHIFTER TTL REFERECE CIRCUIT V+ R10 V REF Q1 R9 Q4 D3 GD LEVEL SHIFTER V+ OVERVOLTAGE ROTECTIO D2 V+ R2 R3 R4 R5 R6 R7 R8 LEVEL SHIFTED ADDRESS TO DECODE R1 200 D1 V- GD V- ADD I ADDRESS DECODER V+ TO -CHAEL DEVICE OF THE SWITCH A 0 OR A 0 A 2 OR A 2 A 1 OR A 1 TO -CHAEL DEVICE OF THE SWITCH A 3 OR A 3 EABLE DELETE A 3 OR A 3 IUT FOR HI-507A, HI-508A, HI-509A DELETE A 2 OR A 2 IUT FOR HI-509A V- F3143 Rev.6.00 age 6 of 20

7 Schematic Diagrams (Continued) MULTILEX SWITCH FROM DECODE OVERVOLTAGE ROTECTIO V+ Q5 I R11 D6 D7 D4 D5 Q6 V- FROM DECODE F3143 Rev.6.00 age 7 of 20

8 Absolute Maximum Ratings V+ to V V V+ to GD V V- to GD V Digital Input Voltage (V E, V A ) (V-) -4V to (V+) +4V or 20mA, Whichever Occurs First Analog Signal (V I, V ) (V-) -20V to (V+) +20V Continuous Current, I or mA eak Current, I or, ulsed 1ms, 10% Duty Cycle (Max).. 40mA Operating Conditions Temperature Ranges HI-506A/507A/508A/509A-2, C to +125 C HI-506A/507A/508A/509A C to +75 C Thermal Information Thermal Resistance (Typical, ote 3) JA ( C/W) JC ( C/W) 28 Ld CERDI ackage Ld CERDI ackage Ld DI ackage /A 16 Ld DI ackage /A Maximum Junction Temperature CERDI ackages C DI ackages C Maximum Storage Temperature Range C to +150 C b-free reflow profile see link below CAUTIO: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. OTE: 3. JA is measured with the component mounted on an evaluation C board in free air. Electrical Specifications Supplies = +15V, -15V; V REF in = Open; V AH (Logic Level High) = 4V; V AL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. -2, -8-5 ARAMETER DYAMIC CHARACTERISTICS TEST CODITIOS TEM ( C) MI (ote 12) TY MAX (ote 12) MI (ote 12) TY MAX (ote 12) UITS Access Time, t A ote s Full s Break-Before-Make Delay, t OE ote ns Enable Delay (O), t O(E) ote ns Full ns Enable Delay (OFF), t OFF(E) ote ns Full ns Settling Time, t S HI-506A and HI-507A To 0.1% s To 0.01% s HI-508A and HI-509A To 0.1% s To 0.01% s Off Isolation ote db Channel Input Capacitance, C S(OFF) pf Channel Output Capacitance, C D(OFF) HI-506A pf HI-507A pf HI-508A pf HI-509A pf Digital Input Capacitance, C A pf Input to Output Capacitance, C DS(OFF) pf DIGITAL IUT CHARACTERISTICS Input Low Threshold, TTL Drive, V AL ote 4 Full V Input High Threshold, V AH (ote 11) ote 4 Full V F3143 Rev.6.00 age 8 of 20

9 Electrical Specifications Supplies = +15V, -15V; V REF in = Open; V AH (Logic Level High) = 4V; V AL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. (Continued) ARAMETER TEST CODITIOS TEM ( C) MI (ote 12) -2, -8-5 Input Leakage Current (High or Low), I A otes 4, 8 Full A MOS Drive, V AL, HI-506A/HI-507A V REF = +10V V MOS Drive, V AH, HI-506A/HI-507A V REF = +10V V AALOG CHAEL CHARACTERISTICS Analog Signal Range, V I ote 4 Full V On Resistance, r O otes 4, k Full k Off Input Leakage Current, I S(OFF) otes 4, na Full na Off Output Leakage Current, I D(OFF) otes 4, na HI-506A Full na HI-507A Full na HI-508A Full na HI-509A Full na I D(OFF) With Input Overvoltage Applied ote na Full A On Channel Leakage Current, I D(O) otes 4, na HI-506A Full na HI-507A Full na HI-508A Full na HI-509A Full na Differential Off Output Leakage Current, I DIFF, (HI-507A, HI-509A Only) Full na OWER SULY CHARACTERISTICS Current, I+ otes 4, 10 Full ma Current, I- otes 4, 10 Full ma ower Dissipation, D Full mw OTES: % tested for Dash 8. Leakage currents not tested at -55 C. 5. V = 10V, I = +100 A nA is the practical lower limit for high speed measurement in the production test environment. 7. Analog Overvoltage = 33V. 8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25 C. 9. V E = 0.8V, R L =, C L = 15pF, V S = 7V RMS, f = 100kHz. 10. V E, V A = 0V or 4V. 11. To drive from DTL/TTL Circuits, pull-up resistors to +5V supply are recommended. 12. arts are 100% tested at +25 C. Over-temperature limits established by characterization and are not production tested. TY MAX (ote 12) MI (ote 12) TY MAX (ote 12) UITS F3143 Rev.6.00 age 9 of 20

10 Test Circuits and Waveforms T A = +25 C, V SULY = 15V, V AH = 4V, V AL = 0.8V, V REF = Open, Unless Otherwise Specified 100 A V 2 I V I ro = V A FIGURE 1A. TEST CIRCUIT 1.4 O RESISTACE (k ) C +25 C -55 C ORMALIZED RESISTACE (REFERRED TO VALUE AT 15V) C TO +125 C V I = +5V AALOG IUT (V) SULY VOLTAGE ( V) FIGURE 1B. O RESISTACE vs AALOG IUT VOLTAGE FIGURE 1C. ORMALIZED O RESISTACE vs SULY VOLTAGE FIGURE 1. O RESISTACE 100nA 10nA LEAKAGE CURRET 1nA 100pA O LEAKAGE CURRET I D(O) OFF UT CURRET I D(OFF) OFF IUT LEAKAGE CURRET I S(OFF) ±10V E +0.8V A I D(OFF) ± 10V 10pA TEMERATURE ( C) FIGURE 2A. LEAKAGE CURRET vs TEMERATURE FIGURE 2B. I D(OFF) TEST CIRCUIT (OTE 13) F3143 Rev.6.00 age 10 of 20

11 Test Circuits and Waveforms T A = +25 C, V SULY = 15V, V AH = 4V, V AL = 0.8V, V REF = Open, Unless Otherwise Specified (Continued) A I S(OFF) E +0.8V A 0 A 1 E A I D(O) ±10V 10V ± ± 10V ±10V 4V FIGURE 2C. I S(OFF) TEST CIRCUIT (OTE 13) FIGURE 2D. I D(On) TEST CIRCUIT (OTE 13) OTE: 13. Two measurements per channel: ±10V and +10V. (Two measurements per device for I D(OFF) ±10V and +10V.) FIGURE 2. LEAKAGE CURRETS 7 AALOG IUT CURRET (ma) AALOG IUT CURRET (I I ) UT OFF LEAKAGE CURRET ID (OFF) UT OFF LEAKAGE CURRET (na) A I I A I D(OFF) V I AALOG IUT OVERVOLTAGE (±V) FIGURE 3A. AALOG IUT OVERVOLTAGE CHARACTERISTICS FIGURE 3. AALOG IUT OVERVOLTAGE CHARACTERISTICS FIGURE 3B. TEST CIRCUIT ±14 ±12-55 C +25 C SWITCH CURRET (ma) ±10 ±8 ±6 ± C V I A ± VOLTAGE ACROSS SWITCH ( V) FIGURE 4A. O CHAEL CURRET vs VOLTAGE FIGURE 4. O CHAEL CURRET FIGURE 4B. TEST CIRCUIT F3143 Rev.6.00 age 11 of 20

12 Test Circuits and Waveforms 8 T A = +25 C, V SULY = 15V, V AH = 4V, V AL = 0.8V, V REF = Open, Unless Otherwise Specified (Continued) A +15V/+10V +I SULY SULY CURRET (ma) V SULY = ±15V V SULY = ±10V 10k 100k 1M 10M TOGGLE FREQUECY (Hz) V A 50 +4V E GD V+ A 3 I 1 HI-506A A 2 I 2 THRU A 1 I 7/I 15 A 0 I 8/I 16 V- A -I SULY -15V/-10V ±10V/±5V 10V/ 5V M pf FIGURE 5A. SULY CURRET vs TOGGLE FREQUECY Similar connection for HI-507A/HI-508A/HI-509A FIGURE 5B. TEST CIRCUIT FIGURE 5. DYAMIC SULY CURRET V ACCESS TIME (ns) V REF = OE FOR LOGIC HIGH LEVEL 6V V REF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V LOGIC LEVEL (HIGH) (V) V A 50 +4V V REF V+ A 3 I 1 A 2 I 2 THRU I 7/I 15 A 1 HI-506A A 0 I 16 E GD V- -15V 10V 10V k pf FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) Similar connection for HI-507A/HI-580A/HI-509A FIGURE 6B. TEST CIRCUIT 1 /2 V AH V AH = 4.0V ADDRESS DRIVE (V A ) V A IUT 2V/DIV. S 1 O 0V +10V UT UT 5V/DIV. 10% -10V S 16 O t A 200ns/DIV. FIGURE 6C. MEASUREMET OITS FIGURE 6. ACCESS TIME FIGURE 6D. WAVEFORMS F3143 Rev.6.00 age 12 of 20

13 Test Circuits and Waveforms T A = +25 C, V SULY = 15V, V AH = 4V, V AL = 0.8V, V REF = Open, Unless Otherwise Specified (Continued) A 3 A 2 HI-506A I 1 +5V V AH = 4.0V I 2 THRU V A V A 1 I 7/I 15 A 0 I 8/I 16 E GD V 50pF 0V 50% 50% ADDRESS DRIVE (V A ) UT Similar connection for HI-507A/HI-508A/HI-509A FIGURE 7A. TEST CIRCUIT t OE FIGURE 7B. MEASUREMET OITS V A IUT 2V/DIV. S 1 O S 16 O UT 0.5V/DIV. 100ns/DIV. FIGURE 7C. WAVEFORMS FIGURE 7. BREAK-BEFORE-MAKE DELAY F3143 Rev.6.00 age 13 of 20

14 Test Circuits and Waveforms T A = +25 C, V SULY = 15V, V AH = 4V, V AL = 0.8V, V REF = Open, Unless Otherwise Specified (Continued) A 3 HI-506A A 2 I 1 +10V V AH = 4.0V A 1 A 0 I 2 THRU I 7/I 15 I 8 /I 16 50% 50% EABLE DRIVE (V A ) 0V V A 50 E GD V 50pF 90% UT 10% 0V Similar connection for HI-507A//HI-508A/HI-509A t O(E) t OFF(E) FIGURE 8A. TEST CIRCUIT FIGURE 8B. MEASUREMET OITS EABLE DRIVE 2V/DIV. DISABLED EABLED (S 1 O) UT 2V/DIV. 100ns/DIV. FIGURE 8C. WAVEFORMS FIGURE 8. EABLE DELAYS F3143 Rev.6.00 age 14 of 20

15 Die Characteristics DIE DIMESIOS: 159 mils x 83.9 mils METALLIZATIO: Type: CuAl Thickness: 16kÅ 2kÅ SUBSTRATE OTETIAL (OTE): -V SULY WORST CASE CURRET DESITY: 1.4 x 10 5 A/cm 2 TRASISTOR C: 485 ROCESS: CMOS-DI ASSIVATIO: Silox: 12kÅ 2kÅ itride: 3.5kÅ Å OTE: The substrate appears resistive to the -V SULY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SULY potential. Metallization Mask Layouts HI-506A E A 0 A 1 A 2 A 3 V REF GD (18) (17) (16) (15) (14) (13) (12) HI-507A E A 0 A 1 A 2 C V REF GD (18) (17) (16) (15) (14) (13) (12) I 1 (19) I 2 (20) I 9 (11) I 10 (10) I 1A (19) I 2A (20) I 1B (11) I 2B (10) I 3 (21) I 4 (22) I 11 (9) I 12 (8) I 3A (21) I 4A (22) I 3B (9) I 4B (8) I 5 (23) I 6 (24) I 13 (7) I 14 (6) I 5A (23) I 6A (24) I 5B (7) I 6B (6) I 7 (25) I 15 (5) I 8 I 16 (26) (4) I 7A (25) I 7B (5) I 8A I 8B (26) (4) V- (27) (28) +V (1) C (2) V- (27) A (28) +V (1) B(2) F3143 Rev.6.00 age 15 of 20

16 Die Characteristics DIE DIMESIOS: 108 mils x 83 mils METALLIZATIO: Type: CuAl Thickness: 16kÅ 2kÅ SUBSTRATE OTETIAL (OTE): -V SULY WORST CASE CURRET DESITY: 1.4 x 10 5 A/cm 2 TRASISTOR C: 253 ROCESS: CMOS-DI ASSIVATIO: Silox: 12kÅ 2kÅ itride: 3.5kÅ Å OTE: The substrate appears resistive to the -V SULY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SULY potential. Metallization Mask Layouts HI-508A HI-509A I 6 I 7 I 8 I 4 I 3 (11) (10) (9) (8) (7) (6) I 3B I 4B B A I 4A I 3A (11) (10) (9) (8) (7) (6) I 5 (12) +V (13) GD (14) I 2 (5) I 1 (4) -V (3) I 2B (12) I 1B (13) +V (14) I 2A (5) I 1A (4) -V (3) A 2 A 1 A 0 E (15) (16) (1) (2) GD A 1 A 0 E (15) (16) (1) (2) F3143 Rev.6.00 age 16 of 20

17 Ceramic Dual-In-Line Frit Seal ackages (CERDI) BASE LAE SEATIG LAE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- OTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1,, /2, and /2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ASI Y14.5M Controlling dimension: ICH. E L M c1 ea/2 S D S aaa M C A - B LEAD FIISH BASE METAL b1 M (b) SECTIO A-A S ea c D S (c) F28.6 MIL-STD-1835 GDI1-T28 (D-10, COFIGURATIO A) 28 LEAD CERAMIC DUAL-I-LIE FRIT SEAL ACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A b b b b c c D E e BSC 2.54 BSC - ea BSC BSC - ea/ BSC 7.62 BSC - L Q S o 105 o 90 o 105 o - aaa bbb ccc M , Rev. 0 4/94 F3143 Rev.6.00 age 17 of 20

18 Dual-In-Line lastic ackages (DI) IDEX AREA BASE LAE SEATIG LAE D1 B1 -C- -A /2 B D e D1 E1 OTES: 1. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ASI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of ublication o Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. is the maximum number of terminal positions. 10. Corner leads (1,, /2 and /2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). -B- A (0.25) M C A A2 L B S A e C E C L e A C e B E28.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-I-LIE LASTIC ACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B C D D E E e BSC 2.54 BSC - e A BSC BSC 6 e B L Rev. 1 12/00 F3143 Rev.6.00 age 18 of 20

19 Ceramic Dual-In-Line Frit Seal ackages (CERDI) BASE LAE SEATIG LAE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- OTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1,, /2, and /2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ASI Y14.5M Controlling dimension: ICH. E L M c1 ea/2 S D S aaa M C A - B LEAD FIISH BASE METAL b1 M (b) SECTIO A-A S ea c D S (c) F16.3 MIL-STD-1835 GDI1-T16 (D-2, COFIGURATIO A) 16 LEAD CERAMIC DUAL-I-LIE FRIT SEAL ACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A b b b b c c D E e BSC 2.54 BSC - ea BSC 7.62 BSC - ea/ BSC 3.81 BSC - L Q S o 105 o 90 o 105 o - aaa bbb ccc M , Rev. 0 4/94 F3143 Rev.6.00 age 19 of 20

20 Dual-In-Line lastic ackages (DI) IDEX AREA BASE LAE SEATIG LAE D1 B1 -C- -A /2 B D e D1 E1 OTES: 1. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ASI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of ublication o Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. is the maximum number of terminal positions. 10. Corner leads (1,, /2 and /2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). -B- A (0.25) M C A A2 L B S A e C E C L e A C e B E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-I-LIE LASTIC ACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B , 10 C D D E E e BSC 2.54 BSC - e A BSC 7.62 BSC 6 e B L Rev. 0 12/93 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see F3143 Rev.6.00 age 20 of 20

DATASHEET HI-518. Features. Ordering Information. Applications. Pinout. 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer

DATASHEET HI-518. Features. Ordering Information. Applications. Pinout. 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer DATASHEET HI-518 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer F3147 Rev 4.00 The Hl-518 is a monolithic, dielectrically isolated, high speed, high performance CMOS analog multiplexer.